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RTSD
HDL
Commits
8aedf4e1
Commit
8aedf4e1
authored
4 years ago
by
Pieter Donker
Browse files
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L2SDP-246
, backup
parent
193b3300
No related branches found
No related tags found
2 merge requests
!100
Removed text for XSub that is now written in Confluence Subband correlator...
,
!83
Resolve L2SDP-246
Changes
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applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_sst_offload.vhd
+88
-120
88 additions, 120 deletions
...erbank/tb/vhdl/tb_lofar2_unb2b_filterbank_sst_offload.vhd
with
88 additions
and
120 deletions
applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_sst_offload.vhd
+
88
−
120
View file @
8aedf4e1
...
@@ -17,7 +17,7 @@
...
@@ -17,7 +17,7 @@
-- limitations under the License.
-- limitations under the License.
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Test statistics offload with "ethernet packet statistics" in wave window only
-- Usage:
-- Usage:
-- > as 7 # default
-- > as 7 # default
-- > as 12 # for detailed debugging
-- > as 12 # for detailed debugging
...
@@ -50,7 +50,6 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_filterbank_sst_offload IS
...
@@ -50,7 +50,6 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_filterbank_sst_offload IS
CONSTANT
c_node_nr
:
NATURAL
:
=
0
;
CONSTANT
c_node_nr
:
NATURAL
:
=
0
;
CONSTANT
c_id
:
STD_LOGIC_VECTOR
(
7
DOWNTO
0
)
:
=
"00000000"
;
CONSTANT
c_id
:
STD_LOGIC_VECTOR
(
7
DOWNTO
0
)
:
=
"00000000"
;
CONSTANT
c_version
:
STD_LOGIC_VECTOR
(
1
DOWNTO
0
)
:
=
"00"
;
CONSTANT
c_version
:
STD_LOGIC_VECTOR
(
1
DOWNTO
0
)
:
=
"00"
;
CONSTANT
c_fw_version
:
t_unb2b_board_fw_version
:
=
(
1
,
0
);
CONSTANT
c_eth_clk_period
:
TIME
:
=
8
ns
;
-- 125 MHz XO on UniBoard
CONSTANT
c_eth_clk_period
:
TIME
:
=
8
ns
;
-- 125 MHz XO on UniBoard
CONSTANT
c_ext_clk_period
:
TIME
:
=
5
ns
;
CONSTANT
c_ext_clk_period
:
TIME
:
=
5
ns
;
...
@@ -62,14 +61,6 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_filterbank_sst_offload IS
...
@@ -62,14 +61,6 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_filterbank_sst_offload IS
CONSTANT
c_nof_block_per_sync
:
NATURAL
:
=
16
;
CONSTANT
c_nof_block_per_sync
:
NATURAL
:
=
16
;
CONSTANT
c_wpfb_sim
:
t_wpfb
:
=
func_wpfb_set_nof_block_per_sync
(
c_sdp_wpfb_subbands
,
c_nof_block_per_sync
);
CONSTANT
c_wpfb_sim
:
t_wpfb
:
=
func_wpfb_set_nof_block_per_sync
(
c_sdp_wpfb_subbands
,
c_nof_block_per_sync
);
-- ETH
CONSTANT
c_dst_mac_hi
:
INTEGER
:
=
16
#
00001234
#
;
CONSTANT
c_dst_mac_lo
:
INTEGER
:
=
16
#
56789
ABC
#
;
CONSTANT
c_dst_mac
:
STD_LOGIC_VECTOR
(
47
DOWNTO
0
)
:
=
TO_UVEC
(
c_dst_mac_hi
,
16
)
&
TO_UVEC
(
c_dst_mac_lo
,
32
);
-- = X"123456789ABC";
CONSTANT
c_src_mac_hi
:
INTEGER
:
=
16
#
00228608
#
;
CONSTANT
c_src_mac_lo
:
INTEGER
:
=
c_unb_nr
*
256
+
c_node_nr
;
CONSTANT
c_src_mac
:
STD_LOGIC_VECTOR
(
47
DOWNTO
0
)
:
=
TO_UVEC
(
c_src_mac_hi
,
32
)
&
TO_UVEC
(
c_src_mac_lo
,
16
);
-- = X"00228608" & unb & fpga;
-- WG
-- WG
CONSTANT
c_full_scale_ampl
:
REAL
:
=
REAL
(
2
**
(
18-1
)
-1
);
-- = full scale of WG
CONSTANT
c_full_scale_ampl
:
REAL
:
=
REAL
(
2
**
(
18-1
)
-1
);
-- = full scale of WG
CONSTANT
c_bsn_start_wg
:
NATURAL
:
=
2
;
-- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
CONSTANT
c_bsn_start_wg
:
NATURAL
:
=
2
;
-- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
...
@@ -80,11 +71,11 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_filterbank_sst_offload IS
...
@@ -80,11 +71,11 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_filterbank_sst_offload IS
CONSTANT
c_wg_ampl_lsb
:
REAL
:
=
c_diag_wg_ampl_unit
/
c_full_scale_ampl
;
-- amplitude in number of LSbit resolution steps
CONSTANT
c_wg_ampl_lsb
:
REAL
:
=
c_diag_wg_ampl_unit
/
c_full_scale_ampl
;
-- amplitude in number of LSbit resolution steps
-- . 1GbE output
-- . 1GbE output
CONSTANT
c_eth_check_nof_packets
:
NATURAL
:
=
1024
;
--
FXME
CONSTANT
c_eth_check_nof_packets
:
NATURAL
:
=
4512
;
--
received packets in 2 sync periods
CONSTANT
c_eth_header_size
:
NATURAL
:
=
4
0
;
--
FIXME (
pad(2) + eth(14) + ip(20) + udp(8)
+ app(16+24))/4 = 84 / 4
CONSTANT
c_eth_header_size
:
NATURAL
:
=
4
4
;
-- pad(2) + eth(14) + ip(20) + udp(8)
CONSTANT
c_udp_payload_size
:
NATURAL
:
=
41
04
;
--
FIXME
CONSTANT
c_udp_payload_size
:
NATURAL
:
=
41
28
;
--
udp payload 32 + 4096
CONSTANT
c_eth_packet_size
:
NATURAL
:
=
c_eth_header_size
+
c_udp_payload_size
;
CONSTANT
c_eth_packet_size
:
NATURAL
:
=
c_eth_header_size
+
c_udp_payload_size
;
CONSTANT
c_eth_runtime_timeout
:
TIME
:
=
5
00
ms
;
-- factor 2 margin
CONSTANT
c_eth_runtime_timeout
:
TIME
:
=
1
00
ms
;
-- factor 2 margin
-- MM
-- MM
CONSTANT
c_mm_file_reg_bsn_source
:
STRING
:
=
mmf_unb_file_prefix
(
c_unb_nr
,
c_node_nr
)
&
"REG_BSN_SOURCE"
;
CONSTANT
c_mm_file_reg_bsn_source
:
STRING
:
=
mmf_unb_file_prefix
(
c_unb_nr
,
c_node_nr
)
&
"REG_BSN_SOURCE"
;
...
@@ -130,12 +121,10 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_filterbank_sst_offload IS
...
@@ -130,12 +121,10 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_filterbank_sst_offload IS
BEGIN
BEGIN
----------------------------------------------------------------------------
-- System setup
-- System setup
----------------------------------------------------------------------------
ext_clk
<=
(
NOT
ext_clk
)
OR
tb_end
AFTER
c_ext_clk_period
/
2
;
-- External clock (200 MHz)
ext_clk
<=
NOT
ext_clk
AFTER
c_ext_clk_period
/
2
;
-- External clock (200 MHz)
eth_clk
<=
(
NOT
eth_clk
)
OR
tb_end
AFTER
c_eth_clk_period
/
2
;
-- Ethernet ref clock (125 MHz)
eth_clk
<=
NOT
eth_clk
AFTER
c_eth_clk_period
/
2
;
-- Ethernet ref clock (125 MHz)
JESD204B_REFCLK
<=
(
NOT
JESD204B_REFCLK
)
OR
tb_end
AFTER
c_bck_ref_clk_period
/
2
;
-- JESD sample clock (200MHz)
JESD204B_REFCLK
<=
NOT
JESD204B_REFCLK
AFTER
c_bck_ref_clk_period
/
2
;
-- JESD sample clock (200MHz)
INTA
<=
'H'
;
-- pull up
INTA
<=
'H'
;
-- pull up
INTB
<=
'H'
;
-- pull up
INTB
<=
'H'
;
-- pull up
...
@@ -145,16 +134,12 @@ BEGIN
...
@@ -145,16 +134,12 @@ BEGIN
pmbus_scl
<=
'H'
;
-- pull up
pmbus_scl
<=
'H'
;
-- pull up
pmbus_sda
<=
'H'
;
-- pull up
pmbus_sda
<=
'H'
;
-- pull up
------------------------------------------------------------------------------
-- External PPS
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse
(
10
,
c_pps_period
,
'1'
,
pps_rst
,
ext_clk
,
pps
);
proc_common_gen_pulse
(
10
,
c_pps_period
,
'1'
,
pps_rst
,
ext_clk
,
pps
);
jesd204b_sysref
<=
pps
;
jesd204b_sysref
<=
pps
;
ext_pps
<=
pps
;
ext_pps
<=
pps
;
------------------------------------------------------------------------------
-- >> DUT <<
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_filterbank
:
ENTITY
work
.
lofar2_unb2b_filterbank
u_lofar_unb2b_filterbank
:
ENTITY
work
.
lofar2_unb2b_filterbank
GENERIC
MAP
(
GENERIC
MAP
(
g_design_name
=>
"lofar2_unb2b_filterbank_full"
,
g_design_name
=>
"lofar2_unb2b_filterbank_full"
,
...
@@ -203,12 +188,8 @@ BEGIN
...
@@ -203,12 +188,8 @@ BEGIN
JESD204B_SYNC_N
=>
jesd204b_sync_n
JESD204B_SYNC_N
=>
jesd204b_sync_n
);
);
------------------------------------------------------------------------------
-- MM slave accesses via file IO
-- MM slave accesses via file IO
------------------------------------------------------------------------------
tb_clk
<=
(
NOT
tb_clk
)
OR
tb_end
AFTER
c_tb_clk_period
/
2
;
-- Testbench MM clock
tb_clk
<=
NOT
tb_clk
AFTER
c_tb_clk_period
/
2
;
-- Testbench MM clock
p_mm_stimuli
:
PROCESS
p_mm_stimuli
:
PROCESS
CONSTANT
c_mm_file_reg_stat_enable
:
STRING
:
=
mmf_unb_file_prefix
(
c_unb_nr
,
c_node_nr
)
&
"REG_STAT_ENABLE"
;
CONSTANT
c_mm_file_reg_stat_enable
:
STRING
:
=
mmf_unb_file_prefix
(
c_unb_nr
,
c_node_nr
)
&
"REG_STAT_ENABLE"
;
...
@@ -220,19 +201,13 @@ BEGIN
...
@@ -220,19 +201,13 @@ BEGIN
proc_common_wait_until_hi_lo
(
ext_clk
,
ext_pps
);
proc_common_wait_until_hi_lo
(
ext_clk
,
ext_pps
);
----------------------------------------------------------------------------
-- Enable BS
-- Enable BS
----------------------------------------------------------------------------
mmf_mm_bus_wr
(
c_mm_file_reg_bsn_source
,
3
,
0
,
tb_clk
);
mmf_mm_bus_wr
(
c_mm_file_reg_bsn_source
,
3
,
0
,
tb_clk
);
mmf_mm_bus_wr
(
c_mm_file_reg_bsn_source
,
2
,
1
,
tb_clk
);
-- Init BSN = 0
mmf_mm_bus_wr
(
c_mm_file_reg_bsn_source
,
2
,
1
,
tb_clk
);
-- Init BSN = 0
mmf_mm_bus_wr
(
c_mm_file_reg_bsn_source
,
1
,
c_nof_block_per_sync
,
tb_clk
);
-- nof_block_per_sync
mmf_mm_bus_wr
(
c_mm_file_reg_bsn_source
,
1
,
c_nof_block_per_sync
,
tb_clk
);
-- nof_block_per_sync
mmf_mm_bus_wr
(
c_mm_file_reg_bsn_source
,
0
,
16
#
00000003
#
,
tb_clk
);
-- Enable BS at PPS
mmf_mm_bus_wr
(
c_mm_file_reg_bsn_source
,
0
,
16
#
00000003
#
,
tb_clk
);
-- Enable BS at PPS
----------------------------------------------------------------------------
-- Enable WG
-- Enable WG
----------------------------------------------------------------------------
-- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3)
-- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3)
-- nof_samples[31:16] --> <= c_ram_wg_size=1024
-- nof_samples[31:16] --> <= c_ram_wg_size=1024
-- 1 : phase[15:0]
-- 1 : phase[15:0]
...
@@ -259,34 +234,27 @@ BEGIN
...
@@ -259,34 +234,27 @@ BEGIN
WAIT
FOR
c_sdp_T_sub
*
c_sdp_N_taps
;
WAIT
FOR
c_sdp_T_sub
*
c_sdp_N_taps
;
WAIT
FOR
c_sdp_T_sub
*
2
;
WAIT
FOR
c_sdp_T_sub
*
2
;
-- Offload enable
-- Offload enable
mmf_mm_bus_wr
(
c_mm_file_reg_stat_enable
,
0
,
1
,
tb_clk
);
mmf_mm_bus_wr
(
c_mm_file_reg_stat_enable
,
0
,
1
,
tb_clk
);
proc_common_wait_some_cycles
(
ext_clk
,
50000
);
---------------------------------------------------------------------------
-- End Simulation
-- End Simulation
---------------------------------------------------------------------------
proc_common_wait_until_high
(
ext_clk
,
eth_done
);
sim_done
<=
'1'
;
proc_common_wait_some_cycles
(
ext_clk
,
100
);
proc_common_stop_simulation
(
TRUE
,
ext_clk
,
eth_done
,
tb_end
);
WAIT
;
WAIT
;
END
PROCESS
;
END
PROCESS
;
------------------------------------------------------------------------------
-- >> Verify proper DUT output using Ethernet packet statistics <<
-- Verify proper DUT output using Ethernet packet statistics
------------------------------------------------------------------------------
u_eth_statistics
:
ENTITY
eth_lib
.
eth_statistics
u_eth_statistics
:
ENTITY
eth_lib
.
eth_statistics
GENERIC
MAP
(
GENERIC
MAP
(
g_runtime_nof_packets
=>
c_eth_check_nof_packets
,
g_runtime_nof_packets
=>
c_eth_check_nof_packets
,
g_runtime_timeout
=>
c_eth_runtime_timeout
,
g_runtime_timeout
=>
c_eth_runtime_timeout
,
g_check_nof_valid
=>
TRUE
,
g_check_nof_valid
=>
TRUE
,
g_check_nof_valid_ref
=>
c_eth_check_nof_packets
*
c_eth_packet_size
g_check_nof_valid_ref
=>
c_eth_check_nof_packets
--
*c_eth_packet_size
)
)
PORT
MAP
(
PORT
MAP
(
eth_serial_in
=>
eth_txp
(
0
),
eth_serial_in
=>
eth_txp
(
0
),
tb_end
=>
eth_done
tb_end
=>
eth_done
);
);
verify_done
<=
eth_done
AND
sim_done
;
proc_common_stop_simulation
(
TRUE
,
ext_clk
,
sim_done
,
tb_end
);
END
tb
;
END
tb
;
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