diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_sst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_sst_offload.vhd index 0c3b1c322af3c6b2ebf90ec02d177b351981b69d..6b7f2546830ef6b6a08ea5363213505a07d496d1 100644 --- a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_sst_offload.vhd +++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_sst_offload.vhd @@ -17,7 +17,7 @@ -- limitations under the License. -- ------------------------------------------------------------------------------- - +-- Test statistics offload with "ethernet packet statistics" in wave window only -- Usage: -- > as 7 # default -- > as 12 # for detailed debugging @@ -45,46 +45,37 @@ END tb_lofar2_unb2b_filterbank_sst_offload; ARCHITECTURE tb OF tb_lofar2_unb2b_filterbank_sst_offload IS - CONSTANT c_sim : BOOLEAN := TRUE; - CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0 - CONSTANT c_node_nr : NATURAL := 0; - CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; - CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; - CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0); + CONSTANT c_sim : BOOLEAN := TRUE; + CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0 + CONSTANT c_node_nr : NATURAL := 0; + CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; - CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard - CONSTANT c_ext_clk_period : TIME := 5 ns; - CONSTANT c_bck_ref_clk_period : TIME := 5 ns; - CONSTANT c_pps_period : NATURAL := 1000; + CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard + CONSTANT c_ext_clk_period : TIME := 5 ns; + CONSTANT c_bck_ref_clk_period : TIME := 5 ns; + CONSTANT c_pps_period : NATURAL := 1000; - CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C + CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C - CONSTANT c_nof_block_per_sync : NATURAL := 16; - CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync); + CONSTANT c_nof_block_per_sync : NATURAL := 16; + CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync); - -- ETH - CONSTANT c_dst_mac_hi : INTEGER := 16#00001234#; - CONSTANT c_dst_mac_lo : INTEGER := 16#56789ABC#; - CONSTANT c_dst_mac : STD_LOGIC_VECTOR(47 DOWNTO 0) := TO_UVEC(c_dst_mac_hi, 16) & TO_UVEC(c_dst_mac_lo, 32); -- = X"123456789ABC"; - CONSTANT c_src_mac_hi : INTEGER := 16#00228608#; - CONSTANT c_src_mac_lo : INTEGER := c_unb_nr * 256 + c_node_nr; - CONSTANT c_src_mac : STD_LOGIC_VECTOR(47 DOWNTO 0) := TO_UVEC(c_src_mac_hi, 32) & TO_UVEC(c_src_mac_lo, 16); -- = X"00228608" & unb & fpga; - -- WG - CONSTANT c_full_scale_ampl : REAL := REAL(2**(18-1)-1); -- = full scale of WG - CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values - CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/2; -- in number of lsb - CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus - CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit - CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz - CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps + CONSTANT c_full_scale_ampl : REAL := REAL(2**(18-1)-1); -- = full scale of WG + CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values + CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/2; -- in number of lsb + CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus + CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit + CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz + CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps -- . 1GbE output - CONSTANT c_eth_check_nof_packets : NATURAL := 1024; -- FXME - CONSTANT c_eth_header_size : NATURAL := 40; -- FIXME (pad(2) + eth(14) + ip(20) + udp(8) + app(16+24))/4 = 84 / 4 - CONSTANT c_udp_payload_size : NATURAL := 4104; -- FIXME - CONSTANT c_eth_packet_size : NATURAL := c_eth_header_size + c_udp_payload_size; - CONSTANT c_eth_runtime_timeout : TIME := 500 ms; -- factor 2 margin + CONSTANT c_eth_check_nof_packets : NATURAL := 4512; -- received packets in 2 sync periods + CONSTANT c_eth_header_size : NATURAL := 44; -- pad(2) + eth(14) + ip(20) + udp(8) + CONSTANT c_udp_payload_size : NATURAL := 4128; -- udp payload 32 + 4096 + CONSTANT c_eth_packet_size : NATURAL := c_eth_header_size + c_udp_payload_size; + CONSTANT c_eth_runtime_timeout : TIME := 100 ms; -- factor 2 margin -- MM CONSTANT c_mm_file_reg_bsn_source : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE"; @@ -92,69 +83,63 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_filterbank_sst_offload IS CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG"; -- Tb - SIGNAL tb_end : STD_LOGIC := '0'; - SIGNAL sim_done : STD_LOGIC := '0'; - SIGNAL eth_done : STD_LOGIC := '0'; - SIGNAL verify_done : STD_LOGIC := '0'; - SIGNAL tb_clk : STD_LOGIC := '0'; + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL sim_done : STD_LOGIC := '0'; + SIGNAL eth_done : STD_LOGIC := '0'; + SIGNAL verify_done : STD_LOGIC := '0'; + SIGNAL tb_clk : STD_LOGIC := '0'; -- WG - SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0); + SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0); -- DUT - SIGNAL ext_clk : STD_LOGIC := '0'; - SIGNAL pps : STD_LOGIC := '0'; - SIGNAL ext_pps : STD_LOGIC := '0'; - SIGNAL pps_rst : STD_LOGIC := '0'; + SIGNAL ext_clk : STD_LOGIC := '0'; + SIGNAL pps : STD_LOGIC := '0'; + SIGNAL ext_pps : STD_LOGIC := '0'; + SIGNAL pps_rst : STD_LOGIC := '0'; - SIGNAL WDI : STD_LOGIC; - SIGNAL INTA : STD_LOGIC; - SIGNAL INTB : STD_LOGIC; + SIGNAL WDI : STD_LOGIC; + SIGNAL INTA : STD_LOGIC; + SIGNAL INTB : STD_LOGIC; - SIGNAL eth_clk : STD_LOGIC := '0'; - SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0); - SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0); + SIGNAL eth_clk : STD_LOGIC := '0'; + SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0); + SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0); - SIGNAL sens_scl : STD_LOGIC; - SIGNAL sens_sda : STD_LOGIC; - SIGNAL pmbus_scl : STD_LOGIC; - SIGNAL pmbus_sda : STD_LOGIC; + SIGNAL sens_scl : STD_LOGIC; + SIGNAL sens_sda : STD_LOGIC; + SIGNAL pmbus_scl : STD_LOGIC; + SIGNAL pmbus_sda : STD_LOGIC; -- back transceivers SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0); SIGNAL JESD204B_REFCLK : STD_LOGIC := '1'; -- jesd204b syncronization signals - SIGNAL jesd204b_sysref : STD_LOGIC; - SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0); + SIGNAL jesd204b_sysref : STD_LOGIC; + SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0); BEGIN - ---------------------------------------------------------------------------- -- System setup - ---------------------------------------------------------------------------- - ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz) - eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz) - JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz) + ext_clk <= (NOT ext_clk) OR tb_end AFTER c_ext_clk_period/2; -- External clock (200 MHz) + eth_clk <= (NOT eth_clk) OR tb_end AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz) + JESD204B_REFCLK <= (NOT JESD204B_REFCLK) OR tb_end AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz) INTA <= 'H'; -- pull up INTB <= 'H'; -- pull up - sens_scl <= 'H'; -- pull up - sens_sda <= 'H'; -- pull up + sens_scl <= 'H'; -- pull up + sens_sda <= 'H'; -- pull up pmbus_scl <= 'H'; -- pull up pmbus_sda <= 'H'; -- pull up - ------------------------------------------------------------------------------ -- External PPS - ------------------------------------------------------------------------------ proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps); jesd204b_sysref <= pps; ext_pps <= pps; - ------------------------------------------------------------------------------ - -- DUT - ------------------------------------------------------------------------------ + -- >> DUT << u_lofar_unb2b_filterbank : ENTITY work.lofar2_unb2b_filterbank GENERIC MAP ( g_design_name => "lofar2_unb2b_filterbank_full", @@ -167,81 +152,71 @@ BEGIN ) PORT MAP ( -- GENERAL - CLK => ext_clk, - PPS => pps, - WDI => WDI, - INTA => INTA, - INTB => INTB, + CLK => ext_clk, + PPS => pps, + WDI => WDI, + INTA => INTA, + INTB => INTB, -- Others - VERSION => c_version, - ID => c_id, - TESTIO => open, + VERSION => c_version, + ID => c_id, + TESTIO => open, -- I2C Interface to Sensors - SENS_SC => sens_scl, - SENS_SD => sens_sda, + SENS_SC => sens_scl, + SENS_SD => sens_sda, - PMBUS_SC => pmbus_scl, - PMBUS_SD => pmbus_sda, - PMBUS_ALERT => open, + PMBUS_SC => pmbus_scl, + PMBUS_SD => pmbus_sda, + PMBUS_ALERT => open, -- 1GbE Control Interface - ETH_CLK => eth_clk, - ETH_SGIN => eth_rxp, - ETH_SGOUT => eth_txp, + ETH_CLK => eth_clk, + ETH_SGIN => eth_rxp, + ETH_SGOUT => eth_txp, -- LEDs - QSFP_LED => open, + QSFP_LED => open, -- back transceivers JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA, JESD204B_REFCLK => JESD204B_REFCLK, -- jesd204b syncronization signals - JESD204B_SYSREF => jesd204b_sysref, - JESD204B_SYNC_N => jesd204b_sync_n + JESD204B_SYSREF => jesd204b_sysref, + JESD204B_SYNC_N => jesd204b_sync_n ); - - - ------------------------------------------------------------------------------ -- MM slave accesses via file IO - ------------------------------------------------------------------------------ - tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock + tb_clk <= (NOT tb_clk) OR tb_end AFTER c_tb_clk_period/2; -- Testbench MM clock p_mm_stimuli : PROCESS - CONSTANT c_mm_file_reg_stat_enable : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE"; - CONSTANT c_mm_file_reg_stat_hdr_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_HDR_INFO"; - VARIABLE v_bsn : NATURAL; + CONSTANT c_mm_file_reg_stat_enable : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE"; + CONSTANT c_mm_file_reg_stat_hdr_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_HDR_INFO"; + VARIABLE v_bsn : NATURAL; BEGIN -- Wait for DUT power up after reset WAIT FOR 1 us; proc_common_wait_until_hi_lo(ext_clk, ext_pps); - - ---------------------------------------------------------------------------- -- Enable BS - ---------------------------------------------------------------------------- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3, 0, tb_clk); mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 1, tb_clk); -- Init BSN = 0 mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk); -- nof_block_per_sync mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk); -- Enable BS at PPS - - ---------------------------------------------------------------------------- -- Enable WG - ---------------------------------------------------------------------------- -- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3) -- nof_samples[31:16] --> <= c_ram_wg_size=1024 -- 1 : phase[15:0] -- 2 : freq[30:0] -- 3 : ampl[16:0] - mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc - mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, INTEGER( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees - mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER((c_subband_sp_0+c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq - mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, INTEGER(REAL(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl + mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc + mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, INTEGER( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees + mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER((c_subband_sp_0 + c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq + mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, INTEGER(REAL(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl -- Read current BSN mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk); @@ -256,37 +231,30 @@ BEGIN mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1 -- Wait for ADUH monitor to have filled with WG data - WAIT FOR c_sdp_T_sub*c_sdp_N_taps; - WAIT FOR c_sdp_T_sub*2; + WAIT FOR c_sdp_T_sub * c_sdp_N_taps; + WAIT FOR c_sdp_T_sub * 2; - -- Offload enable mmf_mm_bus_wr(c_mm_file_reg_stat_enable, 0, 1, tb_clk); - proc_common_wait_some_cycles(ext_clk, 50000); - --------------------------------------------------------------------------- - -- End Simulation - --------------------------------------------------------------------------- - sim_done <= '1'; + -- End Simulation + proc_common_wait_until_high(ext_clk, eth_done); + proc_common_wait_some_cycles(ext_clk, 100); + proc_common_stop_simulation(TRUE, ext_clk, eth_done, tb_end); WAIT; END PROCESS; - ------------------------------------------------------------------------------ - -- Verify proper DUT output using Ethernet packet statistics - ------------------------------------------------------------------------------ + -- >> Verify proper DUT output using Ethernet packet statistics << u_eth_statistics : ENTITY eth_lib.eth_statistics GENERIC MAP ( g_runtime_nof_packets => c_eth_check_nof_packets, g_runtime_timeout => c_eth_runtime_timeout, g_check_nof_valid => TRUE, - g_check_nof_valid_ref => c_eth_check_nof_packets*c_eth_packet_size + g_check_nof_valid_ref => c_eth_check_nof_packets -- *c_eth_packet_size ) PORT MAP ( eth_serial_in => eth_txp(0), tb_end => eth_done ); - verify_done <= eth_done AND sim_done; - proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end); - END tb;