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Commit 8a503bd3 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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added the tx_seq and rx_seq (BG, DB)

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boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream.vhd
+ 39
− 29
View file @ 8a503bd3
...@@ -45,8 +45,8 @@ ENTITY ddr_stream IS ...@@ -45,8 +45,8 @@ ENTITY ddr_stream IS
g_nof_streams : NATURAL; g_nof_streams : NATURAL;
g_data_w : NATURAL; g_data_w : NATURAL;
g_bg_block_size : NATURAL := 900; g_bg_block_size : NATURAL := 1024;
g_bg_gapsize : NATURAL := 100; g_bg_gapsize : NATURAL := 0;
g_bg_blocks_per_sync : NATURAL := 200000; g_bg_blocks_per_sync : NATURAL := 200000;
g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master; g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
...@@ -55,40 +55,44 @@ ENTITY ddr_stream IS ...@@ -55,40 +55,44 @@ ENTITY ddr_stream IS
); );
PORT ( PORT (
-- System -- System
mm_rst : IN STD_LOGIC; mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC; mm_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC; dp_rst : IN STD_LOGIC;
dp_clk : IN STD_LOGIC; dp_clk : IN STD_LOGIC;
-- blockgen mm -- blockgen mm
reg_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG control register (one for all streams) reg_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG control register (one for all streams)
reg_diag_bg_miso : OUT t_mem_miso; reg_diag_bg_miso : OUT t_mem_miso;
ram_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG buffer RAM (one per stream) ram_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG buffer RAM (one per stream)
ram_diag_bg_miso : OUT t_mem_miso; ram_diag_bg_miso : OUT t_mem_miso;
reg_diag_tx_seq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_diag_tx_seq_miso : OUT t_mem_miso;
-- bsn -- bsn
reg_bsn_monitor_mosi : IN t_mem_mosi; reg_bsn_monitor_mosi : IN t_mem_mosi;
reg_bsn_monitor_miso : OUT t_mem_miso; reg_bsn_monitor_miso : OUT t_mem_miso;
-- databuffer -- databuffer
reg_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst; reg_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_diag_data_buf_miso : OUT t_mem_miso; reg_diag_data_buf_miso : OUT t_mem_miso;
ram_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst; ram_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_diag_data_buf_miso : OUT t_mem_miso; ram_diag_data_buf_miso : OUT t_mem_miso;
reg_diag_rx_seq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_diag_rx_seq_miso : OUT t_mem_miso;
-- IO DDR register map -- IO DDR register map
reg_io_ddr_mosi : IN t_mem_mosi; reg_io_ddr_mosi : IN t_mem_mosi;
reg_io_ddr_miso : OUT t_mem_miso; reg_io_ddr_miso : OUT t_mem_miso;
-- Reorder transpose -- Reorder transpose
ram_ss_ss_transp_mosi : IN t_mem_mosi; ram_ss_ss_transp_mosi : IN t_mem_mosi;
ram_ss_ss_transp_miso : OUT t_mem_miso; ram_ss_ss_transp_miso : OUT t_mem_miso;
-- SO-DIMM Memory Bank I -- SO-DIMM Memory Bank I
MB_I_IN : IN t_tech_ddr3_phy_in; MB_I_IN : IN t_tech_ddr3_phy_in;
MB_I_IO : INOUT t_tech_ddr3_phy_io; MB_I_IO : INOUT t_tech_ddr3_phy_io;
MB_I_OU : OUT t_tech_ddr3_phy_ou MB_I_OU : OUT t_tech_ddr3_phy_ou
); );
END ddr_stream; END ddr_stream;
...@@ -149,8 +153,9 @@ BEGIN ...@@ -149,8 +153,9 @@ BEGIN
g_buf_dat_w => g_data_w, g_buf_dat_w => g_data_w,
g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)), g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
g_file_index_arr => array_init(0, g_nof_streams), g_file_index_arr => array_init(0, g_nof_streams),
g_file_name_prefix => "../../counter_data_" & NATURAL'IMAGE(g_data_w), g_file_name_prefix => "hex/counter_data_" & NATURAL'IMAGE(g_data_w),
g_diag_block_gen_rst => c_bg_ctrl g_diag_block_gen_rst => c_bg_ctrl,
g_use_tx_seq => TRUE
) )
PORT MAP ( PORT MAP (
mm_rst => mm_rst, mm_rst => mm_rst,
...@@ -166,7 +171,9 @@ BEGIN ...@@ -166,7 +171,9 @@ BEGIN
reg_bg_ctrl_mosi => reg_diag_bg_mosi, reg_bg_ctrl_mosi => reg_diag_bg_mosi,
reg_bg_ctrl_miso => reg_diag_bg_miso, reg_bg_ctrl_miso => reg_diag_bg_miso,
ram_bg_data_mosi => ram_diag_bg_mosi, ram_bg_data_mosi => ram_diag_bg_mosi,
ram_bg_data_miso => ram_diag_bg_miso ram_bg_data_miso => ram_diag_bg_miso,
reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
reg_tx_seq_miso => reg_diag_tx_seq_miso
); );
...@@ -199,7 +206,8 @@ BEGIN ...@@ -199,7 +206,8 @@ BEGIN
g_nof_streams => g_nof_streams, g_nof_streams => g_nof_streams,
g_data_w => 32, --g_data_w, --FIXME g_data_w => 32, --g_data_w, --FIXME
g_buf_nof_data => 1024, g_buf_nof_data => 1024,
g_buf_use_sync => FALSE -- sync by reading last address of data buffer g_buf_use_sync => FALSE, -- sync by reading last address of data buffer
g_use_rx_seq => TRUE
) )
PORT MAP ( PORT MAP (
mm_rst => mm_rst, mm_rst => mm_rst,
...@@ -211,6 +219,8 @@ BEGIN ...@@ -211,6 +219,8 @@ BEGIN
ram_data_buf_miso => ram_diag_data_buf_miso, ram_data_buf_miso => ram_diag_data_buf_miso,
reg_data_buf_mosi => reg_diag_data_buf_mosi, reg_data_buf_mosi => reg_diag_data_buf_mosi,
reg_data_buf_miso => reg_diag_data_buf_miso, reg_data_buf_miso => reg_diag_data_buf_miso,
reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
reg_rx_seq_miso => reg_diag_rx_seq_miso,
in_sync => diag_data_buf_snk_in_arr(0).sync, in_sync => diag_data_buf_snk_in_arr(0).sync,
in_sosi_arr => diag_data_buf_snk_in_arr in_sosi_arr => diag_data_buf_snk_in_arr
......
boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
+ 15
− 5
View file @ 8a503bd3
...@@ -63,6 +63,8 @@ ENTITY udp_stream IS ...@@ -63,6 +63,8 @@ ENTITY udp_stream IS
reg_diag_bg_miso : OUT t_mem_miso; reg_diag_bg_miso : OUT t_mem_miso;
ram_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG buffer RAM (one per stream) ram_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG buffer RAM (one per stream)
ram_diag_bg_miso : OUT t_mem_miso; ram_diag_bg_miso : OUT t_mem_miso;
reg_diag_tx_seq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_diag_tx_seq_miso : OUT t_mem_miso;
-- dp_offload_tx -- dp_offload_tx
reg_dp_offload_tx_mosi : IN t_mem_mosi := c_mem_mosi_rst; reg_dp_offload_tx_mosi : IN t_mem_mosi := c_mem_mosi_rst;
...@@ -90,7 +92,9 @@ ENTITY udp_stream IS ...@@ -90,7 +92,9 @@ ENTITY udp_stream IS
reg_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst; reg_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_diag_data_buf_miso : OUT t_mem_miso; reg_diag_data_buf_miso : OUT t_mem_miso;
ram_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst; ram_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_diag_data_buf_miso : OUT t_mem_miso ram_diag_data_buf_miso : OUT t_mem_miso;
reg_diag_rx_seq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_diag_rx_seq_miso : OUT t_mem_miso
); );
END udp_stream; END udp_stream;
...@@ -157,8 +161,9 @@ BEGIN ...@@ -157,8 +161,9 @@ BEGIN
g_buf_dat_w => g_data_w, g_buf_dat_w => g_data_w,
g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)), g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
g_file_index_arr => array_init(0, g_nof_streams), g_file_index_arr => array_init(0, g_nof_streams),
g_file_name_prefix => "../../counter_data_" & NATURAL'IMAGE(g_data_w), g_file_name_prefix => "hex/counter_data_" & NATURAL'IMAGE(g_data_w),
g_diag_block_gen_rst => c_bg_ctrl g_diag_block_gen_rst => c_bg_ctrl,
g_use_tx_seq => TRUE
) )
PORT MAP ( PORT MAP (
mm_rst => mm_rst, mm_rst => mm_rst,
...@@ -173,7 +178,9 @@ BEGIN ...@@ -173,7 +178,9 @@ BEGIN
reg_bg_ctrl_mosi => reg_diag_bg_mosi, reg_bg_ctrl_mosi => reg_diag_bg_mosi,
reg_bg_ctrl_miso => reg_diag_bg_miso, reg_bg_ctrl_miso => reg_diag_bg_miso,
ram_bg_data_mosi => ram_diag_bg_mosi, ram_bg_data_mosi => ram_diag_bg_mosi,
ram_bg_data_miso => ram_diag_bg_miso ram_bg_data_miso => ram_diag_bg_miso,
reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
reg_tx_seq_miso => reg_diag_tx_seq_miso
); );
gen_dp_fifo_sc : FOR i IN 0 TO g_nof_streams-1 GENERATE gen_dp_fifo_sc : FOR i IN 0 TO g_nof_streams-1 GENERATE
...@@ -321,7 +328,8 @@ BEGIN ...@@ -321,7 +328,8 @@ BEGIN
g_nof_streams => g_nof_streams, g_nof_streams => g_nof_streams,
g_data_w => 32, --g_data_w, --FIXME g_data_w => 32, --g_data_w, --FIXME
g_buf_nof_data => 1024, g_buf_nof_data => 1024,
g_buf_use_sync => FALSE -- sync by reading last address of data buffer g_buf_use_sync => FALSE, -- sync by reading last address of data buffer
g_use_rx_seq => TRUE
) )
PORT MAP ( PORT MAP (
mm_rst => mm_rst, mm_rst => mm_rst,
...@@ -333,6 +341,8 @@ BEGIN ...@@ -333,6 +341,8 @@ BEGIN
ram_data_buf_miso => ram_diag_data_buf_miso, ram_data_buf_miso => ram_diag_data_buf_miso,
reg_data_buf_mosi => reg_diag_data_buf_mosi, reg_data_buf_mosi => reg_diag_data_buf_mosi,
reg_data_buf_miso => reg_diag_data_buf_miso, reg_data_buf_miso => reg_diag_data_buf_miso,
reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
reg_rx_seq_miso => reg_diag_rx_seq_miso,
in_sync => diag_data_buf_snk_in_arr(0).sync, in_sync => diag_data_buf_snk_in_arr(0).sync,
in_sosi_arr => diag_data_buf_snk_in_arr in_sosi_arr => diag_data_buf_snk_in_arr
......
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