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Kenneth Hiemstra authoredKenneth Hiemstra authored
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ddr_stream.vhd 12.83 KiB
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, technology_lib, tech_ddr_lib, diag_lib, io_ddr_lib, reorder_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_interface_layers_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE reorder_lib.reorder_pkg.ALL;
USE work.unb1_test_pkg.ALL;
ENTITY ddr_stream IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_technology : NATURAL := c_tech_stratixiv;
g_nof_streams : NATURAL;
g_data_w : NATURAL;
g_bg_block_size : NATURAL := 1024;
g_bg_gapsize : NATURAL := 0;
g_bg_blocks_per_sync : NATURAL := 200000;
g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
g_ena_pre_transp : BOOLEAN := FALSE;
g_reorder_seq : t_reorder_seq := c_reorder_seq_same
);
PORT (
-- System
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
dp_clk : IN STD_LOGIC;
-- blockgen mm
reg_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG control register (one for all streams)
reg_diag_bg_miso : OUT t_mem_miso;
ram_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG buffer RAM (one per stream)
ram_diag_bg_miso : OUT t_mem_miso;
reg_diag_tx_seq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_diag_tx_seq_miso : OUT t_mem_miso;
-- bsn
reg_bsn_monitor_mosi : IN t_mem_mosi;
reg_bsn_monitor_miso : OUT t_mem_miso;
-- databuffer
reg_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_diag_data_buf_miso : OUT t_mem_miso;
ram_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_diag_data_buf_miso : OUT t_mem_miso;
reg_diag_rx_seq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_diag_rx_seq_miso : OUT t_mem_miso;
-- IO DDR register map
reg_io_ddr_mosi : IN t_mem_mosi;
reg_io_ddr_miso : OUT t_mem_miso;
-- Reorder transpose
ram_ss_ss_transp_mosi : IN t_mem_mosi;
ram_ss_ss_transp_miso : OUT t_mem_miso;
-- SO-DIMM Memory Bank I
MB_I_IN : IN t_tech_ddr3_phy_in;
MB_I_IO : INOUT t_tech_ddr3_phy_io;
MB_I_OU : OUT t_tech_ddr3_phy_ou
);
END ddr_stream;
ARCHITECTURE str OF ddr_stream IS
-- Block generator
CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
'0', -- enable_sync
TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
TO_UVEC( 0, c_diag_bg_bsn_init_w));
CONSTANT c_max_nof_words_per_block : NATURAL := g_bg_block_size;
CONSTANT c_min_nof_words_per_block : NATURAL := 1;
CONSTANT c_def_nof_blocks_per_packet : NATURAL := 1;
-- ddr
CONSTANT c_wr_fifo_depth : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO.
CONSTANT c_rd_fifo_depth : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
SIGNAL block_gen_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL block_gen_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
SIGNAL fifo_block_gen_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL fifo_block_gen_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL diag_data_buf_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-- Signals to interface with the DDR conroller and memory model.
SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
SIGNAL to_mem_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL to_mem_sosi : t_dp_sosi;
SIGNAL from_mem_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL from_mem_sosi : t_dp_sosi;
SIGNAL ddr_ref_rst : STD_LOGIC;
SIGNAL ddr_out_clk_i : STD_LOGIC;
SIGNAL ddr_out_rst_i : STD_LOGIC;
BEGIN
-----------------------------------------------------------------------------
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: ENTITY diag_lib.mms_diag_block_gen
GENERIC MAP (
g_nof_streams => g_nof_streams,
g_buf_dat_w => g_data_w,
g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
g_file_index_arr => array_init(0, g_nof_streams),
g_file_name_prefix => "hex/counter_data_" & NATURAL'IMAGE(g_data_w),
g_diag_block_gen_rst => c_bg_ctrl,
g_use_tx_seq => TRUE
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
en_sync => '1',
out_sosi_arr => block_gen_src_out_arr,
out_siso_arr => block_gen_src_in_arr,
reg_bg_ctrl_mosi => reg_diag_bg_mosi,
reg_bg_ctrl_miso => reg_diag_bg_miso,
ram_bg_data_mosi => ram_diag_bg_mosi,
ram_bg_data_miso => ram_diag_bg_miso,
reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
reg_tx_seq_miso => reg_diag_tx_seq_miso
);
u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
GENERIC MAP (
g_nof_streams => g_nof_streams,
g_cross_clock_domain => TRUE,
--g_sync_timeout => g_bg_blocks_per_sync*(g_bg_block_size+g_bg_gapsize),
g_cnt_sop_w => c_word_w,--ceil_log2(g_bg_blocks_per_sync+1),
g_cnt_valid_w => c_word_w,--ceil_log2(g_bg_blocks_per_sync*g_bg_block_size+1),
g_log_first_bsn => TRUE
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
reg_mosi => reg_bsn_monitor_mosi,
reg_miso => reg_bsn_monitor_miso,
dp_rst => dp_rst,
dp_clk => dp_clk,
in_siso_arr => diag_data_buf_snk_out_arr,
in_sosi_arr => diag_data_buf_snk_in_arr
);
diag_data_buf_snk_out_arr <= (OTHERS=>c_dp_siso_rdy);
u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_nof_streams => g_nof_streams,
g_data_w => 32, --g_data_w, --FIXME
g_buf_nof_data => 1024,
g_buf_use_sync => FALSE, -- sync by reading last address of data buffer
g_use_rx_seq => TRUE )
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
ram_data_buf_mosi => ram_diag_data_buf_mosi,
ram_data_buf_miso => ram_diag_data_buf_miso,
reg_data_buf_mosi => reg_diag_data_buf_mosi,
reg_data_buf_miso => reg_diag_data_buf_miso,
reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
reg_rx_seq_miso => reg_diag_rx_seq_miso,
in_sync => diag_data_buf_snk_in_arr(0).sync,
in_sosi_arr => diag_data_buf_snk_in_arr
);
u_transpose: ENTITY reorder_lib.reorder_transpose
GENERIC MAP(
g_nof_streams => g_nof_streams,
g_in_dat_w => g_data_w,
g_frame_size_in => g_reorder_seq.wr_chunksize,
g_frame_size_out => g_reorder_seq.wr_chunksize,
g_use_complex => FALSE,
g_ena_pre_transp => g_ena_pre_transp,
g_reorder_seq => g_reorder_seq
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => ddr_out_rst_i,
dp_clk => ddr_out_clk_i,
-- ST sink
snk_out_arr => block_gen_src_in_arr,
snk_in_arr => block_gen_src_out_arr,
-- ST source
src_in_arr => (OTHERS => c_dp_siso_rdy),
src_out_arr => diag_data_buf_snk_in_arr,
ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-- Control interface to the external memory
dvr_miso => ctlr_dvr_miso,
dvr_mosi => ctlr_dvr_mosi,
-- Data interface to the external memory
to_mem_src_out => to_mem_sosi,
to_mem_src_in => to_mem_siso,
from_mem_snk_in => from_mem_sosi,
from_mem_snk_out => from_mem_siso
);
u_areset_ddr_ref_rst : ENTITY common_lib.common_areset
GENERIC MAP(
g_rst_level => '1',
g_delay_len => 40
)
PORT MAP(
clk => dp_clk,
in_rst => '0',
out_rst => ddr_ref_rst
);
------------------------------------------------------------------------------
-- DDR3 MODULE 0, MB_I
------------------------------------------------------------------------------
u_ddr_mem_ctrl : ENTITY io_ddr_lib.io_ddr
GENERIC MAP(
g_technology => g_technology,
g_tech_ddr => g_tech_ddr,
g_cross_domain_dvr_ctlr => FALSE,
g_wr_data_w => g_data_w,
g_wr_fifo_depth => c_wr_fifo_depth,
g_rd_fifo_depth => c_rd_fifo_depth,
g_rd_data_w => g_data_w,
g_wr_flush_mode => "SYN",
g_wr_flush_use_channel => FALSE,
g_wr_flush_start_channel => 0,
g_wr_flush_nof_channels => 1
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
-- MM register map for DDR controller status info
reg_io_ddr_mosi => reg_io_ddr_mosi,
reg_io_ddr_miso => reg_io_ddr_miso,
-- DDR reference clock
ctlr_ref_clk => dp_clk,
ctlr_ref_rst => ddr_ref_rst,
-- DDR controller clock domain
ctlr_clk_out => ddr_out_clk_i,
ctlr_rst_out => ddr_out_rst_i,
ctlr_clk_in => ddr_out_clk_i,
ctlr_rst_in => ddr_out_rst_i,
-- Driver clock domain
dvr_clk => ddr_out_clk_i,
dvr_rst => ddr_out_rst_i,
dvr_miso => ctlr_dvr_miso,
dvr_mosi => ctlr_dvr_mosi,
-- Write FIFO clock domain
wr_clk => ddr_out_clk_i,
wr_rst => ddr_out_rst_i,
wr_fifo_usedw => OPEN,
wr_sosi => to_mem_sosi,
wr_siso => to_mem_siso,
-- Read FIFO clock domain
rd_clk => ddr_out_clk_i,
rd_rst => ddr_out_rst_i,
rd_fifo_usedw => OPEN,
rd_sosi => from_mem_sosi,
rd_siso => from_mem_siso,
term_ctrl_out => OPEN,
term_ctrl_in => OPEN,
phy3_in => MB_I_IN,
phy3_io => MB_I_IO,
phy3_ou => MB_I_OU
);
END str;