-- Purpose: Provide AXI-4-stream interfaces + standard avalon MM interfaces for
-- eth_tester.vhd such that it can be used to create a Vivado IP block.
-- Description:
-- . The rdma_demo_eth_tester_wrapper uses axi4_stream_dp_bridge to convert the dp
-- . The rdma_demo_roce_tester_wrapper uses axi4_stream_dp_bridge to convert the dp
-- sosi/siso interfaces of the eth_tester into AXI4-Stream interfaces.
-- . In order for this component to be suitable as a Vivado IP, the ports are
-- exclusively STD_LOGIC(_VECTOR) where the widths are hard-coded as demanded
-- by the Vivado IP creator (only supports VHDL-93).
-- . * roce = RDMA Over Converged Ethernet
-- Remark
-- . Avalon is used for all MM interfaces, which can be bridged to AXI4-Lite in
-- vivado using the AXI AMM Bridge IP.
...
...
@@ -195,7 +196,8 @@ begin
g_hdr_calc_ip_crc=>true,
g_hdr_field_arr=>c_rdma_demo_roce_hdr_field_arr,
g_hdr_field_sel=>c_rdma_demo_roce_hdr_field_sel,
g_hdr_app_len=>c_rdma_demo_roce_hdr_len+c_rdma_demo_roce_icrc_len,-- Add icrc length here as this generic is used to calculate the total packet length.
-- Add icrc length here as g_hdr_app_len is used to calculate the total packet length.