Reinier van der Walle
--- a/libraries/io/eth/src/vhdl/eth_checksum_10g.vhd deleted 100644 → 0
+++ b/libraries/io/eth/src/vhdl/eth_checksum_10g.vhd deleted 100644 → 0
--- a/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd
+++ b/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd
  --   to 0 by declaring hdr_fields_in_arr with all 0. Hence e.g. udp_checksum
  --   = 0 can be achieve via data path and default hdr_fields_in_arr = 0 or
  --   via MM controlled and field_default(0).
-  constant c_rdma_demo_nof_hdr_fields : natural := 4;
-  constant c_rdma_demo_hdr_field_sel  : std_logic_vector(c_rdma_demo_nof_hdr_fields - 1 downto 0) := "0100";
+  constant c_rdma_demo_dp_nof_hdr_fields : natural := 4;
+  constant c_rdma_demo_dp_hdr_field_sel  : std_logic_vector(c_rdma_demo_dp_nof_hdr_fields - 1 downto 0) := "0100";

-  constant c_rdma_demo_hdr_field_arr : t_common_field_arr(c_rdma_demo_nof_hdr_fields - 1 downto 0) := (
+  constant c_rdma_demo_dp_hdr_field_arr : t_common_field_arr(c_rdma_demo_dp_nof_hdr_fields - 1 downto 0) := (
      ( field_name_pad("dp_length"                               ), "RW", 16, field_default(0) ),
--- a/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd 0 → 100644
+++ b/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd 0 → 100644
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: R. van der Walle
+-- Purpose: Provide AXI-4-stream interfaces + standard avalon MM interfaces for
+--          eth_tester.vhd such that it can be used to create a Vivado IP block.
+-- Description:
+-- . The rdma_demo_eth_tester_wrapper uses axi4_stream_dp_bridge to convert the dp
+--   sosi/siso interfaces of the eth_tester into AXI4-Stream interfaces.
+-- . In order for this component to be suitable as a Vivado IP, the ports are
+--   exclusively STD_LOGIC(_VECTOR) where the widths are hard-coded as demanded
+--   by the Vivado IP creator (only supports VHDL-93).
+-- Remark
--- a/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd 0 → 100644
+++ b/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd 0 → 100644
+  signal mm_rst : std_logic := '0';
+  signal st_rst : std_logic := '0';
+
+begin
+
+  u_eth_tester : entity eth_lib.eth_tester
+  generic map (
+    g_nof_octet_generate => c_rdma_demo_nof_octet_generate_100gbe,
+    g_nof_octet_output   => c_rdma_demo_nof_octet_output_100gbe,
+    g_use_eth_header     => false,
+    g_use_ip_udp_header  => true,
+    g_use_dp_header      => false,
+    g_hdr_calc_ip_crc    => true,
+    g_hdr_field_arr      => c_rdma_demo_roce_hdr_field_arr,
+    g_hdr_field_sel      => c_rdma_demo_roce_hdr_field_sel,
+    g_hdr_app_len        => c_rdma_demo_roce_hdr_len + c_rdma_demo_roce_icrc_len, -- Add icrc length here as this generic is used to calculate the total packet length.