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Commit 89e5b9c9 authored by Reinier van der Walle's avatar Reinier van der Walle
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2 merge requests!100Removed text for XSub that is now written in Confluence Subband correlator...,!84initial commit of dp_sync_insert_v2
...@@ -368,6 +368,7 @@ regression_test_vhdl = ...@@ -368,6 +368,7 @@ regression_test_vhdl =
tb/vhdl/tb_tb_dp_sync_checker.vhd tb/vhdl/tb_tb_dp_sync_checker.vhd
tb/vhdl/tb_mms_dp_sync_checker.vhd tb/vhdl/tb_mms_dp_sync_checker.vhd
tb/vhdl/tb_tb_dp_sync_insert.vhd tb/vhdl/tb_tb_dp_sync_insert.vhd
tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
tb/vhdl/tb_dp_counter_func.vhd tb/vhdl/tb_dp_counter_func.vhd
tb/vhdl/tb_tb_dp_counter.vhd tb/vhdl/tb_tb_dp_counter.vhd
tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
......
...@@ -71,13 +71,12 @@ ARCHITECTURE rtl OF dp_sync_insert_v2 IS ...@@ -71,13 +71,12 @@ ARCHITECTURE rtl OF dp_sync_insert_v2 IS
TYPE t_reg IS RECORD -- local registers TYPE t_reg IS RECORD -- local registers
blk_cnt : NATURAL RANGE 0 TO g_nof_blk_per_sync; blk_cnt : NATURAL RANGE 0 TO g_nof_blk_per_sync;
nof_blk_per_sync : NATURAL RANGE 0 TO g_nof_blk_per_sync; nof_blk_per_sync : NATURAL RANGE 0 TO g_nof_blk_per_sync;
in_sosi_arr_reg : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
out_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); out_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
END RECORD; END RECORD;
CONSTANT c_reg_rst : t_reg := ( 0, 0, (OTHERS => c_dp_sosi_rst), (OTHERS => c_dp_sosi_rst)); CONSTANT c_reg_rst : t_reg := ( 0, 0, (OTHERS => c_dp_sosi_rst));
CONSTANT c_mm_reg_w : NATURAL := ceil_log2(g_nof_blk_per_sync+1); CONSTANT c_mm_reg_w : NATURAL := ceil_log2(g_nof_blk_per_sync+1);
CONSTANT c_nof_blk_per_sync_reg : t_c_mem := (1, 1, c_mm_reg_w, 1, 'X'); CONSTANT c_nof_blk_per_sync_mm_reg : t_c_mem := (1, 1, c_mm_reg_w, 1, 'X');
CONSTANT c_init_reg : STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := TO_UVEC(g_nof_blk_per_sync, c_mem_reg_init_w); CONSTANT c_init_reg : STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := TO_UVEC(g_nof_blk_per_sync, c_mem_reg_init_w);
-- Define the local registers in t_reg record -- Define the local registers in t_reg record
...@@ -103,18 +102,17 @@ BEGIN ...@@ -103,18 +102,17 @@ BEGIN
VARIABLE v : t_reg; VARIABLE v : t_reg;
BEGIN BEGIN
v := r; v := r;
v.in_sosi_arr_reg := in_sosi_arr; v.out_sosi_arr := in_sosi_arr;
v.out_sosi_arr := r.in_sosi_arr_reg;
v.nof_blk_per_sync := TO_UINT(reg_nof_blk_per_sync); v.nof_blk_per_sync := TO_UINT(reg_nof_blk_per_sync);
IF TO_UINT(reg_nof_blk_per_sync) < g_nof_blk_per_sync_min THEN IF TO_UINT(reg_nof_blk_per_sync) < g_nof_blk_per_sync_min THEN
v.nof_blk_per_sync := g_nof_blk_per_sync_min; v.nof_blk_per_sync := g_nof_blk_per_sync_min;
END IF; END IF;
IF r.in_sosi_arr_reg(0).sop = '1' THEN IF in_sosi_arr(0).sop = '1' THEN
v.blk_cnt := r.blk_cnt + 1; v.blk_cnt := r.blk_cnt + 1;
IF r.blk_cnt = r.nof_blk_per_sync-1 OR r.in_sosi_arr_reg(0).sync = '1' THEN IF r.blk_cnt = r.nof_blk_per_sync-1 OR in_sosi_arr(0).sync = '1' THEN
v.blk_cnt := 0; v.blk_cnt := 0;
FOR I IN 0 TO g_nof_streams-1 LOOP FOR I IN 0 TO g_nof_streams-1 LOOP
v.out_sosi_arr(I).sync := '1'; v.out_sosi_arr(I).sync := '1';
...@@ -130,7 +128,7 @@ BEGIN ...@@ -130,7 +128,7 @@ BEGIN
GENERIC MAP ( GENERIC MAP (
g_cross_clock_domain => TRUE, g_cross_clock_domain => TRUE,
g_readback => FALSE, g_readback => FALSE,
g_reg => c_nof_blk_per_sync_reg, g_reg => c_nof_blk_per_sync_mm_reg,
g_init_reg => c_init_reg g_init_reg => c_init_reg
) )
PORT MAP ( PORT MAP (
......
...@@ -21,7 +21,11 @@ ...@@ -21,7 +21,11 @@
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Author : R vd Walle -- Author : R vd Walle
-- Purpose: Verify dp_sync_insert_v2 -- Purpose: Verify dp_sync_insert_v2
-- Description: -- Description: The tb verifies:
-- . data valid gaps between blocks
-- . data valid gaps within blocks
-- . output sop, eop, valid, bsn equal to input
-- . expected output sync consisting of input syncs and inserted syncs
-- Usage: -- Usage:
-- > as 8 -- > as 8
-- > run -all -- > run -all
...@@ -57,7 +61,7 @@ END tb_dp_sync_insert_v2; ...@@ -57,7 +61,7 @@ END tb_dp_sync_insert_v2;
ARCHITECTURE tb OF tb_dp_sync_insert_v2 IS ARCHITECTURE tb OF tb_dp_sync_insert_v2 IS
CONSTANT c_dut_latency : NATURAL := 2; CONSTANT c_dut_latency : NATURAL := 1;
CONSTANT c_nof_replicated_sync : NATURAL := g_nof_blk_per_sync_input/g_nof_blk_per_sync; CONSTANT c_nof_replicated_sync : NATURAL := g_nof_blk_per_sync_input/g_nof_blk_per_sync;
CONSTANT c_dp_clk_period : TIME := 5 ns; CONSTANT c_dp_clk_period : TIME := 5 ns;
......
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