diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index 8e1ea30462a962828a9b3b4c0d540fc28a2dcfc5..9bceeae7d50a99e04c724a62f37821888af5a23f 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -368,6 +368,7 @@ regression_test_vhdl =
     tb/vhdl/tb_tb_dp_sync_checker.vhd
     tb/vhdl/tb_mms_dp_sync_checker.vhd
     tb/vhdl/tb_tb_dp_sync_insert.vhd
+    tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
     tb/vhdl/tb_dp_counter_func.vhd
     tb/vhdl/tb_tb_dp_counter.vhd
     tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
diff --git a/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd b/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
index 327c73530a0e36be0271e600b6006ed4badbdc4e..09ec4ea11954da32ea8b28ab42c75dd6fc34664e 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
@@ -71,13 +71,12 @@ ARCHITECTURE rtl OF dp_sync_insert_v2 IS
   TYPE t_reg IS RECORD  -- local registers
     blk_cnt          : NATURAL RANGE 0 TO g_nof_blk_per_sync;
     nof_blk_per_sync : NATURAL RANGE 0 TO g_nof_blk_per_sync;
-    in_sosi_arr_reg  : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
     out_sosi_arr     : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
   END RECORD;
   
-  CONSTANT c_reg_rst  : t_reg := ( 0, 0, (OTHERS => c_dp_sosi_rst), (OTHERS => c_dp_sosi_rst));
+  CONSTANT c_reg_rst  : t_reg := ( 0, 0, (OTHERS => c_dp_sosi_rst));
   CONSTANT c_mm_reg_w : NATURAL := ceil_log2(g_nof_blk_per_sync+1);
-  CONSTANT c_nof_blk_per_sync_reg   : t_c_mem := (1, 1, c_mm_reg_w, 1, 'X');
+  CONSTANT c_nof_blk_per_sync_mm_reg   : t_c_mem := (1, 1, c_mm_reg_w, 1, 'X');
   CONSTANT c_init_reg : STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := TO_UVEC(g_nof_blk_per_sync, c_mem_reg_init_w);
 
   -- Define the local registers in t_reg record
@@ -103,18 +102,17 @@ BEGIN
     VARIABLE v : t_reg;
   BEGIN
     v := r;
-    v.in_sosi_arr_reg := in_sosi_arr;
-    v.out_sosi_arr := r.in_sosi_arr_reg;
+    v.out_sosi_arr := in_sosi_arr;
 
     v.nof_blk_per_sync := TO_UINT(reg_nof_blk_per_sync);
     IF TO_UINT(reg_nof_blk_per_sync) < g_nof_blk_per_sync_min THEN
       v.nof_blk_per_sync := g_nof_blk_per_sync_min;
     END IF;
 
-    IF r.in_sosi_arr_reg(0).sop = '1' THEN
+    IF in_sosi_arr(0).sop = '1' THEN
       v.blk_cnt  := r.blk_cnt + 1;        
       
-      IF r.blk_cnt = r.nof_blk_per_sync-1 OR r.in_sosi_arr_reg(0).sync = '1' THEN
+      IF r.blk_cnt = r.nof_blk_per_sync-1 OR in_sosi_arr(0).sync = '1' THEN
         v.blk_cnt := 0;
         FOR I IN 0 TO g_nof_streams-1 LOOP
           v.out_sosi_arr(I).sync := '1';
@@ -130,7 +128,7 @@ BEGIN
   GENERIC MAP (
     g_cross_clock_domain => TRUE,
     g_readback           => FALSE,
-    g_reg                => c_nof_blk_per_sync_reg,
+    g_reg                => c_nof_blk_per_sync_mm_reg,
     g_init_reg           => c_init_reg
   )
   PORT MAP (
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
index 8dbd0634e1a7cdeef974df635f812a948ba4d434..cf0756ff928d873ed1836956a1577ae69607b406 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
@@ -21,7 +21,11 @@
 -------------------------------------------------------------------------------
 -- Author : R vd Walle
 -- Purpose: Verify dp_sync_insert_v2
--- Description:
+-- Description: The tb verifies:
+--  . data valid gaps between blocks
+--  . data valid gaps within blocks
+--  . output sop, eop, valid, bsn equal to input
+--  . expected output sync consisting of input syncs and inserted syncs
 -- Usage:
 -- > as 8
 -- > run -all
@@ -57,7 +61,7 @@ END tb_dp_sync_insert_v2;
 
 ARCHITECTURE tb OF tb_dp_sync_insert_v2 IS
 
-  CONSTANT c_dut_latency         : NATURAL := 2;
+  CONSTANT c_dut_latency         : NATURAL := 1;
   CONSTANT c_nof_replicated_sync : NATURAL := g_nof_blk_per_sync_input/g_nof_blk_per_sync;
   
   CONSTANT c_dp_clk_period       : TIME := 5 ns;