Made tb self stopping and added to regression test.

applications/apertif/designs/apertif_unb1_bn_filterbank/hdllib.cfg

@@ -19,6 +19,7 @@ test_bench_files =
     tb/vhdl/tb_apertif_unb1_bn_filterbank_stimuli_wg.vhd
 
 regression_test_vhdl = 
+    tb/vhdl/tb_apertif_unb1_bn_filterbank.vhd
     tb/vhdl/tb_apertif_unb1_bn_filterbank_stimuli_wg.vhd
 
 [modelsim_project_file]

applications/apertif/designs/apertif_unb1_bn_filterbank/tb/vhdl/tb_apertif_unb1_bn_filterbank.vhd

@@ -34,12 +34,17 @@ LIBRARY IEEE, common_lib, unb1_board_lib, bf_lib, i2c_lib, aduh_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
 USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
 USE unb1_board_lib.unb1_board_pkg.ALL;
 USE aduh_lib.aduh_dd_pkg.ALL;
 USE i2c_lib.i2c_dev_max1617_pkg.ALL;
 USE bf_lib.bf_pkg.ALL;
 
 ENTITY tb_apertif_unb1_bn_filterbank IS
+  GENERIC (
+    g_sim_time        : TIME := 1 us   -- Simulation duration, use 1 us for regression test and e.g. 100 us for
+                                       -- simulation with external MM file IO control using a Python test case
+  );
 END tb_apertif_unb1_bn_filterbank;
 
 ARCHITECTURE tb OF tb_apertif_unb1_bn_filterbank IS
@@ -109,6 +114,10 @@ ARCHITECTURE tb OF tb_apertif_unb1_bn_filterbank IS
   SIGNAL ADC_CD_SCL            : STD_LOGIC;
   SIGNAL ADC_CD_SDA            : STD_LOGIC;
   
+  -- Tb
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL sim_done            : STD_LOGIC := '0';
+  
   -- DUT
   SIGNAL WDI                 : STD_LOGIC;
   SIGNAL ext_pps             : STD_LOGIC;
@@ -147,8 +156,6 @@ ARCHITECTURE tb OF tb_apertif_unb1_bn_filterbank IS
   
 BEGIN
 
-  -- Run 1 ms
-  
   ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz) 
   eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- 1GbE XO clock (25 MHz) 
   tr_clk  <= NOT tr_clk AFTER c_tr_clk_period/2;    -- Transceiver clock (156.25 MHz) 
@@ -336,5 +343,13 @@ BEGIN
   BN_BI_0_RX <= TRANSPORT BN_BI_0_TX AFTER c_cable_delay;
   BN_BI_1_RX <= TRANSPORT BN_BI_1_TX AFTER c_cable_delay;
   BN_BI_2_RX <= TRANSPORT BN_BI_2_TX AFTER c_cable_delay;
+
  
+  ------------------------------------------------------------------------------
+  -- Simulation end
+  ------------------------------------------------------------------------------
+  sim_done <= '0', '1' AFTER g_sim_time;
+  
+  proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+
 END tb;