Made tb self stopping and added to regression test.

applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg

@@ -20,6 +20,9 @@ synth_files =
 test_bench_files =                                                                      
     tb_apertif_unb1_fn_beamformer_trans.vhd                                       
 
+regression_test_vhdl = 
+    tb_apertif_unb1_fn_beamformer_trans.vhd                                       
+
 
 [modelsim_project_file]
 modelsim_copy_files = ../../src/hex hex                                                   

applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/tb_apertif_unb1_fn_beamformer_trans.vhd

@@ -55,13 +55,17 @@ ARCHITECTURE tb OF tb_apertif_unb1_fn_beamformer_trans IS
   CONSTANT c_cable_delay     : TIME := 12 ns;
   CONSTANT c_eth_clk_period  : TIME := 40 ns;  -- 25 MHz XO on UniBoard
   CONSTANT c_sa_clk_period   : TIME := 6.4 ns;  
-  CONSTANT c_clk_period      : TIME := 5 ns; 
+  CONSTANT c_ext_clk_period  : TIME := 5 ns; 
   CONSTANT c_pps_period      : NATURAL := 1000; 
   
   CONSTANT c_ddr             : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
 
+  -- Tb
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL sim_done            : STD_LOGIC := '0';
+  
   -- DUT
-  SIGNAL clk                 : STD_LOGIC := '0';
+  SIGNAL ext_clk             : STD_LOGIC := '0';
   SIGNAL pps                 : STD_LOGIC := '0';
   SIGNAL pps_rst             : STD_LOGIC := '0';
   SIGNAL sa_clk              : STD_LOGIC := '1';
@@ -94,7 +98,7 @@ BEGIN
   ----------------------------------------------------------------------------
   -- System setup
   ----------------------------------------------------------------------------
-  clk     <= NOT clk AFTER c_clk_period/2;        -- External clock (200 MHz)
+  ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
   eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (25 MHz)
   sa_clk  <= NOT sa_clk  AFTER c_sa_clk_period/2;
   sb_clk  <= NOT sb_clk  AFTER c_sa_clk_period/2;
@@ -108,7 +112,7 @@ BEGIN
   ------------------------------------------------------------------------------
   -- External PPS
   ------------------------------------------------------------------------------  
-  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
   
   ------------------------------------------------------------------------------
   -- DUT
@@ -122,7 +126,7 @@ BEGIN
   )
   PORT MAP (
     -- GENERAL
-      CLK         => clk,
+    CLK         => ext_clk,
     PPS         => pps,
     WDI         => WDI,
     INTA        => INTA,
@@ -175,5 +179,12 @@ BEGIN
     mem3_ou => phy_in
   );
     
+  ------------------------------------------------------------------------------
+  -- Check that design can simulate some us without error
+  ------------------------------------------------------------------------------
+  sim_done <= '0', '1' AFTER 1 us;
+  
+  proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+
 
 END tb;