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Commit 898964c0 authored by Eric Kooistra's avatar Eric Kooistra
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Use fractional PLL to created 156.25 MHz and 312.5 MHz for mac_10g and for... 

Use fractional PLL to created 156.25 MHz and 312.5 MHz for mac_10g and for 10gbase_r. The 10gbase_r XGMII interface is not available at 32b so need to stick to 64b@ 156.25MHz.
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libraries/technology/10gbase_r/hdllib.cfg
+ 1
− 1
View file @ 898964c0
hdl_lib_name = tech_10gbase_r
hdl_library_clause_name = tech_10gbase_r_lib
hdl_lib_uses = technology ip_arria10_phy_10gbase_r ip_arria10_transceiver_pll_10g ip_arria10_transceiver_reset_controller_1 common
hdl_lib_uses = technology ip_arria10_phy_10gbase_r ip_arria10_transceiver_pll_156_312 ip_arria10_transceiver_pll_10g ip_arria10_transceiver_reset_controller_1 common
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
......
libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
+ 30
− 49
View file @ 898964c0
......@@ -34,84 +34,65 @@ USE common_lib.common_interface_layers_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE work.tech_10gbase_r_component_pkg.ALL;
ENTITY tb_tech_10gbase_r IS
-- Test bench control parameters
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_nof_phy : NATURAL := 1
g_technology : NATURAL := c_tech_select_default;
g_nof_channels : NATURAL := 4
);
END tb_tech_10gbase_r;
ARCHITECTURE tb OF tb_tech_10gbase_r IS
CONSTANT sys_clk_period : TIME := 5 ns; -- 200 MHz
CONSTANT tr_ref_clk_period : TIME := 1551515 fs; -- ~ 644.53125 MHz
CONSTANT tx_core_clk_period : TIME := 5 ns; --6.4 ns; -- 156.25 MHz
CONSTANT rx_core_clk_period : TIME := 5 ns; --6.4 ns; -- 156.25 MHz
CONSTANT phy_delay : TIME := 1 ns;
CONSTANT c_sim : BOOLEAN:= TRUE;
CONSTANT phy_loopback_delay : TIME := 1 ns;
SIGNAL sys_clk : STD_LOGIC := '0';
SIGNAL sys_rst : STD_LOGIC;
SIGNAL tr_ref_clk : STD_LOGIC := '0';
SIGNAL clk_312 : STD_LOGIC; -- 312.5 MHz
SIGNAL clk_156 : STD_LOGIC; -- 156.25 MHz
SIGNAL rst_156 : STD_LOGIC; -- reset for clk_156 clock domain
SIGNAL tr_ref_clk : STD_LOGIC := '0';
SIGNAL tx_core_clk_in : STD_LOGIC := '0';
SIGNAL rx_core_clk_in : STD_LOGIC := '0';
SIGNAL tx_pma_div_clk_out : STD_LOGIC;
SIGNAL tx_pma_clk_out : STD_LOGIC;
SIGNAL tx_clk_out : STD_LOGIC; -- 156.25 MHz
SIGNAL rx_clk_out : STD_LOGIC; -- 156.25 MHz
-- XGMII interface
SIGNAL xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_phy-1 DOWNTO 0);
SIGNAL xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_phy-1 DOWNTO 0);
SIGNAL xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);
SIGNAL xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);
-- PHY serial interface
SIGNAL tx_serial_arr : STD_LOGIC_VECTOR(g_nof_phy-1 DOWNTO 0);
SIGNAL rx_serial_arr : STD_LOGIC_VECTOR(g_nof_phy-1 DOWNTO 0);
SIGNAL tx_serial_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL rx_serial_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
BEGIN
-- run 50 us
sys_clk <= NOT sys_clk AFTER sys_clk_period/2;
tr_ref_clk <= NOT tr_ref_clk AFTER tr_ref_clk_period/2;
tx_core_clk_in <= NOT tx_core_clk_in AFTER tx_core_clk_period/2;
rx_core_clk_in <= NOT rx_core_clk_in AFTER rx_core_clk_period/2;
sys_rst <= '1', '0' AFTER sys_clk_period*10;
tr_ref_clk <= NOT tr_ref_clk AFTER tech_10gbase_r_ref_clk_period/2;
dut : ENTITY work.tech_10gbase_r
GENERIC MAP (
g_technology => g_technology,
g_nof_phy => g_nof_phy
g_technology => g_technology,
g_sim => c_sim,
g_nof_channels => g_nof_channels
)
PORT MAP (
sys_clk => sys_clk,
sys_rst => sys_rst,
-- Transceiver PLL reference clock
tr_ref_clk => tr_ref_clk,
tx_core_clk_in => tx_core_clk_in,
rx_core_clk_in => rx_core_clk_in,
tr_ref_clk => tr_ref_clk, -- 644.531250 MHz
tx_pma_div_clk_out => tx_pma_div_clk_out,
tx_pma_clk_out => tx_pma_clk_out,
tx_clk_out => tx_clk_out, -- 156.25 MHz
rx_clk_out => rx_clk_out, -- 156.25 MHz
xgmii_tx_dc_arr => xgmii_tx_dc_arr,
xgmii_rx_dc_arr => xgmii_rx_dc_arr,
-- Derived clocks
clk_312 => clk_312,
clk_156 => clk_156,
rst_156 => rst_156,
-- XGMII interface
xgmii_tx_dc_arr => xgmii_tx_dc_arr,
xgmii_rx_dc_arr => xgmii_rx_dc_arr,
tx_serial_arr => tx_serial_arr,
rx_serial_arr => rx_serial_arr
-- PHY serial IO
tx_serial_arr => tx_serial_arr,
rx_serial_arr => rx_serial_arr
);
-- PHY loopback
rx_serial_arr <= TRANSPORT tx_serial_arr AFTER phy_delay;
rx_serial_arr <= TRANSPORT tx_serial_arr AFTER phy_loopback_delay;
END tb;
libraries/technology/10gbase_r/tech_10gbase_r.vhd
+ 24
− 24
View file @ 898964c0
......@@ -29,45 +29,45 @@ USE common_lib.common_interface_layers_pkg.ALL;
ENTITY tech_10gbase_r IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_nof_phy : NATURAL := 1
);
g_technology : NATURAL := c_tech_select_default;
g_sim : BOOLEAN := FALSE;
g_nof_channels : NATURAL := 1 -- fixed for now
);
PORT (
sys_clk : IN STD_LOGIC; -- 200 MHz
sys_rst : IN STD_LOGIC;
-- Transceiver PLL reference clock
tr_ref_clk : IN STD_LOGIC; -- 644.531250 MHz
tx_core_clk_in : IN STD_LOGIC; -- 156.25 MHz
rx_core_clk_in : IN STD_LOGIC; -- 156.25 MHz
tx_pma_div_clk_out : OUT STD_LOGIC;
tx_pma_clk_out : OUT STD_LOGIC;
tx_clk_out : OUT STD_LOGIC; -- 156.25 MHz
rx_clk_out : OUT STD_LOGIC; -- 156.25 MHz
xgmii_tx_dc_arr : IN t_xgmii_dc_arr(g_nof_phy-1 DOWNTO 0);
xgmii_rx_dc_arr : OUT t_xgmii_dc_arr(g_nof_phy-1 DOWNTO 0);
-- Derived clocks
clk_312 : OUT STD_LOGIC; -- 312.5 MHz
clk_156 : OUT STD_LOGIC; -- 156.25 MHz
rst_156 : OUT STD_LOGIC; -- reset for clk_156_in clock domain
-- XGMII interface
xgmii_tx_dc_arr : IN t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
xgmii_rx_dc_arr : OUT t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
tx_serial_arr : OUT STD_LOGIC_VECTOR(g_nof_phy-1 DOWNTO 0);
rx_serial_arr : IN STD_LOGIC_VECTOR(g_nof_phy-1 DOWNTO 0)
-- PHY serial IO
tx_serial_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
rx_serial_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
);
END tech_10gbase_r;
ARCHITECTURE str OF tech_10gbase_r IS
SIGNAL clk_156_out : STD_LOGIC; -- connect to clk_156_out to clk_156_in to avoid delta-cycle differences in simulation
BEGIN
clk_156 <= clk_156_out;
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
u0 : ENTITY work.tech_10gbase_r_arria10
GENERIC MAP (g_nof_phy)
PORT MAP (sys_clk, sys_rst,
tr_ref_clk, tx_core_clk_in, rx_core_clk_in,
tx_pma_div_clk_out, tx_pma_clk_out, tx_clk_out, rx_clk_out,
xgmii_tx_dc_arr(0), xgmii_rx_dc_arr(0),
tx_serial_arr(0), rx_serial_arr(0));
GENERIC MAP (g_sim, g_nof_channels)
PORT MAP (tr_ref_clk,
clk_312, clk_156_out, clk_156_out, rst_156,
xgmii_tx_dc_arr, xgmii_rx_dc_arr,
tx_serial_arr, rx_serial_arr);
END GENERATE;
END str;
......
libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
+ 168
− 150
View file @ 898964c0
......@@ -22,6 +22,7 @@
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_phy_10gbase_r_lib;
LIBRARY ip_arria10_transceiver_pll_156_312_lib;
LIBRARY ip_arria10_transceiver_pll_10g_lib;
LIBRARY ip_arria10_transceiver_reset_controller_1_lib;
......@@ -33,184 +34,201 @@ USE work.tech_10gbase_r_component_pkg.ALL;
ENTITY tech_10gbase_r_arria10 IS
GENERIC (
g_nof_phy : NATURAL := 1 -- fixed for now
g_sim : BOOLEAN := FALSE;
g_nof_channels : NATURAL := 1
);
PORT (
sys_clk : IN STD_LOGIC; -- 200 MHz
sys_rst : IN STD_LOGIC;
-- Transceiver PLL reference clock
tr_ref_clk : IN STD_LOGIC; -- 644.531250 MHz
tx_core_clk_in : IN STD_LOGIC; -- 156.25 MHz
rx_core_clk_in : IN STD_LOGIC; -- 156.25 MHz
tx_pma_div_clk_out : OUT STD_LOGIC;
tx_pma_clk_out : OUT STD_LOGIC;
tx_clk_out : OUT STD_LOGIC; -- 156.25 MHz
rx_clk_out : OUT STD_LOGIC; -- 156.25 MHz
-- Derived clocks
clk_312_out : OUT STD_LOGIC; -- 312.5 MHz
clk_156_out : OUT STD_LOGIC; -- 156.25 MHz
clk_156_in : IN STD_LOGIC; -- externally connect to clk_156_out to avoid delta-cycle differences in simulation
rst_156 : OUT STD_LOGIC; -- reset for clk_156_in clock domain
-- XGMII interface
xgmii_tx_dc : IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
xgmii_rx_dc : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
xgmii_tx_dc_arr : IN t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
xgmii_rx_dc_arr : OUT t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
-- PHY serial IO
tx_serial : OUT STD_LOGIC;
rx_serial : IN STD_LOGIC
tx_serial_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
rx_serial_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
);
END tech_10gbase_r_arria10;
ARCHITECTURE str OF tech_10gbase_r_arria10 IS
SIGNAL tx_serial_clk : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL tx_serial_data : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL rx_serial_data : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL tx_coreclkin : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL rx_coreclkin : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL tx_serial_clk : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL tx_pma_div_clkout : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL tx_pma_clkout : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL tx_clkout : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL rx_clkout : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL tx_coreclkin : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL rx_coreclkin : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL tx_parallel_data : STD_LOGIC_VECTOR(c_xgmii_data_w-1 DOWNTO 0); -- 64 bit
SIGNAL rx_parallel_data : STD_LOGIC_VECTOR(c_xgmii_data_w-1 DOWNTO 0); -- 64 bit
SIGNAL tx_control : STD_LOGIC_VECTOR(c_xgmii_ctrl_w-1 DOWNTO 0); -- 8 bit
SIGNAL rx_control : STD_LOGIC_VECTOR(c_xgmii_ctrl_w-1 DOWNTO 0); -- 8 bit
SIGNAL tx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit
SIGNAL rx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit
SIGNAL tx_control_arr : t_xgmii_c_arr(g_nof_channels-1 DOWNTO 0); -- 8 bit
SIGNAL rx_control_arr : t_xgmii_c_arr(g_nof_channels-1 DOWNTO 0); -- 8 bit
-- transceiver reset controller
SIGNAL tx_analogreset : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL tx_digitalreset : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL rx_analogreset : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL rx_digitalreset : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL tx_cal_busy : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL rx_cal_busy : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL rx_is_lockedtodata : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL pll_or_tx_cal_busy : STD_LOGIC_VECTOR(0 DOWNTO 0);
-- transceiver PLL for 10G
SIGNAL pll_powerdown : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL pll_locked : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL pll_cal_busy : STD_LOGIC;
SIGNAL tx_analogreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL tx_digitalreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL rx_analogreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL rx_digitalreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL tx_cal_busy_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL rx_cal_busy_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL rx_is_lockedtodata_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL cal_busy_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
-- transceiver ATX PLL for 10G
SIGNAL atx_pll_powerdown : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- only use reset controller 0 for ATX PLL power down
SIGNAL atx_pll_locked_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL atx_pll_locked : STD_LOGIC;
SIGNAL atx_pll_cal_busy : STD_LOGIC;
-- transceiver fractional PLL for 156.25 MHz and 312.5 MHz from tr_ref_clk = 644.53125 MHz
SIGNAL fpll_cal_busy : STD_LOGIC;
SIGNAL fpll_locked : STD_LOGIC;
SIGNAL fpll_locked_n : STD_LOGIC;
SIGNAL i_rst_156 : STD_LOGIC;
BEGIN
-- Clocks
tx_coreclkin(0) <= tx_core_clk_in;
rx_coreclkin(0) <= rx_core_clk_in;
tx_coreclkin(0) <= clk_156_in;
rx_coreclkin(0) <= clk_156_in;
gen_phy : FOR I IN 0 TO g_nof_channels-1 GENERATE
-- Reset controller
cal_busy_arr(I) <= tx_cal_busy_arr(I) OR atx_pll_cal_busy;
-- On hardware use atx_pll_locked for all channels, in simulation model some timing difference between the channels
on_hw : IF g_sim=FALSE GENERATE
atx_pll_locked_arr(I) <= atx_pll_locked;
END GENERATE;
in_sim : IF g_sim=TRUE GENERATE
atx_pll_locked_arr(I) <= TRANSPORT atx_pll_locked AFTER tech_10gbase_r_clk_156_period*I;
END GENERATE;
-- XGMII
tx_parallel_data_arr(I)(63 DOWNTO 56) <= xgmii_tx_dc_arr(I)(70 DOWNTO 63); tx_control_arr(I)(7) <= xgmii_tx_dc_arr(I)(71);
tx_parallel_data_arr(I)(55 DOWNTO 48) <= xgmii_tx_dc_arr(I)(61 DOWNTO 54); tx_control_arr(I)(6) <= xgmii_tx_dc_arr(I)(62);
tx_parallel_data_arr(I)(47 DOWNTO 40) <= xgmii_tx_dc_arr(I)(52 DOWNTO 45); tx_control_arr(I)(5) <= xgmii_tx_dc_arr(I)(53);
tx_parallel_data_arr(I)(39 DOWNTO 32) <= xgmii_tx_dc_arr(I)(43 DOWNTO 36); tx_control_arr(I)(4) <= xgmii_tx_dc_arr(I)(44);
tx_parallel_data_arr(I)(31 DOWNTO 24) <= xgmii_tx_dc_arr(I)(34 DOWNTO 27); tx_control_arr(I)(3) <= xgmii_tx_dc_arr(I)(35);
tx_parallel_data_arr(I)(23 DOWNTO 16) <= xgmii_tx_dc_arr(I)(25 DOWNTO 18); tx_control_arr(I)(2) <= xgmii_tx_dc_arr(I)(26);
tx_parallel_data_arr(I)(15 DOWNTO 8) <= xgmii_tx_dc_arr(I)(16 DOWNTO 9); tx_control_arr(I)(1) <= xgmii_tx_dc_arr(I)(17);
tx_parallel_data_arr(I)( 7 DOWNTO 0) <= xgmii_tx_dc_arr(I)( 7 DOWNTO 0); tx_control_arr(I)(0) <= xgmii_tx_dc_arr(I)( 8);
tx_clk_out <= tx_clkout(0);
rx_clk_out <= rx_clkout(0);
tx_pma_div_clk_out <= tx_pma_div_clkout(0);
tx_pma_clk_out <= tx_pma_clkout(0);
-- Serial
tx_serial <= tx_serial_data(0);
rx_serial_data(0) <= rx_serial;
-- Reset controller
pll_or_tx_cal_busy(0) <= tx_cal_busy(0) OR pll_cal_busy;
-- XGMII
tx_parallel_data(63 DOWNTO 56) <= xgmii_tx_dc(70 DOWNTO 63); tx_control(7) <= xgmii_tx_dc(71);
tx_parallel_data(55 DOWNTO 48) <= xgmii_tx_dc(61 DOWNTO 54); tx_control(6) <= xgmii_tx_dc(62);
tx_parallel_data(47 DOWNTO 40) <= xgmii_tx_dc(52 DOWNTO 45); tx_control(5) <= xgmii_tx_dc(53);
tx_parallel_data(39 DOWNTO 32) <= xgmii_tx_dc(43 DOWNTO 36); tx_control(4) <= xgmii_tx_dc(44);
tx_parallel_data(31 DOWNTO 24) <= xgmii_tx_dc(34 DOWNTO 27); tx_control(3) <= xgmii_tx_dc(35);
tx_parallel_data(23 DOWNTO 16) <= xgmii_tx_dc(25 DOWNTO 18); tx_control(2) <= xgmii_tx_dc(26);
tx_parallel_data(15 DOWNTO 8) <= xgmii_tx_dc(16 DOWNTO 9); tx_control(1) <= xgmii_tx_dc(17);
tx_parallel_data( 7 DOWNTO 0) <= xgmii_tx_dc( 7 DOWNTO 0); tx_control(0) <= xgmii_tx_dc( 8);
xgmii_rx_dc(70 DOWNTO 63) <= rx_parallel_data(63 DOWNTO 56); xgmii_rx_dc(71) <= rx_control(7);
xgmii_rx_dc(61 DOWNTO 54) <= rx_parallel_data(55 DOWNTO 48); xgmii_rx_dc(62) <= rx_control(6);
xgmii_rx_dc(52 DOWNTO 45) <= rx_parallel_data(47 DOWNTO 40); xgmii_rx_dc(53) <= rx_control(5);
xgmii_rx_dc(43 DOWNTO 36) <= rx_parallel_data(39 DOWNTO 32); xgmii_rx_dc(44) <= rx_control(4);
xgmii_rx_dc(34 DOWNTO 27) <= rx_parallel_data(31 DOWNTO 24); xgmii_rx_dc(35) <= rx_control(3);
xgmii_rx_dc(25 DOWNTO 18) <= rx_parallel_data(23 DOWNTO 16); xgmii_rx_dc(26) <= rx_control(2);
xgmii_rx_dc(16 DOWNTO 9) <= rx_parallel_data(15 DOWNTO 8); xgmii_rx_dc(17) <= rx_control(1);
xgmii_rx_dc( 7 DOWNTO 0) <= rx_parallel_data( 7 DOWNTO 0); xgmii_rx_dc( 8) <= rx_control(0);
u_ip_arria10_phy_10gbase_r_top : ip_arria10_phy_10gbase_r_top
xgmii_rx_dc_arr(I)(70 DOWNTO 63) <= rx_parallel_data_arr(I)(63 DOWNTO 56); xgmii_rx_dc_arr(I)(71) <= rx_control_arr(I)(7);
xgmii_rx_dc_arr(I)(61 DOWNTO 54) <= rx_parallel_data_arr(I)(55 DOWNTO 48); xgmii_rx_dc_arr(I)(62) <= rx_control_arr(I)(6);
xgmii_rx_dc_arr(I)(52 DOWNTO 45) <= rx_parallel_data_arr(I)(47 DOWNTO 40); xgmii_rx_dc_arr(I)(53) <= rx_control_arr(I)(5);
xgmii_rx_dc_arr(I)(43 DOWNTO 36) <= rx_parallel_data_arr(I)(39 DOWNTO 32); xgmii_rx_dc_arr(I)(44) <= rx_control_arr(I)(4);
xgmii_rx_dc_arr(I)(34 DOWNTO 27) <= rx_parallel_data_arr(I)(31 DOWNTO 24); xgmii_rx_dc_arr(I)(35) <= rx_control_arr(I)(3);
xgmii_rx_dc_arr(I)(25 DOWNTO 18) <= rx_parallel_data_arr(I)(23 DOWNTO 16); xgmii_rx_dc_arr(I)(26) <= rx_control_arr(I)(2);
xgmii_rx_dc_arr(I)(16 DOWNTO 9) <= rx_parallel_data_arr(I)(15 DOWNTO 8); xgmii_rx_dc_arr(I)(17) <= rx_control_arr(I)(1);
xgmii_rx_dc_arr(I)( 7 DOWNTO 0) <= rx_parallel_data_arr(I)( 7 DOWNTO 0); xgmii_rx_dc_arr(I)( 8) <= rx_control_arr(I)(0);
u_ip_arria10_phy_10gbase_r_top : ip_arria10_phy_10gbase_r_top
PORT MAP (
tx_analogreset => tx_analogreset_arr(I DOWNTO I),
tx_digitalreset => tx_digitalreset_arr(I DOWNTO I),
rx_analogreset => rx_analogreset_arr(I DOWNTO I),
rx_digitalreset => rx_digitalreset_arr(I DOWNTO I),
tx_cal_busy => tx_cal_busy_arr(I DOWNTO I),
rx_cal_busy => rx_cal_busy_arr(I DOWNTO I),
tx_serial_clk0 => tx_serial_clk,
rx_cdr_refclk0 => tr_ref_clk,
tx_serial_data => tx_serial_arr(I DOWNTO I),
rx_serial_data => rx_serial_arr(I DOWNTO I),
rx_is_lockedtoref => OPEN,
rx_is_lockedtodata => rx_is_lockedtodata_arr(I DOWNTO I),
tx_coreclkin => tx_coreclkin, -- 156.25 MHz
rx_coreclkin => rx_coreclkin, -- 156.25 MHz
tx_parallel_data => tx_parallel_data_arr(I),
rx_parallel_data => rx_parallel_data_arr(I),
tx_control => tx_control_arr(I),
--tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins
--unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- unused_tx_parallel_data.unused_tx_parallel_data
--unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
rx_control => rx_control_arr(I)
--unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
--unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control
--tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
--tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
--tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
--tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
--tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
--rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
--rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
--rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
--rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
--rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
--rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber
--rx_enh_blk_lock : out std_logic_vector(0 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
);
u_ip_arria10_transceiver_reset_controller_1_top : ip_arria10_transceiver_reset_controller_1_top
PORT MAP (
clock => clk_156_in,
reset => i_rst_156,
pll_powerdown => atx_pll_powerdown(I DOWNTO I),
tx_analogreset => tx_analogreset_arr(I DOWNTO I),
tx_digitalreset => tx_digitalreset_arr(I DOWNTO I),
tx_ready => OPEN,
pll_locked => atx_pll_locked_arr(I DOWNTO I),
pll_select => "0", -- set to zero when using one PLL
tx_cal_busy => cal_busy_arr(I DOWNTO I),
rx_analogreset => rx_analogreset_arr(I DOWNTO I),
rx_digitalreset => rx_digitalreset_arr(I DOWNTO I),
rx_ready => OPEN,
rx_is_lockedtodata => rx_is_lockedtodata_arr(I DOWNTO I),
rx_cal_busy => rx_cal_busy_arr(I DOWNTO I)
);
END GENERATE;
-- ATX PLL
u_ip_arria10_transceiver_pll_10g_top : ip_arria10_transceiver_pll_10g_top
PORT MAP (
tx_analogreset => tx_analogreset,
tx_digitalreset => tx_digitalreset,
rx_analogreset => rx_analogreset,
rx_digitalreset => rx_digitalreset,
tx_cal_busy => tx_cal_busy,
rx_cal_busy => rx_cal_busy,
tx_serial_clk0 => tx_serial_clk,
rx_cdr_refclk0 => tr_ref_clk,
tx_serial_data => tx_serial_data,
rx_serial_data => rx_serial_data,
rx_is_lockedtoref => OPEN,
rx_is_lockedtodata => rx_is_lockedtodata,
tx_coreclkin => tx_coreclkin,
rx_coreclkin => rx_coreclkin,
tx_clkout => tx_clkout,
rx_clkout => rx_clkout,
tx_parallel_data => tx_parallel_data,
rx_parallel_data => rx_parallel_data,
tx_pma_div_clkout => tx_pma_div_clkout,
tx_control => tx_control,
--tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins
--unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- unused_tx_parallel_data.unused_tx_parallel_data
--unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
rx_control => rx_control,
--unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
--unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control
--tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
--tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
--tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
--tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
--tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
--rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
--rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
--rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
--rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
--rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
--rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber
--rx_enh_blk_lock : out std_logic_vector(0 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
tx_pma_clkout => tx_pma_clkout
pll_powerdown => atx_pll_powerdown(0),
pll_refclk0 => tr_ref_clk,
tx_serial_clk => tx_serial_clk(0),
pll_locked => atx_pll_locked,
pll_cal_busy => atx_pll_cal_busy
);
u_ip_arria10_transceiver_reset_controller_1_top : ip_arria10_transceiver_reset_controller_1_top
-- fractional PLL
u_ip_arria10_transceiver_pll_156_312_top : ip_arria10_transceiver_pll_156_312_top
PORT MAP (
clock => sys_clk,
reset => sys_rst,
pll_powerdown => pll_powerdown,
tx_analogreset => tx_analogreset,
tx_digitalreset => tx_digitalreset,
tx_ready => OPEN,
pll_locked => pll_locked,
pll_select => "0", -- set to zero when using one PLL
tx_cal_busy => pll_or_tx_cal_busy,
rx_analogreset => rx_analogreset,
rx_digitalreset => rx_digitalreset,
rx_ready => OPEN,
rx_is_lockedtodata => rx_is_lockedtodata,
rx_cal_busy => rx_cal_busy
pll_refclk0 => tr_ref_clk,
pll_powerdown => '0',
pll_locked => fpll_locked,
outclk0 => clk_156_out,
pll_cal_busy => fpll_cal_busy,
outclk1 => clk_312_out
);
u_ip_arria10_transceiver_pll_10g_top : ip_arria10_transceiver_pll_10g_top
fpll_locked_n <= NOT fpll_locked;
u_common_areset : ENTITY common_lib.common_areset
GENERIC MAP (
g_rst_level => '1',
g_delay_len => c_meta_delay_len
)
PORT MAP (
pll_powerdown => pll_powerdown(0),
pll_refclk0 => tr_ref_clk,
tx_serial_clk => tx_serial_clk(0),
pll_locked => pll_locked(0),
pll_cal_busy => pll_cal_busy
in_rst => fpll_locked_n,
clk => clk_156_in,
out_rst => i_rst_156
);
rst_156 <= i_rst_156;
END str;
libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
+ 17
− 2
View file @ 898964c0
......@@ -27,6 +27,10 @@ USE technology_lib.technology_pkg.ALL;
PACKAGE tech_10gbase_r_component_pkg IS
CONSTANT tech_10gbase_r_ref_clk_period : TIME := 1551520 fs; -- = 1.551520 ns ~= 644.53125 MHz
CONSTANT tech_10gbase_r_clk_156_period : TIME := (tech_10gbase_r_ref_clk_period*33)/8; -- = 6.400020 ns ~= 156.25 MHz
CONSTANT tech_10gbase_r_clk_312_period : TIME := (tech_10gbase_r_ref_clk_period*33)/16; -- = 3.200010 ns ~= 312.5 MHz
------------------------------------------------------------------------------
-- ip_arria10
------------------------------------------------------------------------------
......@@ -71,11 +75,22 @@ PACKAGE tech_10gbase_r_component_pkg IS
rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber
rx_enh_blk_lock : out std_logic_vector(0 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
tx_pma_clkout : out std_logic_vector(0 downto 0) -- tx_pma_clkout.clk
rx_enh_blk_lock : out std_logic_vector(0 downto 0) -- rx_enh_blk_lock.rx_enh_blk_lock
);
END COMPONENT;
-- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_156_312/ip_arria10_transceiver_pll_156_312_top.vhd
COMPONENT ip_arria10_transceiver_pll_156_312_top IS
PORT (
pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
pll_locked : out std_logic; -- pll_locked.pll_locked
outclk0 : out std_logic; -- outclk0.clk
pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
outclk1 : out std_logic -- outclk1.clk
);
END COMPONENT;
-- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g_top.vhd
COMPONENT ip_arria10_transceiver_pll_10g_top IS
PORT (
......
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