diff --git a/libraries/technology/ddr/sim_ddr.vhd b/libraries/technology/ddr/sim_ddr.vhd
index 6bc51b873fdd70ea514203df18730cea8620c81f..8be871ee35cfe25a351a483dc2484eafe7ec9620 100644
--- a/libraries/technology/ddr/sim_ddr.vhd
+++ b/libraries/technology/ddr/sim_ddr.vhd
@@ -117,10 +117,16 @@ ARCHITECTURE str OF sim_ddr IS
   SIGNAL sim_clk     : STD_LOGIC;
   SIGNAL sim_rst     : STD_LOGIC;
 
-  SIGNAL mem_state   : t_mem_state;
-
+  -- Debug signals for view in Wave window
+  SIGNAL dbg_c_nof_addr : NATURAL;
+  SIGNAL dbg_c_dat_w    : NATURAL;
+  SIGNAL mem_state      : t_mem_state;
+  
 BEGIN
 
+  dbg_c_nof_addr <= c_nof_addr;
+  dbg_c_dat_w    <= c_dat_w;
+  
   -- Prevent delta delay issues by using a re-assigned clk both internally (sim_clk) and externally (ctrl_gen_clk)
   ctlr_gen_clk <= ref_clk;
   ctlr_gen_rst <= ref_rst;