ported unb_ddr3_transpose to radiohdl

boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg

+hdl_lib_name = unb1_ddr3_transpose
+hdl_library_clause_name = unb1_ddr3_transpose_lib
+hdl_lib_uses_synth = common mm i2c unb1_board dp eth diagnostics ddr3
+hdl_lib_uses_sim = 
+#hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
+
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+    $HDL_BUILD_DIR/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
+    src/vhdl/mmm_unb1_ddr3_transpose.vhd
+    src/vhdl/unb1_ddr3_transpose.vhd
+    
+test_bench_files = 
+    tb/vhdl/tb_unb1_ddr3_transpose.vhd
+
+synth_top_level_entity =
+
+quartus_copy_files =
+    quartus/sopc_unb_ddr3_transpose.sopc .
+
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    
+quartus_tcl_files =
+    quartus/unb1_ddr3_transpose_pins.tcl
+    quartus/unb_ddr3_transpose_pins_constraints.tcl
+    
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $HDL_BUILD_DIR/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
+    #$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    #$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+
+modelsim_compile_ip_files =
+#    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+
+
+modelsim_search_libraries =
+# stratixiv only
+    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
+    altera     lpm     sgate     altera_mf     altera_lnsim     stratixiv     stratixiv_hssi     stratixiv_pcie_hip
+# arria10 only
+#    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+#    altera     lpm     sgate     altera_mf     altera_lnsim     twentynm     twentynm_hssi     twentynm_hip
+# both (will yield errors if the technology library is not available in simulator but these errors can be ignored)
+#    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+#    altera     lpm     sgate     altera_mf     altera_lnsim     stratixiv     stratixiv_hssi     stratixiv_pcie_hip     twentynm     twentynm_hssi     twentynm_hip
+

boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl

+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+

boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/tc_unb_ddr3_transpose.py

+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (C) 2012
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+"""Test case for the unb_ddr3_transpose design.
+
+   Description:
+
+    
+   Usage in simulation:
+
+   > python tc_unb_ddr3_transpose.py --unb 0 --bn 3 --sim 
+
+"""
+
+###############################################################################
+# System imports
+import test_case
+import node_io
+import unb_apertif as apr
+import pi_diag_block_gen
+import pi_diag_data_buffer
+import pi_ss_ss_wide  
+import pi_bsn_monitor
+import dsp_test
+
+import sys, os
+import subprocess  
+import time
+import pylab as pl
+import numpy as np
+import scipy as sp
+import random
+from tools import *
+from common import *  
+import mem_init_file
+
+###############################################################################
+
+# Create a test case object
+tc = test_case.Testcase('TB - ', '')
+
+# Constants/Generics that are shared between VHDL and Python
+# Name                   Value   Default   Description
+# START_VHDL_GENERICS
+if tc.sim==True:
+    g_wr_chunksize    = 64 
+    g_wr_nof_chunks   = 1   
+    g_rd_chunksize    = 16  
+    g_rd_nof_chunks   = 4   
+    g_gapsize         = 0   
+    g_nof_blocks      = 4
+else:
+    g_wr_chunksize    = 64 # 256 
+    g_wr_nof_chunks   = 1  # 1   
+    g_rd_chunksize    = 16 # 16  
+    g_rd_nof_chunks   = 4  # 16   
+    g_gapsize         = 0  # 0   
+    g_nof_blocks      = 4 # 16
+
+# END_VHDL_GENERICS
+
+# Overwrite generics with argumented generics from autoscript or command line. 
+if tc.generics != None:  
+    g_wr_chunksize   = tc.generics['g_wr_chunksize']
+    g_wr_nof_chunks  = tc.generics['g_wr_nof_chunks']
+    g_rd_chunksize   = tc.generics['g_rd_chunksize']      
+    g_rd_nof_chunks  = tc.generics['g_rd_nof_chunks']    
+    g_gapsize        = tc.generics['g_gapsize']      
+    g_nof_blocks     = tc.generics['g_nof_blocks']      
+
+c_blocksize         = (g_wr_chunksize + g_gapsize) * g_wr_nof_chunks
+c_pagesize          = c_blocksize * g_nof_blocks
+c_bg_nof_streams    = 4 
+c_bg_ram_size       = g_wr_chunksize * g_wr_nof_chunks * g_rd_chunksize
+c_in_dat_w          = 8
+c_blocks_per_sync   = 1600000
+c_db_nof_streams    = c_bg_nof_streams
+c_db_ram_size       = c_bg_ram_size #g_rd_chunksize * g_rd_nof_chunks * g_nof_blocks
+c_frame_size_in     = g_wr_chunksize
+c_nof_int_streams   = 1
+c_ena_pre_transpose = False
+
+tc.append_log(3, '>>>')
+tc.append_log(1, '>>> Title : Test Case for unb_ddr3_transpose' )
+tc.append_log(3, '>>>')
+tc.append_log(3, '')
+tc.set_result('PASSED')
+
+# Create access object for nodes
+io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+# Create block generator instance
+bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, c_bg_nof_streams, c_bg_ram_size)
+
+# Create databuffer instances
+db_re = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName = 'RE', nofStreams=c_db_nof_streams, ramSizePerStream=c_db_ram_size)
+db_im = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName = 'IM', nofStreams=c_db_nof_streams, ramSizePerStream=c_db_ram_size)
+   
+# Create subandselect instance for pre-transpose.   
+ss = pi_ss_ss_wide.PiSsSsWide (tc, io, c_frame_size_in*g_rd_chunksize, c_nof_int_streams) 
+
+# BSN monitor
+bsn = pi_bsn_monitor.PiBsnMonitor(tc, io, instanceName='', nofStreams=2)
+
+# Create dsp_test instance for helpful methods
+dsp_test_bg = dsp_test.DspTest(inDatW=c_in_dat_w)
+
+# Function for generating stimuli and generating hex files. 
+def gen_bg_hex_files(c_nof_values = 1024, c_nof_streams = 4):
+    data = [] 
+    for i in range(c_nof_streams): 
+        stream_re = []
+        stream_im = []
+        for j in range(c_nof_values): 
+            stream_re.append(j)
+            stream_im.append(i)
+        data_concat = dsp_test_bg.concatenate_two_lists(stream_re, stream_im, c_in_dat_w)
+        data.append(data_concat)
+        filename = "../../src/hex/tb_bg_dat_" + str(i) + ".hex"
+        mem_init_file.list_to_hex(list_in=data_concat, filename=filename, mem_width=c_nof_complex*c_in_dat_w, mem_depth=2**(ceil_log2(c_bg_ram_size)))
+    return data
+
+if __name__ == "__main__":      
+    ###############################################################################
+    #
+    # Create setting for the pre-transpose (subbandselect)
+    #
+    ###############################################################################
+    bsn.read_bsn_monitor(0)
+    bsn.read_bsn_monitor(1)
+    
+    print "nof_words"
+    a=db_re.read_nof_words()
+    print a
+    ss_list = []
+    for i in range(c_frame_size_in):
+        for j in range(g_rd_chunksize):
+            ss_list.append(i + j*c_frame_size_in)
+
+    ss.write_selects(ss_list)
+    
+    ###############################################################################
+    #
+    # Create stimuli for the BG
+    #
+    ###############################################################################
+    # Prepare x stimuli for block generator
+    bg_data = gen_bg_hex_files(c_bg_ram_size, c_bg_nof_streams)
+ 
+    ################################################################################
+    ##
+    ## Write data and settings to block generator
+    ##
+    ################################################################################
+    # Write setting for the block generator:
+    bg.write_block_gen_settings(samplesPerPacket=c_frame_size_in, blocksPerSync=c_blocks_per_sync, gapSize=0, memLowAddr=0, memHighAddr=c_bg_ram_size-1, BSNInit=10)
+    
+    # Write the stimuli to the block generator and enable the block generator
+    for i in range(c_bg_nof_streams):
+        bg.write_waveform_ram(data=bg_data[i], channelNr= i)
+
+    # Concatenate all channels 
+    t=2
+    while len(bg_data) > 1:
+        concat_data = []
+        for i in range(len(bg_data)/2):
+            concat_data.append(dsp_test_bg.concatenate_two_lists(bg_data[2*i], bg_data[2*i+1], c_in_dat_w*t))
+        bg_data = concat_data
+        t=t*2
+    
+    bg_data = flatten(bg_data)  
+    
+#    for i in range(len(bg_data)):
+#        print ">%X<" % bg_data[i]
+    
+    ###############################################################################
+    #
+    # Calculate reference data
+    #
+    ###############################################################################
+    # Subband Select pre-transpose 
+    if c_ena_pre_transpose:
+        bg_data = ss.subband_select(bg_data, ss_list)    
+
+    ref_data_total = []
+    # Check how many data there is and how many pages will be used:
+    for t in range(len(bg_data)/c_pagesize):     
+        bg_data_single_page = bg_data[t*c_pagesize:(t+1)*c_pagesize]
+        # Write to memory
+        mem_page = [0] * c_pagesize   
+        for i in range(g_nof_blocks):
+            for j in range(g_wr_nof_chunks):
+                for k in range(g_wr_chunksize):
+                    mem_page[i*c_blocksize*g_wr_nof_chunks + j*c_blocksize + k] = bg_data_single_page[i*g_wr_chunksize*g_wr_nof_chunks + j*g_wr_chunksize + k]
+        
+        # Read from memory
+        ref_data = [0] * g_nof_blocks * g_rd_nof_chunks * g_rd_chunksize
+        chunk_cnt = 0
+        chunk_offset = 0
+        for i in range(g_nof_blocks):
+            for j in range(g_rd_nof_chunks):
+                if chunk_cnt == g_nof_blocks:
+                    chunk_cnt = 0
+                    chunk_offset = chunk_offset + 1
+                for k in range(g_rd_chunksize):
+                    #ref_data[chunk_cnt*(g_rd_chunksize*g_rd_nof_chunks)+ chunk_offset*g_rd_chunksize + k] = mem_page[chunk_cnt*(g_rd_chunksize*g_rd_nof_chunks+g_gapsize)+ chunk_offset*g_rd_chunksize + k]
+                    ref_data[i*(g_rd_chunksize*g_rd_nof_chunks)+j*g_rd_chunksize + k] = mem_page[chunk_cnt*(g_rd_chunksize*g_rd_nof_chunks+g_gapsize)+ chunk_offset*g_rd_chunksize + k]
+                chunk_cnt = chunk_cnt + 1    
+        ref_data_total.append(ref_data)
+        
+    ref_data_total=flatten(ref_data_total)    
+    
+    # Split the data again in individual channels 
+    ref_data_split = []
+    ref_data_split.append(ref_data_total)
+    t = c_bg_nof_streams
+    while len(ref_data_split) < c_bg_nof_streams:
+        ref_data_temp = []
+        for i in range(len(ref_data_split)):
+            [data_a, data_b] = dsp_test_bg.split_in_two_lists(ref_data_split[i], c_in_dat_w*t)
+            ref_data_temp.append(data_a)
+            ref_data_temp.append(data_b) 
+        ref_data_split = ref_data_temp
+        t = t/2
+    
+    ref_data_re = []
+    ref_data_im = []
+    # Split the data in real and imaginary
+    for i in range(c_bg_nof_streams):
+        [data_re, data_im] = dsp_test_bg.split_in_two_lists(ref_data_split[i], c_in_dat_w)
+        ref_data_re.append(data_re)
+        ref_data_im.append(data_im)
+
+#    print "real + imag"     
+#    for i in range(len(ref_data_re)):
+#        for j in range(len(ref_data_re[i])):
+#            print "concat: >%X< real: >%X<  imag: >%X< " % (ref_data_split[i][j], ref_data_re[i][j], ref_data_im[i][j])
+#        print
+#    
+
+    # Wait until the DDR3 model is initialized. 
+    if tc.sim==True:
+        do_until_gt(io.simIO.getSimTime, ms_retry=1000, val=110000, s_timeout=13600)  # 110000 
+        
+    # Enable the blockgenerator
+    bg.write_enable()
+
+    # Poll the databuffer to check if the response is there.
+    # Retry after 3 seconds so we don't issue too many MM reads in case of simulation.
+    # time.sleep(5) 
+    do_until_ge(db_re.read_nof_words, ms_retry=3000, val=c_db_ram_size, s_timeout=3600)
+
+    ###############################################################################
+    #
+    # Read transposed data from data buffer
+    #
+    ###############################################################################
+    db_out_re = []
+    db_out_im = []
+    for i in range(c_bg_nof_streams): 
+        db_out_re.append(flatten(db_re.read_data_buffer(streamNr=i, n=c_db_ram_size, radix='uns', width=c_in_dat_w, nofColumns=8)))
+        db_out_im.append(flatten(db_im.read_data_buffer(streamNr=i, n=c_db_ram_size, radix='uns', width=c_in_dat_w, nofColumns=8)))
+
+    bsn.read_bsn_monitor(0)
+    bsn.read_bsn_monitor(1)
+
+    ###############################################################################
+    #
+    # Verify output data
+    #
+    ###############################################################################
+    for i in range(c_bg_nof_streams): 
+        for j in range(c_db_ram_size):
+            if db_out_re[i][j] != ref_data_re[i][j]:
+                tc.append_log(2, 'Error in real output data. Expected data: %d Data read: %d Iteration nr: %d %d' % (ref_data_re[i][j], db_out_re[i][j], i, j))
+                tc.set_result('FAILED')
+            if db_out_im[i][j] != ref_data_im[i][j]:
+                tc.append_log(2, 'Error in imag output data. Expected data: %d Data read: %d Iteration nr: %d %d' % (ref_data_im[i][j], db_out_im[i][j], i, j))
+                tc.set_result('FAILED')
+   
+    ###############################################################################
+    # End
+    tc.set_section_id('')
+    tc.append_log(3, '')
+    tc.append_log(3, '>>>')
+    tc.append_log(0, '>>> Test bench result: %s' % tc.get_result())
+    tc.append_log(3, '>>>')
+    
+    sys.exit(tc.get_result())

boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/unb_ddr3_transpose.py

+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (C) 2013
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+"""
+On execution, this script will start ModelSim, compile and run DESIGN_NAME and
+run COMMANDS against the running simulation. If --hold is not passed, the running
+simulation will be killed after completion.
+"""
+import sys, os
+sys.path.append(os.environ['UNB']+'/Firmware/sim/python')
+from auto_sim import *
+
+LIBRARY_NAME = 'unb_ddr3_transpose'
+TB_NAME      = 'tb_unb_ddr3_transpose'   
+TARGET_NODES = ' --unb 0 --bn 3 '
+COMMANDS     = ['$UPE/peripherals/util_system_info.py' +TARGET_NODES+ '-n 2',
+                '$UPE/peripherals/util_system_info.py' +TARGET_NODES+ '-n 4',
+                '$UPE/peripherals/util_unb_sens.py'    +TARGET_NODES+ '-n 0'
+               ]
+
+# Give sim some time until the sensors have been read
+INIT_DELAY_NS = 5000
+
+GENERICS = {}
+OTHER = ''
+    
+# Run the sim and return its result using sys.exit([return_value])
+sys.exit(auto_sim(os.environ['UNB'], LIBRARY_NAME, TB_NAME, COMMANDS, INIT_DELAY_NS, GENERICS, OTHER))
\ No newline at end of file

boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for unb_ddrs_transpose.
+--          The DUT can be targeted at unb 0, bn3 with the same Python scripts 
+--          that are used on hardware. 
+
+
+LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, ddr3_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;  
+USE ddr3_lib.ddr3_pkg.ALL;
+
+ENTITY tb_unb1_ddr3_transpose IS
+END tb_unb1_ddr3_transpose;
+
+ARCHITECTURE tb OF tb_unb1_ddr3_transpose IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 7; -- Back node 3
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w ) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
+
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb1_board_fw_version := (1, 0);
+
+  CONSTANT c_cable_delay     : TIME := 12 ns;
+  CONSTANT c_eth_clk_period  : TIME := 40 ns;  -- 25 MHz XO on UniBoard
+  CONSTANT c_clk_period      : TIME := 5 ns; 
+  CONSTANT c_pps_period      : NATURAL := 1000;  
+  
+  CONSTANT c_ddr             : t_c_ddr3_phy := c_ddr3_phy_4g;
+
+  -- DUT
+  SIGNAL clk                 : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL pps_rst             : STD_LOGIC := '0';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC;
+  SIGNAL eth_rxp             : STD_LOGIC;
+  
+  SIGNAL VERSION             : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version; 
+  SIGNAL ID                  : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0)      := c_id;
+  SIGNAL TESTIO              : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;    
+  
+    -- Signals to interface with the DDR3 memory model.
+  SIGNAL phy_in              : t_ddr3_phy_in_arr(0 DOWNTO 0);
+  SIGNAL phy_io              : t_ddr3_phy_io_arr(0 DOWNTO 0);
+  SIGNAL phy_ou              : t_ddr3_phy_ou_arr(0 DOWNTO 0);   
+  
+  SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL we_n  : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+  -- Model I2C sensor slaves as on the UniBoard
+  CONSTANT c_fpga_temp_address   : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000";  -- MAX1618 address LOW LOW
+  CONSTANT c_fpga_temp           : INTEGER := 60;
+  CONSTANT c_eth_temp_address    : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0101001";  -- MAX1618 address MID LOW
+  CONSTANT c_eth_temp            : INTEGER := 40;
+  CONSTANT c_hot_swap_address    : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1000100";  -- LTC4260 address L L L
+  CONSTANT c_hot_swap_R_sense    : REAL := 0.01;                               -- = 10 mOhm on UniBoard
+  
+  CONSTANT c_uniboard_current    : REAL := 5.0;   -- = assume 5.0 A on UniBoard
+  CONSTANT c_uniboard_supply     : REAL := 48.0;  -- = assume 48.0 V on UniBoard
+  CONSTANT c_uniboard_adin       : REAL := -1.0;  -- = NC on UniBoard
+
+BEGIN
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  clk     <= NOT clk AFTER c_clk_period/2;        -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (25 MHz)
+  
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+
+  ------------------------------------------------------------------------------
+  -- 1GbE Loopback model
+  ------------------------------------------------------------------------------  
+  eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay;
+  
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_unb1_ddr3_transpose : ENTITY work.unb1_ddr3_transpose
+    GENERIC MAP (
+      g_sim         => c_sim,
+      g_sim_unb_nr  => c_unb_nr,
+      g_sim_node_nr => c_node_nr
+    )
+    PORT MAP (
+      -- GENERAL
+      CLK         => clk,
+      PPS         => pps,
+      WDI         => WDI,
+      INTA        => INTA,
+      INTB        => INTB,
+
+      sens_sc     => sens_scl,
+      sens_sd     => sens_sda,
+
+      -- Others
+      VERSION     => VERSION,
+      ID          => ID,
+      TESTIO      => TESTIO,
+
+      -- 1GbE Control Interface
+      ETH_clk     => eth_clk,
+      ETH_SGIN    => eth_rxp,
+      ETH_SGOUT   => eth_txp,
+      
+      MB_I_in     => phy_in, 
+      MB_I_io     => phy_io, 
+      MB_I_ou     => phy_ou 
+      
+    );
+
+  ------------------------------------------------------------------------------
+  -- UniBoard sensors
+  ------------------------------------------------------------------------------
+  -- I2C slaves that are available for each FPGA
+  u_fpga_temp : ENTITY i2c_lib.dev_max1618
+  GENERIC MAP (
+    g_address => c_fpga_temp_address
+  )
+  PORT MAP (
+    scl  => sens_scl,
+    sda  => sens_sda,
+    temp => c_fpga_temp
+  );
+
+  -- I2C slaves that are available only via FPGA back node 3
+  u_eth_temp : ENTITY i2c_lib.dev_max1618
+  GENERIC MAP (
+    g_address => c_eth_temp_address
+  )
+  PORT MAP (
+    scl  => sens_scl,
+    sda  => sens_sda,
+    temp => c_eth_temp
+  );
+  
+  u_power : ENTITY i2c_lib.dev_ltc4260
+  GENERIC MAP (
+    g_address => c_hot_swap_address,
+    g_R_sense => c_hot_swap_R_sense
+  )
+  PORT MAP (
+    scl               => sens_scl,
+    sda               => sens_sda,
+    ana_current_sense => c_uniboard_current,
+    ana_volt_source   => c_uniboard_supply,
+    ana_volt_adin     => c_uniboard_adin
+  ); 
+  
+  -- DDR3 Model 
+  u_4gb_800_ddr3_model : COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
+	GENERIC MAP (
+		MEM_IF_ADDR_WIDTH            => 15,
+		MEM_IF_ROW_ADDR_WIDTH        => 15,
+		MEM_IF_COL_ADDR_WIDTH        => 10,
+		MEM_IF_CS_PER_RANK           => 1,
+		MEM_IF_CONTROL_WIDTH         => 1,
+		MEM_IF_DQS_WIDTH             => 8,
+		MEM_IF_CS_WIDTH              => 2,
+		MEM_IF_BANKADDR_WIDTH        => 3,
+		MEM_IF_DQ_WIDTH              => 64,
+		MEM_IF_CK_WIDTH              => 2,
+		MEM_IF_CLK_EN_WIDTH          => 2,
+		DEVICE_WIDTH                 => 1,
+		MEM_TRCD                     => 6,
+		MEM_TRTP                     => 3,
+		MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
+		MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
+		MEM_IF_ODT_WIDTH             => 2,
+		MEM_MIRROR_ADDRESSING_DEC    => 0,
+		MEM_REGDIMM_ENABLED          => false,
+		DEVICE_DEPTH                 => 1,
+		MEM_GUARANTEED_WRITE_INIT    => false,
+		MEM_VERBOSE                  => true,
+		MEM_INIT_EN                  => false,
+		MEM_INIT_FILE                => "",
+		DAT_DATA_WIDTH               => 32
+	)
+  PORT MAP (
+		mem_a       => phy_ou(0).a(c_ddr.a_w-1 DOWNTO 0),      
+		mem_ba      => phy_ou(0).ba,       
+		mem_ck      => phy_io(0).clk,      
+		mem_ck_n    => phy_io(0).clk_n,    
+		mem_cke     => phy_ou(0).cke(c_ddr.cs_w-1 DOWNTO 0),   
+		mem_cs_n    => phy_ou(0).cs_n(c_ddr.cs_w-1 DOWNTO 0),  
+		mem_dm      => phy_ou(0).dm,       
+		mem_ras_n   => ras_n,           
+		mem_cas_n   => cas_n,           
+		mem_we_n    => we_n,            
+		mem_reset_n => phy_ou(0).reset_n, 
+		mem_dq      => phy_io(0).dq,       
+		mem_dqs     => phy_io(0).dqs,      
+		mem_dqs_n   => phy_io(0).dqs_n,    
+		mem_odt     => phy_ou(0).odt       
+	);               
+	
+  ras_n(0) <= phy_ou(0).ras_n;
+  cas_n(0) <= phy_ou(0).cas_n;
+  we_n(0)  <= phy_ou(0).we_n;
+
+  
+
+END tb;