From 88ee5e5111a6281de5085f3dbb07b2efc96f18de Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Thu, 2 Apr 2015 07:38:47 +0000
Subject: [PATCH] ported unb_ddr3_transpose to radiohdl
---
.../designs/unb1_ddr3_transpose/hdllib.cfg | 53 +
.../quartus/sopc_unb_ddr3_transpose.sopc | 1186 +++++++++++++++++
.../quartus/unb1_ddr3_transpose_pins.tcl | 7 +
.../unb_ddr3_transpose_pins_constraints.tcl | 517 +++++++
.../src/vhdl/mmm_unb1_ddr3_transpose.vhd | 369 +++++
.../src/vhdl/unb1_ddr3_transpose.vhd | 522 ++++++++
.../tb/python/tc_unb_ddr3_transpose.py | 308 +++++
.../tb/python/unb_ddr3_transpose.py | 46 +
.../tb/vhdl/tb_unb1_ddr3_transpose.vhd | 249 ++++
9 files changed, 3257 insertions(+)
create mode 100644 boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
create mode 100644 boards/uniboard1/designs/unb1_ddr3_transpose/quartus/sopc_unb_ddr3_transpose.sopc
create mode 100644 boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl
create mode 100644 boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb_ddr3_transpose_pins_constraints.tcl
create mode 100644 boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
create mode 100644 boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
create mode 100644 boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/tc_unb_ddr3_transpose.py
create mode 100644 boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/unb_ddr3_transpose.py
create mode 100644 boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
new file mode 100644
index 0000000000..610cae3fa9
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -0,0 +1,53 @@
+hdl_lib_name = unb1_ddr3_transpose
+hdl_library_clause_name = unb1_ddr3_transpose_lib
+hdl_lib_uses_synth = common mm i2c unb1_board dp eth diagnostics ddr3
+hdl_lib_uses_sim =
+#hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
+
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+ $HDL_BUILD_DIR/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
+ src/vhdl/mmm_unb1_ddr3_transpose.vhd
+ src/vhdl/unb1_ddr3_transpose.vhd
+
+test_bench_files =
+ tb/vhdl/tb_unb1_ddr3_transpose.vhd
+
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus/sopc_unb_ddr3_transpose.sopc .
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_tcl_files =
+ quartus/unb1_ddr3_transpose_pins.tcl
+ quartus/unb_ddr3_transpose_pins_constraints.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $HDL_BUILD_DIR/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
+ #$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ #$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+
+modelsim_compile_ip_files =
+# $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+
+
+modelsim_search_libraries =
+# stratixiv only
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
+ altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
+# arria10 only
+# altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+# altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
+# both (will yield errors if the technology library is not available in simulator but these errors can be ignored)
+# altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+# altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip twentynm twentynm_hssi twentynm_hip
+
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/sopc_unb_ddr3_transpose.sopc b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/sopc_unb_ddr3_transpose.sopc
new file mode 100644
index 0000000000..156b2a0e0c
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/sopc_unb_ddr3_transpose.sopc
@@ -0,0 +1,1186 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="sopc_unb_ddr3_transpose">
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element altpll_0
+ {
+ datum _sortIndex
+ {
+ value = "1";
+ type = "int";
+ }
+ }
+ element jtag_uart_0.avalon_jtag_slave
+ {
+ datum baseAddress
+ {
+ value = "720";
+ type = "long";
+ }
+ }
+ element avs_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ }
+ element altpll_0.c0
+ {
+ datum _clockDomain
+ {
+ value = "mm_clk";
+ type = "String";
+ }
+ }
+ element altpll_0.c2
+ {
+ datum _clockDomain
+ {
+ value = "tse_clk";
+ type = "String";
+ }
+ }
+ element clk_0
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ }
+ element cpu_0
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element cpu_0.jtag_debug_module
+ {
+ datum baseAddress
+ {
+ value = "14336";
+ type = "long";
+ }
+ }
+ element jtag_uart_0
+ {
+ datum _sortIndex
+ {
+ value = "3";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element ram_ss_ss_wide.mem
+ {
+ datum baseAddress
+ {
+ value = "69632";
+ type = "long";
+ }
+ }
+ element ram_diag_data_buffer_re.mem
+ {
+ datum baseAddress
+ {
+ value = "32768";
+ type = "long";
+ }
+ }
+ element reg_diag_bg.mem
+ {
+ datum baseAddress
+ {
+ value = "640";
+ type = "long";
+ }
+ }
+ element ram_diag_bg.mem
+ {
+ datum baseAddress
+ {
+ value = "49152";
+ type = "long";
+ }
+ }
+ element ram_diag_data_buffer_im.mem
+ {
+ datum baseAddress
+ {
+ value = "16384";
+ type = "long";
+ }
+ }
+ element reg_diag_data_buffer_im.mem
+ {
+ datum baseAddress
+ {
+ value = "128";
+ type = "long";
+ }
+ }
+ element pio_pps.mem
+ {
+ datum baseAddress
+ {
+ value = "728";
+ type = "long";
+ }
+ }
+ element reg_wdi.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "12288";
+ type = "long";
+ }
+ }
+ element reg_bsn_monitor.mem
+ {
+ datum baseAddress
+ {
+ value = "384";
+ type = "long";
+ }
+ }
+ element reg_unb_sens.mem
+ {
+ datum baseAddress
+ {
+ value = "608";
+ type = "long";
+ }
+ }
+ element reg_diag_data_buffer_re.mem
+ {
+ datum baseAddress
+ {
+ value = "256";
+ type = "long";
+ }
+ }
+ element rom_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "4096";
+ type = "long";
+ }
+ }
+ element pio_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "0";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_ram
+ {
+ datum baseAddress
+ {
+ value = "65536";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_reg
+ {
+ datum baseAddress
+ {
+ value = "512";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_tse
+ {
+ datum baseAddress
+ {
+ value = "8192";
+ type = "long";
+ }
+ }
+ element onchip_memory2_0
+ {
+ datum _sortIndex
+ {
+ value = "2";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{output_language=VHDL, output_directory=D:\\svnroot\\UniBoard_FP7\\UniBoard\\trunk\\Firmware\\designs\\unb_unb_ddr3_transpose\\build\\synth\\quartus}";
+ type = "String";
+ }
+ }
+ element pio_debug_wave
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+ element pio_pps
+ {
+ datum _sortIndex
+ {
+ value = "12";
+ type = "int";
+ }
+ }
+ element pio_system_info
+ {
+ datum _sortIndex
+ {
+ value = "11";
+ type = "int";
+ }
+ }
+ element pio_wdi
+ {
+ datum _sortIndex
+ {
+ value = "6";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element altpll_0.pll_slave
+ {
+ datum _lockedAddress
+ {
+ value = "0";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "672";
+ type = "long";
+ }
+ }
+ element ram_diag_bg
+ {
+ datum _sortIndex
+ {
+ value = "19";
+ type = "int";
+ }
+ }
+ element ram_diag_data_buffer_im
+ {
+ datum _sortIndex
+ {
+ value = "17";
+ type = "int";
+ }
+ }
+ element ram_diag_data_buffer_re
+ {
+ datum _sortIndex
+ {
+ value = "18";
+ type = "int";
+ }
+ }
+ element ram_ss_ss_wide
+ {
+ datum _sortIndex
+ {
+ value = "20";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor
+ {
+ datum _sortIndex
+ {
+ value = "21";
+ type = "int";
+ }
+ }
+ element reg_diag_bg
+ {
+ datum _sortIndex
+ {
+ value = "14";
+ type = "int";
+ }
+ }
+ element reg_diag_data_buffer_im
+ {
+ datum _sortIndex
+ {
+ value = "15";
+ type = "int";
+ }
+ }
+ element reg_diag_data_buffer_re
+ {
+ datum _sortIndex
+ {
+ value = "16";
+ type = "int";
+ }
+ }
+ element reg_unb_sens
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ }
+ element reg_wdi
+ {
+ datum _sortIndex
+ {
+ value = "13";
+ type = "int";
+ }
+ }
+ element rom_system_info
+ {
+ datum _sortIndex
+ {
+ value = "10";
+ type = "int";
+ }
+ }
+ element pio_debug_wave.s1
+ {
+ datum baseAddress
+ {
+ value = "688";
+ type = "long";
+ }
+ }
+ element onchip_memory2_0.s1
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "131072";
+ type = "long";
+ }
+ }
+ element timer_0.s1
+ {
+ datum baseAddress
+ {
+ value = "576";
+ type = "long";
+ }
+ }
+ element pio_wdi.s1
+ {
+ datum baseAddress
+ {
+ value = "704";
+ type = "long";
+ }
+ }
+ element sopc_unb_ddr3_transpose
+ {
+ }
+ element timer_0
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="EP4SGX230KF40C2" />
+ <parameter name="deviceFamily" value="STRATIXIV" />
+ <parameter name="deviceSpeedGrade" value="" />
+ <parameter name="fabricMode" value="SOPC" />
+ <parameter name="generateLegacySim" value="true" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="true" />
+ <parameter name="hdlLanguage" value="VHDL" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName">unb_ddr3_transpose.qpf</parameter>
+ <parameter name="sopcBorderPoints" value="true" />
+ <parameter name="systemHash" value="-54082890877" />
+ <parameter name="timeStamp" value="1418900184248" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <module kind="clock_source" version="11.1" enabled="1" name="clk_0">
+ <parameter name="clockFrequency" value="25000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module kind="altera_nios2" version="11.1" enabled="1" name="cpu_0">
+ <parameter name="userDefinedSettings" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_shadowRegisterSets" value="0" />
+ <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_preciseDivisionErrorException" value="false" />
+ <parameter name="setting_performanceCounter" value="false" />
+ <parameter name="setting_perfCounterWidth" value="_32" />
+ <parameter name="setting_interruptControllerType" value="Internal" />
+ <parameter name="setting_illegalMemAccessDetection" value="false" />
+ <parameter name="setting_illegalInstructionsTrap" value="false" />
+ <parameter name="setting_fullWaveformSignals" value="false" />
+ <parameter name="setting_extraExceptionInfo" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_debugSimGen" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+ <parameter name="setting_branchPredictionType" value="Automatic" />
+ <parameter name="setting_bit31BypassDCache" value="true" />
+ <parameter name="setting_bigEndian" value="false" />
+ <parameter name="setting_bhtPtrSz" value="_8" />
+ <parameter name="setting_bhtIndexPcOnly" value="false" />
+ <parameter name="setting_avalonDebugPortPresent" value="false" />
+ <parameter name="setting_alwaysEncrypt" value="true" />
+ <parameter name="setting_allowFullAddressRange" value="false" />
+ <parameter name="setting_activateTrace" value="true" />
+ <parameter name="setting_activateTestEndChecker" value="false" />
+ <parameter name="setting_activateMonitors" value="true" />
+ <parameter name="setting_activateModelChecker" value="false" />
+ <parameter name="setting_HDLSimCachesCleared" value="true" />
+ <parameter name="setting_HBreakTest" value="false" />
+ <parameter name="resetSlave" value="onchip_memory2_0.s1" />
+ <parameter name="resetOffset" value="0" />
+ <parameter name="muldiv_multiplierType" value="DSPBlock" />
+ <parameter name="muldiv_divider" value="false" />
+ <parameter name="mpu_useLimit" value="false" />
+ <parameter name="mpu_numOfInstRegion" value="8" />
+ <parameter name="mpu_numOfDataRegion" value="8" />
+ <parameter name="mpu_minInstRegionSize" value="_12" />
+ <parameter name="mpu_minDataRegionSize" value="_12" />
+ <parameter name="mpu_enabled" value="false" />
+ <parameter name="mmu_uitlbNumEntries" value="_4" />
+ <parameter name="mmu_udtlbNumEntries" value="_6" />
+ <parameter name="mmu_tlbPtrSz" value="_7" />
+ <parameter name="mmu_tlbNumWays" value="_16" />
+ <parameter name="mmu_processIDNumBits" value="_8" />
+ <parameter name="mmu_enabled" value="false" />
+ <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+ <parameter name="mmu_TLBMissExcSlave" value="" />
+ <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="manuallyAssignCpuID" value="false" />
+ <parameter name="internalIrqMaskSystemInfo" value="7" />
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="instAddrWidth" value="18" />
+ <parameter name="impl" value="Small" />
+ <parameter name="icache_size" value="_4096" />
+ <parameter name="icache_ramBlockType" value="Automatic" />
+ <parameter name="icache_numTCIM" value="_0" />
+ <parameter name="icache_burstType" value="None" />
+ <parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
+ <parameter name="exceptionOffset" value="32" />
+ <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 1 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 1 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ <parameter name="deviceFamilyName" value="Stratix IV" />
+ <parameter name="debug_triggerArming" value="true" />
+ <parameter name="debug_level" value="Level1" />
+ <parameter name="debug_jtagInstanceID" value="0" />
+ <parameter name="debug_embeddedPLL" value="true" />
+ <parameter name="debug_debugReqSignals" value="false" />
+ <parameter name="debug_assignJtagInstanceID" value="false" />
+ <parameter name="debug_OCIOnchipTrace" value="_128" />
+ <parameter name="dcache_size" value="_2048" />
+ <parameter name="dcache_ramBlockType" value="Automatic" />
+ <parameter name="dcache_omitDataMaster" value="false" />
+ <parameter name="dcache_numTCDM" value="_0" />
+ <parameter name="dcache_lineSize" value="_32" />
+ <parameter name="dcache_bursts" value="false" />
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_im.mem' start='0x80' end='0x100' /><slave name='reg_diag_data_buffer_re.mem' start='0x100' end='0x180' /><slave name='reg_bsn_monitor.mem' start='0x180' end='0x200' /><slave name='avs_eth_0.mms_reg' start='0x200' end='0x240' /><slave name='timer_0.s1' start='0x240' end='0x260' /><slave name='reg_unb_sens.mem' start='0x260' end='0x280' /><slave name='reg_diag_bg.mem' start='0x280' end='0x2A0' /><slave name='altpll_0.pll_slave' start='0x2A0' end='0x2B0' /><slave name='pio_debug_wave.s1' start='0x2B0' end='0x2C0' /><slave name='pio_wdi.s1' start='0x2C0' end='0x2D0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x2D0' end='0x2D8' /><slave name='pio_pps.mem' start='0x2D8' end='0x2E0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_diag_data_buffer_im.mem' start='0x4000' end='0x8000' /><slave name='ram_diag_data_buffer_re.mem' start='0x8000' end='0xC000' /><slave name='ram_diag_bg.mem' start='0xC000' end='0x10000' /><slave name='avs_eth_0.mms_ram' start='0x10000' end='0x11000' /><slave name='ram_ss_ss_wide.mem' start='0x11000' end='0x12000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="dataAddrWidth" value="18" />
+ <parameter name="customInstSlavesSystemInfo" value="<info/>" />
+ <parameter name="cpuReset" value="false" />
+ <parameter name="cpuID" value="0" />
+ <parameter name="clockFrequency" value="50000000" />
+ <parameter name="breakSlave">cpu_0.jtag_debug_module</parameter>
+ <parameter name="breakOffset" value="32" />
+ </module>
+ <module
+ kind="altera_avalon_onchip_memory2"
+ version="11.1"
+ enabled="1"
+ name="onchip_memory2_0">
+ <parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="autoInitializationFileName" value="onchip_memory2_0" />
+ <parameter name="blockType" value="M144K" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="deviceFamily" value="Stratix IV" />
+ <parameter name="dualPort" value="false" />
+ <parameter name="initMemContent" value="true" />
+ <parameter name="initializationFileName" value="onchip_memory2_0" />
+ <parameter name="instanceID" value="NONE" />
+ <parameter name="memorySize" value="131072" />
+ <parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="simAllowMRAMContentsFile" value="false" />
+ <parameter name="simMemInitOnlyFilename" value="0" />
+ <parameter name="singleClockOperation" value="false" />
+ <parameter name="slave1Latency" value="1" />
+ <parameter name="slave2Latency" value="1" />
+ <parameter name="useNonDefaultInitFile" value="false" />
+ <parameter name="useShallowMemBlocks" value="false" />
+ <parameter name="writable" value="true" />
+ </module>
+ <module
+ kind="altera_avalon_jtag_uart"
+ version="11.1"
+ enabled="1"
+ name="jtag_uart_0">
+ <parameter name="allowMultipleConnections" value="false" />
+ <parameter name="hubInstanceID" value="0" />
+ <parameter name="readBufferDepth" value="64" />
+ <parameter name="readIRQThreshold" value="8" />
+ <parameter name="simInputCharacterStream"><![CDATA[a
+q]]></parameter>
+ <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
+ <parameter name="useRegistersForReadBuffer" value="false" />
+ <parameter name="useRegistersForWriteBuffer" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ <parameter name="writeBufferDepth" value="64" />
+ <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module kind="altpll" version="11.1" enabled="1" name="altpll_0">
+ <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+ <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+ <parameter name="INTENDED_DEVICE_FAMILY" value="Stratix IV" />
+ <parameter name="WIDTH_CLOCK" value="10" />
+ <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ <parameter name="PRIMARY_CLOCK" value="" />
+ <parameter name="INCLK0_INPUT_FREQUENCY" value="40000" />
+ <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+ <parameter name="OPERATION_MODE" value="NORMAL" />
+ <parameter name="PLL_TYPE" value="AUTO" />
+ <parameter name="QUALIFY_CONF_DONE" value="" />
+ <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+ <parameter name="SCAN_CHAIN" value="" />
+ <parameter name="GATE_LOCK_SIGNAL" value="" />
+ <parameter name="GATE_LOCK_COUNTER" value="" />
+ <parameter name="LOCK_HIGH" value="" />
+ <parameter name="LOCK_LOW" value="" />
+ <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+ <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+ <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+ <parameter name="SKIP_VCO" value="" />
+ <parameter name="SWITCH_OVER_COUNTER" value="" />
+ <parameter name="SWITCH_OVER_TYPE" value="" />
+ <parameter name="FEEDBACK_SOURCE" value="" />
+ <parameter name="BANDWIDTH" value="" />
+ <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+ <parameter name="SPREAD_FREQUENCY" value="" />
+ <parameter name="DOWN_SPREAD" value="" />
+ <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+ <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+ <parameter name="CLK0_MULTIPLY_BY" value="2" />
+ <parameter name="CLK1_MULTIPLY_BY" value="4" />
+ <parameter name="CLK2_MULTIPLY_BY" value="5" />
+ <parameter name="CLK3_MULTIPLY_BY" value="8" />
+ <parameter name="CLK4_MULTIPLY_BY" value="" />
+ <parameter name="CLK5_MULTIPLY_BY" value="" />
+ <parameter name="CLK6_MULTIPLY_BY" value="" />
+ <parameter name="CLK7_MULTIPLY_BY" value="" />
+ <parameter name="CLK8_MULTIPLY_BY" value="" />
+ <parameter name="CLK9_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+ <parameter name="CLK0_DIVIDE_BY" value="1" />
+ <parameter name="CLK1_DIVIDE_BY" value="5" />
+ <parameter name="CLK2_DIVIDE_BY" value="1" />
+ <parameter name="CLK3_DIVIDE_BY" value="5" />
+ <parameter name="CLK4_DIVIDE_BY" value="" />
+ <parameter name="CLK5_DIVIDE_BY" value="" />
+ <parameter name="CLK6_DIVIDE_BY" value="" />
+ <parameter name="CLK7_DIVIDE_BY" value="" />
+ <parameter name="CLK8_DIVIDE_BY" value="" />
+ <parameter name="CLK9_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+ <parameter name="CLK0_PHASE_SHIFT" value="0" />
+ <parameter name="CLK1_PHASE_SHIFT" value="0" />
+ <parameter name="CLK2_PHASE_SHIFT" value="0" />
+ <parameter name="CLK3_PHASE_SHIFT" value="0" />
+ <parameter name="CLK4_PHASE_SHIFT" value="" />
+ <parameter name="CLK5_PHASE_SHIFT" value="" />
+ <parameter name="CLK6_PHASE_SHIFT" value="" />
+ <parameter name="CLK7_PHASE_SHIFT" value="" />
+ <parameter name="CLK8_PHASE_SHIFT" value="" />
+ <parameter name="CLK9_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+ <parameter name="CLK0_DUTY_CYCLE" value="50" />
+ <parameter name="CLK1_DUTY_CYCLE" value="50" />
+ <parameter name="CLK2_DUTY_CYCLE" value="50" />
+ <parameter name="CLK3_DUTY_CYCLE" value="50" />
+ <parameter name="CLK4_DUTY_CYCLE" value="" />
+ <parameter name="CLK5_DUTY_CYCLE" value="" />
+ <parameter name="CLK6_DUTY_CYCLE" value="" />
+ <parameter name="CLK7_DUTY_CYCLE" value="" />
+ <parameter name="CLK8_DUTY_CYCLE" value="" />
+ <parameter name="CLK9_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+ <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+ <parameter name="PORT_extclkena0" value="" />
+ <parameter name="PORT_extclkena1" value="" />
+ <parameter name="PORT_extclkena2" value="" />
+ <parameter name="PORT_extclkena3" value="" />
+ <parameter name="PORT_extclk0" value="" />
+ <parameter name="PORT_extclk1" value="" />
+ <parameter name="PORT_extclk2" value="" />
+ <parameter name="PORT_extclk3" value="" />
+ <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+ <parameter name="PORT_clk0" value="PORT_USED" />
+ <parameter name="PORT_clk1" value="PORT_UNUSED" />
+ <parameter name="PORT_clk2" value="PORT_USED" />
+ <parameter name="PORT_clk3" value="PORT_UNUSED" />
+ <parameter name="PORT_clk4" value="PORT_UNUSED" />
+ <parameter name="PORT_clk5" value="PORT_UNUSED" />
+ <parameter name="PORT_clk6" value="PORT_UNUSED" />
+ <parameter name="PORT_clk7" value="PORT_UNUSED" />
+ <parameter name="PORT_clk8" value="PORT_UNUSED" />
+ <parameter name="PORT_clk9" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_SCLKOUT1" value="" />
+ <parameter name="PORT_SCLKOUT0" value="" />
+ <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+ <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+ <parameter name="PORT_INCLK0" value="PORT_USED" />
+ <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+ <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+ <parameter name="PORT_ARESET" value="PORT_UNUSED" />
+ <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+ <parameter name="PORT_ENABLE0" value="" />
+ <parameter name="PORT_ENABLE1" value="" />
+ <parameter name="PORT_LOCKED" value="PORT_USED" />
+ <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+ <parameter name="PORT_FBOUT" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+ <parameter name="PORT_VCOOVERRANGE" value="" />
+ <parameter name="PORT_VCOUNDERRANGE" value="" />
+ <parameter name="DPA_MULTIPLY_BY" value="" />
+ <parameter name="DPA_DIVIDE_BY" value="" />
+ <parameter name="DPA_DIVIDER" value="" />
+ <parameter name="VCO_MULTIPLY_BY" value="" />
+ <parameter name="VCO_DIVIDE_BY" value="" />
+ <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+ <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+ <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+ <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+ <parameter name="USING_FBMIMICBIDIR_PORT" value="OFF" />
+ <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+ <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+ <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 1 CT#PORT_clk9 PORT_UNUSED CT#PORT_clk8 PORT_UNUSED CT#PORT_clk7 PORT_UNUSED CT#PORT_clk6 PORT_UNUSED CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 5 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 10 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 4 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 40000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_FBOUT PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 5 CT#INTENDED_DEVICE_FAMILY {Stratix IV} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 5 CT#CLK3_MULTIPLY_BY 8 CT#USING_FBMIMICBIDIR_PORT OFF CT#PORT_LOCKED PORT_USED</parameter>
+ <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 25.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ3 40.00000000 PT#OUTPUT_FREQ2 125.00000000 PT#OUTPUT_FREQ1 20.00000000 PT#OUTPUT_FREQ0 50.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE3 40.000000 PT#EFF_OUTPUT_FREQ_VALUE2 125.000000 PT#EFF_OUTPUT_FREQ_VALUE1 20.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Stratix IV} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1256297171721465.mif PT#ACTIVECLK_CHECK 0</parameter>
+ <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+ <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+ <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+ <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
+ <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+ <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="25000000" />
+ <parameter name="AUTO_DEVICE_FAMILY" value="Stratix IV" />
+ </module>
+ <module
+ kind="altera_avalon_pio"
+ version="11.1"
+ enabled="1"
+ name="pio_debug_wave">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="32" />
+ </module>
+ <module kind="altera_avalon_pio" version="11.1" enabled="1" name="pio_wdi">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module kind="altera_avalon_timer" version="11.1" enabled="1" name="timer_0">
+ <parameter name="alwaysRun" value="true" />
+ <parameter name="counterSize" value="32" />
+ <parameter name="fixedPeriod" value="true" />
+ <parameter name="period" value="1" />
+ <parameter name="periodUnits" value="MSEC" />
+ <parameter name="resetOutput" value="false" />
+ <parameter name="snapshot" value="false" />
+ <parameter name="systemFrequency" value="50000000" />
+ <parameter name="timeoutPulseOutput" value="false" />
+ <parameter name="timerPreset">SIMPLE_PERIODIC_INTERRUPT</parameter>
+ </module>
+ <module kind="avs_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
+ <parameter name="AUTO_MM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_sens">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="rom_system_info">
+ <parameter name="g_adr_w" value="10" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_system_info">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_pps">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_wdi">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_diag_bg">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_data_buffer_im">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_data_buffer_re">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="ram_diag_data_buffer_im">
+ <parameter name="g_adr_w" value="12" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="ram_diag_data_buffer_re">
+ <parameter name="g_adr_w" value="12" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="ram_diag_bg">
+ <parameter name="g_adr_w" value="12" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="ram_ss_ss_wide">
+ <parameter name="g_adr_w" value="10" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_bsn_monitor">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="jtag_uart_0.avalon_jtag_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x02d0" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="jtag_uart_0.irq">
+ <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="altpll_0.pll_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x02a0" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="cpu_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="onchip_memory2_0.clk1" />
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="jtag_uart_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="altpll_0.inclk_interface" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="pio_debug_wave.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_debug_wave.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x02b0" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_wdi.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_wdi.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x02c0" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="timer_0.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="timer_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0240" />
+ </connection>
+ <connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq">
+ <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="avs_eth_0.mm" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_tse">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_reg">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0200" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_ram">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00010000" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="avs_eth_0.interrupt">
+ <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_unb_sens.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_unb_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0260" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="rom_system_info.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="rom_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="pio_system_info.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_pps.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_pps.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x02d8" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_wdi.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_wdi.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_diag_bg.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_bg.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0280" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_diag_data_buffer_im.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_data_buffer_im.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0080" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_diag_data_buffer_re.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_data_buffer_re.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0100" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="ram_diag_data_buffer_im.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_diag_data_buffer_im.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x4000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="ram_diag_data_buffer_re.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_diag_data_buffer_re.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x8000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="ram_diag_bg.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_diag_bg.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0xc000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="ram_ss_ss_wide.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_ss_ss_wide.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00011000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_bsn_monitor.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0180" />
+ </connection>
+</system>
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl
new file mode 100644
index 0000000000..23df2d360c
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl
@@ -0,0 +1,7 @@
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb_ddr3_transpose_pins_constraints.tcl b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb_ddr3_transpose_pins_constraints.tcl
new file mode 100644
index 0000000000..6f373eb565
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb_ddr3_transpose_pins_constraints.tcl
@@ -0,0 +1,517 @@
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[8] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[8] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[8] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[9] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[9] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[9] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[10] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[10] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[10] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[11] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[11] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[11] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[12] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[12] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[12] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[13] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[13] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[13] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[14] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[14] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[14] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[15] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[15] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[15] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[16] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[16] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[16] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[17] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[17] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[17] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[18] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[18] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[18] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[19] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[19] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[19] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[20] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[20] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[20] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[21] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[21] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[21] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[22] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[22] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[22] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[23] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[23] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[23] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[24] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[24] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[24] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[25] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[25] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[25] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[26] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[26] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[26] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[27] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[27] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[27] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[28] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[28] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[28] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[29] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[29] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[29] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[30] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[30] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[30] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[31] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[31] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[31] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[32] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[32] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[32] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[33] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[33] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[33] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[34] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[34] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[34] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[35] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[35] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[35] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[36] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[36] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[36] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[37] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[37] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[37] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[38] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[38] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[38] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[39] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[39] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[39] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[40] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[40] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[40] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[41] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[41] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[41] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[42] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[42] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[42] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[43] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[43] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[43] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[44] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[44] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[44] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[45] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[45] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[45] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[46] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[46] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[46] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[47] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[47] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[47] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[48] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[48] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[48] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[49] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[49] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[49] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[50] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[50] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[50] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[51] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[51] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[51] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[52] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[52] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[52] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[53] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[53] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[53] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[54] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[54] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[54] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[55] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[55] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[55] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[56] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[56] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[56] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[57] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[57] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[57] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[58] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[58] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[58] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[59] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[59] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[59] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[60] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[60] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[60] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[61] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[61] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[61] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[62] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[62] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[62] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[63] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[63] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[63] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].clk[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_IO[0].clk[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].clk[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_IO[0].clk[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].clk_n[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_IO[0].clk_n[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].clk_n[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_IO[0].clk_n[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[10] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[10] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[11] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[11] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[12] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[12] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[13] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[13] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[14] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[14] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[8] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[8] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[9] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[9] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].ba[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].ba[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].ba[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].ba[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].ba[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].ba[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].cs_n[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].cs_n[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].cs_n[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].cs_n[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].we_n -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].we_n -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].ras_n -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].ras_n -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].cas_n -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].cas_n -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].cke[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].cke[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].cke[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].cke[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].odt[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].odt[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].odt[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].odt[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD 1.5V -to MB_I_OU[0].reset_n -tag __uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].reset_n -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[8] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[9] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[10] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[11] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[12] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[13] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[14] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[15] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[16] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[17] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[18] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[19] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[20] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[21] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[22] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[23] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[24] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[25] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[26] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[27] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[28] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[29] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[30] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[31] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[32] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[33] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[34] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[35] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[36] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[37] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[38] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[39] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[40] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[41] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[42] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[43] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[44] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[45] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[46] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[47] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[48] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[49] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[50] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[51] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[52] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[53] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[54] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[55] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[56] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[57] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[58] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[59] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[60] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[61] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[62] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[63] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_OU[0].dm[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_OU[0].dm[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_OU[0].dm[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_OU[0].dm[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_OU[0].dm[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_OU[0].dm[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_OU[0].dm[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_OU[0].dm[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[8] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[9] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[10] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[11] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[12] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[13] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[14] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[15] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[16] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[17] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[18] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[19] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[20] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[21] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[22] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[23] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[24] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[25] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[26] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[27] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[28] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[29] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[30] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[31] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[32] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[33] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[34] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[35] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[36] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[37] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[38] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[39] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[40] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[41] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[42] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[43] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[44] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[45] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[46] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[47] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[48] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[49] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[50] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[51] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[52] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[53] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[54] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[55] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[56] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[57] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[58] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[59] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[60] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[61] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[62] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[63] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[0] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[1] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[2] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[3] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[4] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[5] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[6] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[7] -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[1]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[2]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[3]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[5]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[6]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|ureset|phy_reset_mem_stable_n" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|ureset|phy_reset_n" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[5]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[5]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[6]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[6]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[7]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[7]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[0]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[1]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[2]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[3]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[4]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[5]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[6]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[7]" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst" -tag __uphy_4g_800_master_p0
+set_instance_assignment -name PLL_ENFORCE_USER_PHASE_SHIFT ON -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|pll1" -tag __uphy_4g_800_master_p0
+set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name UNIPHY_TEMP_VER_CODE 1979019194
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
new file mode 100644
index 0000000000..17435a68a3
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
@@ -0,0 +1,369 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, ddr3_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE ddr3_lib.ddr3_pkg.ALL;
+
+
+ENTITY mmm_unb_ddr3_transpose IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_frame_size_in : NATURAL := 256;
+ g_nof_streams : NATURAL := 4;
+ g_ddr3_seq : t_ddr3_seq := c_ddr3_seq
+ );
+ PORT (
+ xo_clk : IN STD_LOGIC;
+ xo_rst_n : IN STD_LOGIC;
+ xo_rst : IN STD_LOGIC;
+
+ mm_rst : IN STD_LOGIC;
+ mm_clk : OUT STD_LOGIC;
+ mm_locked : OUT STD_LOGIC;
+
+ pout_wdi : OUT STD_LOGIC;
+
+ -- Manual WDI override
+ reg_wdi_mosi : OUT t_mem_mosi;
+ reg_wdi_miso : IN t_mem_miso;
+
+ -- system_info
+ reg_unb_system_info_mosi : OUT t_mem_mosi;
+ reg_unb_system_info_miso : IN t_mem_miso;
+ rom_unb_system_info_mosi : OUT t_mem_mosi;
+ rom_unb_system_info_miso : IN t_mem_miso;
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi : OUT t_mem_mosi;
+ reg_unb_sens_miso : IN t_mem_miso;
+
+ -- PPSH
+ reg_ppsh_mosi : OUT t_mem_mosi;
+ reg_ppsh_miso : IN t_mem_miso;
+
+ -- eth1g
+ eth1g_tse_clk : OUT STD_LOGIC;
+ eth1g_mm_rst : OUT STD_LOGIC;
+ eth1g_tse_mosi : OUT t_mem_mosi;
+ eth1g_tse_miso : IN t_mem_miso;
+ eth1g_reg_mosi : OUT t_mem_mosi;
+ eth1g_reg_miso : IN t_mem_miso;
+ eth1g_reg_interrupt : IN STD_LOGIC;
+ eth1g_ram_mosi : OUT t_mem_mosi;
+ eth1g_ram_miso : IN t_mem_miso;
+
+ -- Block generators
+ reg_diag_bg_mosi : OUT t_mem_mosi;
+ reg_diag_bg_miso : IN t_mem_miso;
+ ram_diag_bg_mosi : OUT t_mem_mosi;
+ ram_diag_bg_miso : IN t_mem_miso;
+
+ -- DDR3 transpose
+ ram_ss_ss_transp_mosi : OUT t_mem_mosi;
+ ram_ss_ss_transp_miso : IN t_mem_miso;
+
+ -- Databuffers
+ ram_diag_data_buf_im_mosi : OUT t_mem_mosi;
+ ram_diag_data_buf_im_miso : IN t_mem_miso;
+ reg_diag_data_buf_im_mosi : OUT t_mem_mosi;
+ reg_diag_data_buf_im_miso : IN t_mem_miso;
+ ram_diag_data_buf_re_mosi : OUT t_mem_mosi;
+ ram_diag_data_buf_re_miso : IN t_mem_miso;
+ reg_diag_data_buf_re_mosi : OUT t_mem_mosi;
+ reg_diag_data_buf_re_miso : IN t_mem_miso;
+
+ reg_bsn_monitor_mosi : OUT t_mem_mosi;
+ reg_bsn_monitor_miso : IN t_mem_miso
+ );
+END mmm_unb_ddr3_transpose;
+
+ARCHITECTURE str OF mmm_unb_ddr3_transpose IS
+
+ CONSTANT c_stimuli_length : POSITIVE := g_ddr3_seq.wr_nof_chunks * g_ddr3_seq.wr_chunksize * g_ddr3_seq.rd_chunksize;
+ CONSTANT c_reg_diag_bg_adr_w : NATURAL := 3;
+ CONSTANT c_ram_diag_bg_adr_w : POSITIVE := ceil_log2(g_nof_streams * c_stimuli_length);
+ CONSTANT c_reg_diag_data_buf_im_adr_w : NATURAL := 5;
+ CONSTANT c_ram_diag_data_buf_im_adr_w : NATURAL := ceil_log2(g_nof_streams * c_stimuli_length);
+ CONSTANT c_reg_diag_data_buf_re_adr_w : NATURAL := 5;
+ CONSTANT c_ram_diag_data_buf_re_adr_w : NATURAL := ceil_log2(g_nof_streams * c_stimuli_length);
+ CONSTANT c_ram_ss_ss_transp_adr_w : NATURAL := ceil_log2(g_frame_size_in * g_ddr3_seq.rd_chunksize);
+
+ CONSTANT c_mm_clk_period : TIME := 100 ps;
+
+ CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN");
+ CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
+
+ SIGNAL i_mm_clk : STD_LOGIC := '1';
+
+ ----------------------------------------------------------------------------
+ -- mm_file component
+ ----------------------------------------------------------------------------
+ COMPONENT mm_file
+ GENERIC(
+ g_file_prefix : STRING;
+ g_mm_clk_period : TIME := c_mm_clk_period;
+ g_update_on_change : BOOLEAN := FALSE;
+ g_mm_rd_latency : NATURAL := 1
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ mm_master_out : OUT t_mem_mosi;
+ mm_master_in : IN t_mem_miso
+ );
+ END COMPONENT;
+
+BEGIN
+
+ mm_clk <= i_mm_clk;
+
+ ----------------------------------------------------------------------------
+ -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ ----------------------------------------------------------------------------
+ gen_mm_file_io : IF g_sim = TRUE GENERATE
+
+ i_mm_clk <= NOT i_mm_clk AFTER c_mm_clk_period/2;
+ mm_locked <= '0', '1' AFTER c_mm_clk_period*5;
+
+ u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ PORT MAP(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+ u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ PORT MAP(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+ u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ PORT MAP(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+ u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ PORT MAP(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ PORT MAP(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ -- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
+ u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ PORT MAP(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ PORT MAP(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+
+ u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ PORT MAP(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+
+ u_mm_file_ram_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_RE")
+ PORT MAP(mm_rst, i_mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+
+ u_mm_file_reg_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_RE")
+ PORT MAP(mm_rst, i_mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+
+ u_mm_file_ram_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_IM")
+ PORT MAP(mm_rst, i_mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+
+ u_mm_file_reg_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_IM")
+ PORT MAP(mm_rst, i_mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+
+ u_mm_file_ram_ss_ss_transp : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+ PORT MAP(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
+
+ u_mm_file_reg_bsn_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+ PORT MAP(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+
+ ----------------------------------------------------------------------------
+ -- Procedure that polls a sim control file that can be used to e.g. get
+ -- the simulation time in ns
+ ----------------------------------------------------------------------------
+ mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+
+ END GENERATE;
+
+ ----------------------------------------------------------------------------
+ -- SOPC for synthesis
+ ----------------------------------------------------------------------------
+ gen_sopc : IF g_sim = FALSE GENERATE
+ u_sopc : ENTITY work.sopc_unb_ddr3_transpose
+ PORT MAP (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk,
+ tse_clk => eth1g_tse_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb_common.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_diag_bg: entry for the register space of the block generator
+ coe_clk_export_from_the_reg_diag_bg => OPEN,
+ coe_reset_export_from_the_reg_diag_bg => OPEN,
+ coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_ram_diag_bg: entry for the ram space of the block generator
+ coe_clk_export_from_the_ram_diag_bg => OPEN,
+ coe_reset_export_from_the_ram_diag_bg => OPEN,
+ coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_diag_data_buf_im: register space for the imaginary databuffer
+ coe_clk_export_from_the_reg_diag_data_buffer_im => OPEN,
+ coe_reset_export_from_the_reg_diag_data_buffer_im => OPEN,
+ coe_address_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.address(c_reg_diag_data_buf_im_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_ram_diag_data_buf_im: ram space for the imaginary databuffer
+ coe_clk_export_from_the_ram_diag_data_buffer_im => OPEN,
+ coe_reset_export_from_the_ram_diag_data_buffer_im => OPEN,
+ coe_address_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.address(c_ram_diag_data_buf_im_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_diag_data_buf_re: register space for the real databuffer
+ coe_clk_export_from_the_reg_diag_data_buffer_re => OPEN,
+ coe_reset_export_from_the_reg_diag_data_buffer_re => OPEN,
+ coe_address_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.address(c_reg_diag_data_buf_re_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_ram_diag_data_buf_re: ram space for the real databuffer
+ coe_clk_export_from_the_ram_diag_data_buffer_re => OPEN,
+ coe_reset_export_from_the_ram_diag_data_buffer_re => OPEN,
+ coe_address_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.address(c_ram_diag_data_buf_re_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_ram_ss_ss_transp: ram space for the subband select unit
+ coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.rd,
+ coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_transp_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wr,
+ coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(1+c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w-1 DOWNTO 0),
+ coe_clk_export_from_the_reg_bsn_monitor => OPEN,
+ coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_bsn_monitor => OPEN,
+ coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ );
+ END GENERATE;
+END str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
new file mode 100644
index 0000000000..7d5e352865
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
@@ -0,0 +1,522 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, eth_lib, diag_lib, dp_lib, ddr3_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE ddr3_lib.ddr3_pkg.ALL;
+
+ENTITY unb1_ddr3_transpose IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_design_name : STRING := "unb1_ddr3_transpose";
+ g_design_note : STRING := "Test Design";
+ --g_technology : NATURAL := c_tech_stratixiv;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
+ g_use_MB_I : NATURAL := 1 -- 1: use MB_I 0: do not use
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ sens_sc : INOUT STD_LOGIC;
+ sens_sd : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_clk : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC;
+ ETH_SGOUT : OUT STD_LOGIC;
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN : IN t_ddr3_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0) := (OTHERS=>c_ddr3_phy_in_rst);
+ MB_I_IO : INOUT t_ddr3_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);
+ MB_I_OU : OUT t_ddr3_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0)
+ );
+END unb1_ddr3_transpose;
+
+
+ARCHITECTURE str OF unb1_ddr3_transpose IS
+
+ -- Firmware version x.y
+ CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 6);
+ -- In simulation we don't need the 1GbE core for MM control, deselect it in c_use_phy based on g_sim
+ CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(g_sim, 0, 1), 0, 0, 0, 1, 0, 0, 1);
+
+ -- Compose the Constants for the DUT
+ CONSTANT c_wr_chunksize : POSITIVE := sel_a_b(g_sim, 64, 64);-- 256);
+ CONSTANT c_wr_nof_chunks : POSITIVE := sel_a_b(g_sim, 1, 1);-- 1);
+ CONSTANT c_rd_chunksize : POSITIVE := sel_a_b(g_sim, 16, 16);-- 16);
+ CONSTANT c_rd_nof_chunks : POSITIVE := sel_a_b(g_sim, 4, 4);-- 16);
+ CONSTANT c_gapsize : NATURAL := sel_a_b(g_sim, 0, 0);-- 0);
+ CONSTANT c_nof_blocks : POSITIVE := sel_a_b(g_sim, 4, 4);-- 16);
+
+ CONSTANT c_ddr3_seq_conf : t_ddr3_seq := (c_wr_chunksize,
+ c_wr_nof_chunks,
+ c_rd_chunksize,
+ c_rd_nof_chunks,
+ c_gapsize,
+ c_nof_blocks);
+
+ CONSTANT c_blocksize : POSITIVE := c_wr_nof_chunks * c_wr_chunksize;
+
+ CONSTANT c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
+ CONSTANT c_mts : NATURAL := 800;--1066; --800
+ CONSTANT c_phy : NATURAL := 1;
+ CONSTANT c_data_w : NATURAL := 8;
+ CONSTANT c_nof_streams : POSITIVE := 4;
+ CONSTANT c_frame_size_in : POSITIVE := c_wr_chunksize;
+ CONSTANT c_frame_size_out : POSITIVE := c_frame_size_in;
+ CONSTANT c_nof_blk_per_sync : POSITIVE := 1600000;
+ CONSTANT c_ena_pre_transpose : BOOLEAN := FALSE;
+
+ -- Custom definitions of constants
+ CONSTANT c_bg_block_len : NATURAL := c_blocksize * c_rd_chunksize;
+ CONSTANT c_db_block_len : NATURAL := c_blocksize * c_rd_chunksize;
+
+ -- Configuration of the block generator:
+ CONSTANT c_bg_buf_dat_w : POSITIVE := c_nof_complex*c_data_w;
+ CONSTANT c_bg_buf_adr_w : POSITIVE := ceil_log2(c_bg_block_len);
+ CONSTANT c_bg_data_file_prefix : STRING := "UNUSED"; -- "../../../src/hex/tb_bg_dat";
+ CONSTANT c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, 128, 1);
+
+ -- Configuration of the databuffers:
+ CONSTANT c_db_data_w : POSITIVE := c_diag_db_max_data_w;
+ CONSTANT c_db_buf_nof_data : POSITIVE := c_db_block_len;
+ CONSTANT c_db_buf_use_sync : BOOLEAN := TRUE;
+ CONSTANT c_db_data_type_re : t_diag_data_type_enum := e_real;
+ CONSTANT c_db_data_type_im : t_diag_data_type_enum := e_imag;
+
+ -- System
+ SIGNAL cs_sim : STD_LOGIC;
+ SIGNAL xo_clk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_locked : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+
+ SIGNAL dp_rst : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC;
+ SIGNAL dp_pps : STD_LOGIC;
+
+
+ -- PIOs
+ SIGNAL pout_wdi : STD_LOGIC;
+
+ -- WDI override
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
+
+ -- PPSH
+ SIGNAL reg_ppsh_mosi : t_mem_mosi;
+ SIGNAL reg_ppsh_miso : t_mem_miso;
+
+ -- UniBoard system info
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
+
+ -- UniBoard I2C sens
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
+
+ -- eth1g
+ SIGNAL eth1g_tse_clk : STD_LOGIC;
+ SIGNAL eth1g_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_miso : t_mem_miso;
+ --SIGNAL eth1g_led : t_tse_led;
+
+ -- Blockgenerator
+ SIGNAL bg_siso_arr : t_dp_siso_arr(c_nof_streams -1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL bg_sosi_arr : t_dp_sosi_arr(c_nof_streams -1 DOWNTO 0);
+
+ SIGNAL reg_diag_bg_mosi : t_mem_mosi;
+ SIGNAL reg_diag_bg_miso : t_mem_miso;
+
+ SIGNAL ram_diag_bg_mosi : t_mem_mosi;
+ SIGNAL ram_diag_bg_miso : t_mem_miso;
+
+ -- Databuffer
+ SIGNAL ram_diag_data_buf_re_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_re_miso : t_mem_miso;
+
+ SIGNAL reg_diag_data_buf_re_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_re_miso : t_mem_miso;
+
+ SIGNAL ram_diag_data_buf_im_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_im_miso : t_mem_miso;
+
+ SIGNAL reg_diag_data_buf_im_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_im_miso : t_mem_miso;
+
+ -- DDR3 Transpose
+ SIGNAL ram_ss_ss_transp_mosi : t_mem_mosi;
+ SIGNAL ram_ss_ss_transp_miso : t_mem_miso;
+
+ -- BNS Monitor
+ SIGNAL reg_bsn_monitor_mosi : t_mem_mosi;
+ SIGNAL reg_bsn_monitor_miso : t_mem_miso;
+ SIGNAL bsn_sosi_arr : t_dp_sosi_arr(1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+
+ SIGNAL out_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL out_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- General control function
+ -----------------------------------------------------------------------------
+ u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux
+ )
+ PORT MAP (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ -- . system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+
+ -----------------------------------------------------------------------------
+ -- MM master
+ -----------------------------------------------------------------------------
+ u_mmm : ENTITY work.mmm_unb_ddr3_transpose
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_frame_size_in => c_frame_size_in,
+ g_nof_streams => c_nof_streams,
+ g_ddr3_seq => c_ddr3_seq_conf
+ )
+ PORT MAP(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- Blockgenerator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+
+ -- DDR3 transpose
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ -- Databuffers
+ ram_diag_data_buf_im_mosi => ram_diag_data_buf_im_mosi,
+ ram_diag_data_buf_im_miso => ram_diag_data_buf_im_miso,
+ reg_diag_data_buf_im_mosi => reg_diag_data_buf_im_mosi,
+ reg_diag_data_buf_im_miso => reg_diag_data_buf_im_miso,
+ ram_diag_data_buf_re_mosi => ram_diag_data_buf_re_mosi,
+ ram_diag_data_buf_re_miso => ram_diag_data_buf_re_miso,
+ reg_diag_data_buf_re_mosi => reg_diag_data_buf_re_mosi,
+ reg_diag_data_buf_re_miso => reg_diag_data_buf_re_miso,
+
+ -- BSN monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso
+ );
+
+ -----------------------------------------------------------------------------
+ -- Node function
+ -----------------------------------------------------------------------------
+ u_bg : ENTITY diag_lib.mms_diag_block_gen
+ GENERIC MAP(
+ g_nof_streams => c_nof_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ PORT MAP(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
+
+ u_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
+ GENERIC MAP (
+ g_nof_streams => 2, -- Check one input and one output stream
+ g_cross_clock_domain => TRUE,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_log_first_bsn => TRUE
+ )
+ PORT MAP (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => (OTHERS=>c_dp_siso_rdy),
+ in_sosi_arr => bsn_sosi_arr
+ );
+
+ bsn_sosi_arr(0) <= bg_sosi_arr(0);
+ bsn_sosi_arr(1) <= out_sosi_arr(0);
+
+ u_ddr3_T: ENTITY ddr3_lib.ddr3_transpose
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_nof_streams => c_nof_streams,
+ g_in_dat_w => c_bg_buf_dat_w/c_nof_complex,
+ g_frame_size_in => c_frame_size_in,
+ g_frame_size_out => c_frame_size_out,
+ g_nof_blk_per_sync => c_nof_blk_per_sync,
+ g_use_complex => TRUE,
+ g_ena_pre_transp => c_ena_pre_transpose,
+ g_phy => c_phy,
+ g_mts => c_mts,
+ g_ddr3_seq => c_ddr3_seq_conf
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_out_arr => bg_siso_arr,
+ snk_in_arr => bg_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr,
+
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ ser_term_ctrl_out => OPEN,
+ par_term_ctrl_out => OPEN,
+
+ ser_term_ctrl_in => OPEN,
+ par_term_ctrl_in => OPEN,
+
+ phy_in => MB_I_in(0),
+ phy_io => MB_I_io(0),
+ phy_ou => MB_I_ou(0)
+ );
+
+ ----------------------------------------------------------------------------
+ -- Sink: data buffer real
+ ----------------------------------------------------------------------------
+ u_data_buf_re : ENTITY diag_lib.mms_diag_data_buffer
+ GENERIC MAP (
+ g_nof_streams => c_nof_streams,
+ g_data_type => c_db_data_type_re,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ PORT MAP (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
+
+ ----------------------------------------------------------------------------
+ -- Sink: data buffer imag
+ ----------------------------------------------------------------------------
+ u_data_buf_im : ENTITY diag_lib.mms_diag_data_buffer
+ GENERIC MAP (
+ g_nof_streams => c_nof_streams,
+ g_data_type => c_db_data_type_im,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ PORT MAP (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
+
+END str;
+
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/tc_unb_ddr3_transpose.py b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/tc_unb_ddr3_transpose.py
new file mode 100644
index 0000000000..fc07e30af1
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/tc_unb_ddr3_transpose.py
@@ -0,0 +1,308 @@
+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (C) 2012
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+"""Test case for the unb_ddr3_transpose design.
+
+ Description:
+
+
+ Usage in simulation:
+
+ > python tc_unb_ddr3_transpose.py --unb 0 --bn 3 --sim
+
+"""
+
+###############################################################################
+# System imports
+import test_case
+import node_io
+import unb_apertif as apr
+import pi_diag_block_gen
+import pi_diag_data_buffer
+import pi_ss_ss_wide
+import pi_bsn_monitor
+import dsp_test
+
+import sys, os
+import subprocess
+import time
+import pylab as pl
+import numpy as np
+import scipy as sp
+import random
+from tools import *
+from common import *
+import mem_init_file
+
+###############################################################################
+
+# Create a test case object
+tc = test_case.Testcase('TB - ', '')
+
+# Constants/Generics that are shared between VHDL and Python
+# Name Value Default Description
+# START_VHDL_GENERICS
+if tc.sim==True:
+ g_wr_chunksize = 64
+ g_wr_nof_chunks = 1
+ g_rd_chunksize = 16
+ g_rd_nof_chunks = 4
+ g_gapsize = 0
+ g_nof_blocks = 4
+else:
+ g_wr_chunksize = 64 # 256
+ g_wr_nof_chunks = 1 # 1
+ g_rd_chunksize = 16 # 16
+ g_rd_nof_chunks = 4 # 16
+ g_gapsize = 0 # 0
+ g_nof_blocks = 4 # 16
+
+# END_VHDL_GENERICS
+
+# Overwrite generics with argumented generics from autoscript or command line.
+if tc.generics != None:
+ g_wr_chunksize = tc.generics['g_wr_chunksize']
+ g_wr_nof_chunks = tc.generics['g_wr_nof_chunks']
+ g_rd_chunksize = tc.generics['g_rd_chunksize']
+ g_rd_nof_chunks = tc.generics['g_rd_nof_chunks']
+ g_gapsize = tc.generics['g_gapsize']
+ g_nof_blocks = tc.generics['g_nof_blocks']
+
+c_blocksize = (g_wr_chunksize + g_gapsize) * g_wr_nof_chunks
+c_pagesize = c_blocksize * g_nof_blocks
+c_bg_nof_streams = 4
+c_bg_ram_size = g_wr_chunksize * g_wr_nof_chunks * g_rd_chunksize
+c_in_dat_w = 8
+c_blocks_per_sync = 1600000
+c_db_nof_streams = c_bg_nof_streams
+c_db_ram_size = c_bg_ram_size #g_rd_chunksize * g_rd_nof_chunks * g_nof_blocks
+c_frame_size_in = g_wr_chunksize
+c_nof_int_streams = 1
+c_ena_pre_transpose = False
+
+tc.append_log(3, '>>>')
+tc.append_log(1, '>>> Title : Test Case for unb_ddr3_transpose' )
+tc.append_log(3, '>>>')
+tc.append_log(3, '')
+tc.set_result('PASSED')
+
+# Create access object for nodes
+io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+# Create block generator instance
+bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, c_bg_nof_streams, c_bg_ram_size)
+
+# Create databuffer instances
+db_re = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName = 'RE', nofStreams=c_db_nof_streams, ramSizePerStream=c_db_ram_size)
+db_im = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName = 'IM', nofStreams=c_db_nof_streams, ramSizePerStream=c_db_ram_size)
+
+# Create subandselect instance for pre-transpose.
+ss = pi_ss_ss_wide.PiSsSsWide (tc, io, c_frame_size_in*g_rd_chunksize, c_nof_int_streams)
+
+# BSN monitor
+bsn = pi_bsn_monitor.PiBsnMonitor(tc, io, instanceName='', nofStreams=2)
+
+# Create dsp_test instance for helpful methods
+dsp_test_bg = dsp_test.DspTest(inDatW=c_in_dat_w)
+
+# Function for generating stimuli and generating hex files.
+def gen_bg_hex_files(c_nof_values = 1024, c_nof_streams = 4):
+ data = []
+ for i in range(c_nof_streams):
+ stream_re = []
+ stream_im = []
+ for j in range(c_nof_values):
+ stream_re.append(j)
+ stream_im.append(i)
+ data_concat = dsp_test_bg.concatenate_two_lists(stream_re, stream_im, c_in_dat_w)
+ data.append(data_concat)
+ filename = "../../src/hex/tb_bg_dat_" + str(i) + ".hex"
+ mem_init_file.list_to_hex(list_in=data_concat, filename=filename, mem_width=c_nof_complex*c_in_dat_w, mem_depth=2**(ceil_log2(c_bg_ram_size)))
+ return data
+
+if __name__ == "__main__":
+ ###############################################################################
+ #
+ # Create setting for the pre-transpose (subbandselect)
+ #
+ ###############################################################################
+ bsn.read_bsn_monitor(0)
+ bsn.read_bsn_monitor(1)
+
+ print "nof_words"
+ a=db_re.read_nof_words()
+ print a
+ ss_list = []
+ for i in range(c_frame_size_in):
+ for j in range(g_rd_chunksize):
+ ss_list.append(i + j*c_frame_size_in)
+
+ ss.write_selects(ss_list)
+
+ ###############################################################################
+ #
+ # Create stimuli for the BG
+ #
+ ###############################################################################
+ # Prepare x stimuli for block generator
+ bg_data = gen_bg_hex_files(c_bg_ram_size, c_bg_nof_streams)
+
+ ################################################################################
+ ##
+ ## Write data and settings to block generator
+ ##
+ ################################################################################
+ # Write setting for the block generator:
+ bg.write_block_gen_settings(samplesPerPacket=c_frame_size_in, blocksPerSync=c_blocks_per_sync, gapSize=0, memLowAddr=0, memHighAddr=c_bg_ram_size-1, BSNInit=10)
+
+ # Write the stimuli to the block generator and enable the block generator
+ for i in range(c_bg_nof_streams):
+ bg.write_waveform_ram(data=bg_data[i], channelNr= i)
+
+ # Concatenate all channels
+ t=2
+ while len(bg_data) > 1:
+ concat_data = []
+ for i in range(len(bg_data)/2):
+ concat_data.append(dsp_test_bg.concatenate_two_lists(bg_data[2*i], bg_data[2*i+1], c_in_dat_w*t))
+ bg_data = concat_data
+ t=t*2
+
+ bg_data = flatten(bg_data)
+
+# for i in range(len(bg_data)):
+# print ">%X<" % bg_data[i]
+
+ ###############################################################################
+ #
+ # Calculate reference data
+ #
+ ###############################################################################
+ # Subband Select pre-transpose
+ if c_ena_pre_transpose:
+ bg_data = ss.subband_select(bg_data, ss_list)
+
+ ref_data_total = []
+ # Check how many data there is and how many pages will be used:
+ for t in range(len(bg_data)/c_pagesize):
+ bg_data_single_page = bg_data[t*c_pagesize:(t+1)*c_pagesize]
+ # Write to memory
+ mem_page = [0] * c_pagesize
+ for i in range(g_nof_blocks):
+ for j in range(g_wr_nof_chunks):
+ for k in range(g_wr_chunksize):
+ mem_page[i*c_blocksize*g_wr_nof_chunks + j*c_blocksize + k] = bg_data_single_page[i*g_wr_chunksize*g_wr_nof_chunks + j*g_wr_chunksize + k]
+
+ # Read from memory
+ ref_data = [0] * g_nof_blocks * g_rd_nof_chunks * g_rd_chunksize
+ chunk_cnt = 0
+ chunk_offset = 0
+ for i in range(g_nof_blocks):
+ for j in range(g_rd_nof_chunks):
+ if chunk_cnt == g_nof_blocks:
+ chunk_cnt = 0
+ chunk_offset = chunk_offset + 1
+ for k in range(g_rd_chunksize):
+ #ref_data[chunk_cnt*(g_rd_chunksize*g_rd_nof_chunks)+ chunk_offset*g_rd_chunksize + k] = mem_page[chunk_cnt*(g_rd_chunksize*g_rd_nof_chunks+g_gapsize)+ chunk_offset*g_rd_chunksize + k]
+ ref_data[i*(g_rd_chunksize*g_rd_nof_chunks)+j*g_rd_chunksize + k] = mem_page[chunk_cnt*(g_rd_chunksize*g_rd_nof_chunks+g_gapsize)+ chunk_offset*g_rd_chunksize + k]
+ chunk_cnt = chunk_cnt + 1
+ ref_data_total.append(ref_data)
+
+ ref_data_total=flatten(ref_data_total)
+
+ # Split the data again in individual channels
+ ref_data_split = []
+ ref_data_split.append(ref_data_total)
+ t = c_bg_nof_streams
+ while len(ref_data_split) < c_bg_nof_streams:
+ ref_data_temp = []
+ for i in range(len(ref_data_split)):
+ [data_a, data_b] = dsp_test_bg.split_in_two_lists(ref_data_split[i], c_in_dat_w*t)
+ ref_data_temp.append(data_a)
+ ref_data_temp.append(data_b)
+ ref_data_split = ref_data_temp
+ t = t/2
+
+ ref_data_re = []
+ ref_data_im = []
+ # Split the data in real and imaginary
+ for i in range(c_bg_nof_streams):
+ [data_re, data_im] = dsp_test_bg.split_in_two_lists(ref_data_split[i], c_in_dat_w)
+ ref_data_re.append(data_re)
+ ref_data_im.append(data_im)
+
+# print "real + imag"
+# for i in range(len(ref_data_re)):
+# for j in range(len(ref_data_re[i])):
+# print "concat: >%X< real: >%X< imag: >%X< " % (ref_data_split[i][j], ref_data_re[i][j], ref_data_im[i][j])
+# print
+#
+
+ # Wait until the DDR3 model is initialized.
+ if tc.sim==True:
+ do_until_gt(io.simIO.getSimTime, ms_retry=1000, val=110000, s_timeout=13600) # 110000
+
+ # Enable the blockgenerator
+ bg.write_enable()
+
+ # Poll the databuffer to check if the response is there.
+ # Retry after 3 seconds so we don't issue too many MM reads in case of simulation.
+ # time.sleep(5)
+ do_until_ge(db_re.read_nof_words, ms_retry=3000, val=c_db_ram_size, s_timeout=3600)
+
+ ###############################################################################
+ #
+ # Read transposed data from data buffer
+ #
+ ###############################################################################
+ db_out_re = []
+ db_out_im = []
+ for i in range(c_bg_nof_streams):
+ db_out_re.append(flatten(db_re.read_data_buffer(streamNr=i, n=c_db_ram_size, radix='uns', width=c_in_dat_w, nofColumns=8)))
+ db_out_im.append(flatten(db_im.read_data_buffer(streamNr=i, n=c_db_ram_size, radix='uns', width=c_in_dat_w, nofColumns=8)))
+
+ bsn.read_bsn_monitor(0)
+ bsn.read_bsn_monitor(1)
+
+ ###############################################################################
+ #
+ # Verify output data
+ #
+ ###############################################################################
+ for i in range(c_bg_nof_streams):
+ for j in range(c_db_ram_size):
+ if db_out_re[i][j] != ref_data_re[i][j]:
+ tc.append_log(2, 'Error in real output data. Expected data: %d Data read: %d Iteration nr: %d %d' % (ref_data_re[i][j], db_out_re[i][j], i, j))
+ tc.set_result('FAILED')
+ if db_out_im[i][j] != ref_data_im[i][j]:
+ tc.append_log(2, 'Error in imag output data. Expected data: %d Data read: %d Iteration nr: %d %d' % (ref_data_im[i][j], db_out_im[i][j], i, j))
+ tc.set_result('FAILED')
+
+ ###############################################################################
+ # End
+ tc.set_section_id('')
+ tc.append_log(3, '')
+ tc.append_log(3, '>>>')
+ tc.append_log(0, '>>> Test bench result: %s' % tc.get_result())
+ tc.append_log(3, '>>>')
+
+ sys.exit(tc.get_result())
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/unb_ddr3_transpose.py b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/unb_ddr3_transpose.py
new file mode 100644
index 0000000000..45dfba60ef
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/unb_ddr3_transpose.py
@@ -0,0 +1,46 @@
+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (C) 2013
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+"""
+On execution, this script will start ModelSim, compile and run DESIGN_NAME and
+run COMMANDS against the running simulation. If --hold is not passed, the running
+simulation will be killed after completion.
+"""
+import sys, os
+sys.path.append(os.environ['UNB']+'/Firmware/sim/python')
+from auto_sim import *
+
+LIBRARY_NAME = 'unb_ddr3_transpose'
+TB_NAME = 'tb_unb_ddr3_transpose'
+TARGET_NODES = ' --unb 0 --bn 3 '
+COMMANDS = ['$UPE/peripherals/util_system_info.py' +TARGET_NODES+ '-n 2',
+ '$UPE/peripherals/util_system_info.py' +TARGET_NODES+ '-n 4',
+ '$UPE/peripherals/util_unb_sens.py' +TARGET_NODES+ '-n 0'
+ ]
+
+# Give sim some time until the sensors have been read
+INIT_DELAY_NS = 5000
+
+GENERICS = {}
+OTHER = ''
+
+# Run the sim and return its result using sys.exit([return_value])
+sys.exit(auto_sim(os.environ['UNB'], LIBRARY_NAME, TB_NAME, COMMANDS, INIT_DELAY_NS, GENERICS, OTHER))
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
new file mode 100644
index 0000000000..fedabeda98
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
@@ -0,0 +1,249 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for unb_ddrs_transpose.
+-- The DUT can be targeted at unb 0, bn3 with the same Python scripts
+-- that are used on hardware.
+
+
+LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, ddr3_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE ddr3_lib.ddr3_pkg.ALL;
+
+ENTITY tb_unb1_ddr3_transpose IS
+END tb_unb1_ddr3_transpose;
+
+ARCHITECTURE tb OF tb_unb1_ddr3_transpose IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 7; -- Back node 3
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w ) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
+
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 0);
+
+ CONSTANT c_cable_delay : TIME := 12 ns;
+ CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
+ CONSTANT c_clk_period : TIME := 5 ns;
+ CONSTANT c_pps_period : NATURAL := 1000;
+
+ CONSTANT c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
+
+ -- DUT
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC;
+ SIGNAL eth_rxp : STD_LOGIC;
+
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version;
+ SIGNAL ID : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id;
+ SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+
+ -- Signals to interface with the DDR3 memory model.
+ SIGNAL phy_in : t_ddr3_phy_in_arr(0 DOWNTO 0);
+ SIGNAL phy_io : t_ddr3_phy_io_arr(0 DOWNTO 0);
+ SIGNAL phy_ou : t_ddr3_phy_ou_arr(0 DOWNTO 0);
+
+ SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL we_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+ -- Model I2C sensor slaves as on the UniBoard
+ CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
+ CONSTANT c_fpga_temp : INTEGER := 60;
+ CONSTANT c_eth_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0101001"; -- MAX1618 address MID LOW
+ CONSTANT c_eth_temp : INTEGER := 40;
+ CONSTANT c_hot_swap_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1000100"; -- LTC4260 address L L L
+ CONSTANT c_hot_swap_R_sense : REAL := 0.01; -- = 10 mOhm on UniBoard
+
+ CONSTANT c_uniboard_current : REAL := 5.0; -- = assume 5.0 A on UniBoard
+ CONSTANT c_uniboard_supply : REAL := 48.0; -- = assume 48.0 V on UniBoard
+ CONSTANT c_uniboard_adin : REAL := -1.0; -- = NC on UniBoard
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+
+ ------------------------------------------------------------------------------
+ -- 1GbE Loopback model
+ ------------------------------------------------------------------------------
+ eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_unb1_ddr3_transpose : ENTITY work.unb1_ddr3_transpose
+ GENERIC MAP (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ MB_I_in => phy_in,
+ MB_I_io => phy_io,
+ MB_I_ou => phy_ou
+
+ );
+
+ ------------------------------------------------------------------------------
+ -- UniBoard sensors
+ ------------------------------------------------------------------------------
+ -- I2C slaves that are available for each FPGA
+ u_fpga_temp : ENTITY i2c_lib.dev_max1618
+ GENERIC MAP (
+ g_address => c_fpga_temp_address
+ )
+ PORT MAP (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
+
+ -- I2C slaves that are available only via FPGA back node 3
+ u_eth_temp : ENTITY i2c_lib.dev_max1618
+ GENERIC MAP (
+ g_address => c_eth_temp_address
+ )
+ PORT MAP (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
+
+ u_power : ENTITY i2c_lib.dev_ltc4260
+ GENERIC MAP (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ PORT MAP (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
+
+ -- DDR3 Model
+ u_4gb_800_ddr3_model : COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
+ GENERIC MAP (
+ MEM_IF_ADDR_WIDTH => 15,
+ MEM_IF_ROW_ADDR_WIDTH => 15,
+ MEM_IF_COL_ADDR_WIDTH => 10,
+ MEM_IF_CS_PER_RANK => 1,
+ MEM_IF_CONTROL_WIDTH => 1,
+ MEM_IF_DQS_WIDTH => 8,
+ MEM_IF_CS_WIDTH => 2,
+ MEM_IF_BANKADDR_WIDTH => 3,
+ MEM_IF_DQ_WIDTH => 64,
+ MEM_IF_CK_WIDTH => 2,
+ MEM_IF_CLK_EN_WIDTH => 2,
+ DEVICE_WIDTH => 1,
+ MEM_TRCD => 6,
+ MEM_TRTP => 3,
+ MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
+ MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
+ MEM_IF_ODT_WIDTH => 2,
+ MEM_MIRROR_ADDRESSING_DEC => 0,
+ MEM_REGDIMM_ENABLED => false,
+ DEVICE_DEPTH => 1,
+ MEM_GUARANTEED_WRITE_INIT => false,
+ MEM_VERBOSE => true,
+ MEM_INIT_EN => false,
+ MEM_INIT_FILE => "",
+ DAT_DATA_WIDTH => 32
+ )
+ PORT MAP (
+ mem_a => phy_ou(0).a(c_ddr.a_w-1 DOWNTO 0),
+ mem_ba => phy_ou(0).ba,
+ mem_ck => phy_io(0).clk,
+ mem_ck_n => phy_io(0).clk_n,
+ mem_cke => phy_ou(0).cke(c_ddr.cs_w-1 DOWNTO 0),
+ mem_cs_n => phy_ou(0).cs_n(c_ddr.cs_w-1 DOWNTO 0),
+ mem_dm => phy_ou(0).dm,
+ mem_ras_n => ras_n,
+ mem_cas_n => cas_n,
+ mem_we_n => we_n,
+ mem_reset_n => phy_ou(0).reset_n,
+ mem_dq => phy_io(0).dq,
+ mem_dqs => phy_io(0).dqs,
+ mem_dqs_n => phy_io(0).dqs_n,
+ mem_odt => phy_ou(0).odt
+ );
+
+ ras_n(0) <= phy_ou(0).ras_n;
+ cas_n(0) <= phy_ou(0).cas_n;
+ we_n(0) <= phy_ou(0).we_n;
+
+
+
+END tb;
--
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