added TB and verified ring_lane_info

libraries/base/ring/hdllib.cfg

-hdl_lib_name = lofar2_ring
-hdl_library_clause_name = lofar2_ring_lib
-hdl_lib_uses_synth = common dp technology mm dp diag tr_10GbE
+hdl_lib_name = ring
+hdl_library_clause_name = ring_lib
+hdl_lib_uses_synth = common dp technology mm dp diag
 hdl_lib_uses_sim = 
 hdl_lib_technology = 
 
 synth_files = 
-
+    src/vhdl/ring_pkg.vhd
+    src/vhdl/ring_lane_info_reg.vhd
+    src/vhdl/ring_lane_info.vhd
 test_bench_files =
+    tb/vhdl/tb_ring_lane_info.vhd
 
 regression_test_vhdl = 
+    tb/vhdl/tb_ring_lane_info.vhd
 
 [modelsim_project_file]
 

libraries/base/ring/src/vhdl/ring_lane_info.vhd

@@ -25,7 +25,7 @@
 -- Purpose:
 -- . Ring lane info register
 -- Description:
---
+-- See ring_pkg.vhd
 -- Remark:
 -- .
 -------------------------------------------------------------------------------
@@ -35,6 +35,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_field_pkg.ALL;
+USE work.ring_pkg.ALL;
 
 ENTITY ring_lane_info IS
   PORT (
@@ -80,6 +81,6 @@ BEGIN
   );
 
   
-  lane_info_ro.lane_direction     <= lane_direction;
+  lane_info_ro.lane_direction <= lane_direction;
 
 END str;

libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd

@@ -20,12 +20,12 @@
 
 -------------------------------------------------------------------------------
 --
--- Author: R. Donker
+-- Author: R. van der Walle
 
 -- Purpose:
 -- . Ring lane info register
 -- Description:
---
+-- See ring_pkg.vhd
 -- Remark:
 -- .
 -------------------------------------------------------------------------------
@@ -56,7 +56,7 @@ ENTITY ring_lane_info_reg IS
 END ring_lane_info_reg;
 
 
-ARCHITECTURE str OF lane_info_reg IS
+ARCHITECTURE str OF ring_lane_info_reg IS
 
   SIGNAL mm_fields_in  : STD_LOGIC_VECTOR(field_slv_in_len(c_lane_info_field_arr)-1 DOWNTO 0);
   SIGNAL mm_fields_out : STD_LOGIC_VECTOR(field_slv_out_len(c_lane_info_field_arr)-1 DOWNTO 0);
@@ -104,7 +104,7 @@ BEGIN
 
   -- get "RW" fields from mm_fields
   lane_info_wr.transport_nof_hops <= mm_fields_out(field_hi(c_lane_info_field_arr, "transport_nof_hops") DOWNTO field_lo(c_lane_info_field_arr, "transport_nof_hops"));
-  lane_info_wr.tx_select          <= mm_fields_out(field_hi(c_lane_info_field_arr, "tx_select") DOWNTO field_lo(c_lane_info_field_arr, "tx_select"));
-  lane_info_wr.rx_select          <= mm_fields_out(field_hi(c_lane_info_field_arr, "rx_select") DOWNTO field_lo(c_lane_info_field_arr, "rx_select"));
+  lane_info_wr.tx_select          <= sl(mm_fields_out(field_hi(c_lane_info_field_arr, "tx_select") DOWNTO field_lo(c_lane_info_field_arr, "tx_select")));
+  lane_info_wr.rx_select          <= sl(mm_fields_out(field_hi(c_lane_info_field_arr, "rx_select") DOWNTO field_lo(c_lane_info_field_arr, "rx_select")));
 
 END str;

libraries/base/ring/src/vhdl/ring_pkg.vhd

@@ -32,7 +32,7 @@ USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_field_pkg.ALL;
 
-PACKAGE sdp_pkg is
+PACKAGE ring_pkg is
 -- lane info, see https://support.astron.nl/confluence/x/jyu7Ag
 -- +====================+========+==============================================================================+===========================+
 -- |       Field        | Access |                                   Description                                |          Remark           |
@@ -78,10 +78,10 @@ PACKAGE sdp_pkg is
         (field_name_pad("tx_select"),          "RW",  1, field_default(0)),
         (field_name_pad("rx_select"),          "RW",  1, field_default(0)) );
 
- END PACKAGE sdp_pkg;
+ END PACKAGE ring_pkg;
 
-PACKAGE BODY sdp_pkg IS
+PACKAGE BODY ring_pkg IS
 
   
-END sdp_pkg;
+END ring_pkg;
 

libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+
+-- Purpose:
+-- . test bench for ring_lane_info.vhd (and ring_lane_info_reg.vhd)
+-- Description:
+--
+-- Remark:
+-- .
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL; 
+USE common_lib.tb_common_mem_pkg.ALL; 
+USE work.ring_pkg.ALL;
+
+
+ENTITY tb_ring_lane_info IS
+END tb_ring_lane_info;
+
+ARCHITECTURE tb OF tb_ring_lane_info IS
+  CONSTANT c_dp_clk_period        : TIME := 5 ns;     -- 200 MHz
+  CONSTANT c_mm_clk_period        : TIME := 20 ns;    -- 50 MHz
+
+  CONSTANT c_cross_clock_domain_latency : NATURAL := 20;
+
+  -- used mm_adresses on mm bus
+  CONSTANT c_mm_addr_rx_select               : NATURAL := 0; 
+  CONSTANT c_mm_addr_tx_select               : NATURAL := 1; 
+  CONSTANT c_mm_addr_lane_direction          : NATURAL := 2; 
+  CONSTANT c_mm_addr_transport_nof_hops      : NATURAL := 3; 
+  
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL tb_mm_reg_end       : STD_LOGIC := '0';
+
+  SIGNAL dp_clk              : STD_LOGIC := '1';   -- digital data path clock = 200 MHz (deser factor 4);
+  SIGNAL dp_rst              : STD_LOGIC;
+
+  SIGNAL mm_clk              : STD_LOGIC := '1';   -- MM control clock = 50 MHz
+  SIGNAL mm_rst              : STD_LOGIC;
+  
+  SIGNAL reg_mosi            : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_miso            : t_mem_miso;
+
+  -- signals used to change settings of ring_lane_info 
+  SIGNAL lane_direction     : STD_LOGIC := '0'; 
+
+  SIGNAL lane_info  : t_lane_info; 
+
+  -- signals used for response of mm bus
+  SIGNAL mm_natural_response : NATURAL;
+BEGIN
+  dp_rst <= '1', '0' AFTER c_dp_clk_period*7;
+  dp_clk <= (NOT dp_clk) OR tb_end AFTER c_dp_clk_period/2;
+  
+  mm_rst <= '1', '0' AFTER c_mm_clk_period*7;
+  mm_clk <= (NOT mm_clk) OR tb_end AFTER c_mm_clk_period/2;
+
+  p_mm_reg_stimuli : PROCESS
+  BEGIN
+    reg_mosi <= c_mem_mosi_rst;
+
+    -- initialyze
+    proc_common_wait_until_low(mm_clk, mm_rst);
+    proc_common_wait_some_cycles(mm_clk, 100);
+
+    -- default all register hold value 0, try to write 1 in all registers
+    proc_mem_mm_bus_wr(c_mm_addr_transport_nof_hops     ,11 ,mm_clk, reg_miso, reg_mosi); 
+    proc_mem_mm_bus_wr(c_mm_addr_lane_direction         ,1  ,mm_clk, reg_miso, reg_mosi); -- RO
+    proc_mem_mm_bus_wr(c_mm_addr_tx_select              ,1  ,mm_clk, reg_miso, reg_mosi);
+    proc_mem_mm_bus_wr(c_mm_addr_rx_select              ,1  ,mm_clk, reg_miso, reg_mosi);
+    proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency);
+
+
+    proc_mem_mm_bus_rd(c_mm_addr_transport_nof_hops, mm_clk, reg_mosi);  proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
+    mm_natural_response <= TO_UINT(reg_miso.rddata);  proc_common_wait_some_cycles(mm_clk, 1);
+    ASSERT mm_natural_response = 11 REPORT "wrong c_mm_addr_transport_nof_hops" SEVERITY ERROR;
+
+    proc_mem_mm_bus_rd(c_mm_addr_lane_direction, mm_clk, reg_mosi);  proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
+    mm_natural_response <= TO_UINT(reg_miso.rddata);  proc_common_wait_some_cycles(mm_clk, 1);
+    ASSERT mm_natural_response /= 1 REPORT "wrong lane_direction (not read only)" SEVERITY ERROR;
+
+    proc_mem_mm_bus_rd(c_mm_addr_tx_select, mm_clk, reg_mosi);  proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
+    mm_natural_response <= TO_UINT(reg_miso.rddata);  proc_common_wait_some_cycles(mm_clk, 1);
+    ASSERT mm_natural_response = 1 REPORT "wrong tx_select" SEVERITY ERROR;
+
+    proc_mem_mm_bus_rd(c_mm_addr_rx_select, mm_clk, reg_mosi);  proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
+    mm_natural_response <= TO_UINT(reg_miso.rddata);  proc_common_wait_some_cycles(mm_clk, 1);
+    ASSERT mm_natural_response = 1 REPORT "wrong rx_select" SEVERITY ERROR;
+
+    proc_common_wait_some_cycles(mm_clk, 100);
+    tb_mm_reg_end <= '1';
+    WAIT;
+
+  END PROCESS;
+
+  -- check if values in lane_info match with expected values
+  p_lane_info_stimuli : PROCESS
+  BEGIN
+    proc_common_wait_until_high(mm_clk, tb_mm_reg_end); -- wait for p_mm_reg_stimuli done
+
+    ASSERT TO_UINT(lane_info.transport_nof_hops) =  11 REPORT "wrong lane_info.transport_nof_hops value"  SEVERITY ERROR;
+    ASSERT lane_info.lane_direction              = '0' REPORT "wrong lane_info.lane_direction value"      SEVERITY ERROR;
+    ASSERT lane_info.tx_select                   = '1' REPORT "wrong lane_info.tx_select value"           SEVERITY ERROR;
+    ASSERT lane_info.rx_select                   = '1' REPORT "wrong lane_info.rx_select value"           SEVERITY ERROR;
+
+    proc_common_wait_some_cycles(mm_clk, 100);
+    tb_end <= '1';
+    WAIT;
+  END PROCESS;
+
+
+  -- SDP info
+  u_dut: ENTITY work.ring_lane_info
+    PORT MAP (
+      mm_clk    => mm_clk,
+      mm_rst    => mm_rst,
+
+      dp_clk    => dp_clk,
+      dp_rst    => dp_rst,
+
+      reg_mosi  => reg_mosi,
+      reg_miso  => reg_miso,
+
+      lane_direction => lane_direction,
+
+      lane_info => lane_info
+    );
+
+END tb;