Initial commit

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd

@@ -51,7 +51,8 @@ ENTITY ddrctrl IS
     g_technology      : NATURAL                                             := c_tech_select_default;
     g_nof_streams     : NATURAL                                             := 12;                                            -- number of input streams
     g_data_w          : NATURAL                                             := 14;                                            -- data with of input data vectors
-    g_stop_percentage : NATURAL                                             := 50
+    g_stop_percentage : NATURAL                                             := 50;
+    g_block_size      : NATURAL                                             := 1024
   );
   PORT (
     clk               : IN  STD_LOGIC                                       := '0';
@@ -213,7 +214,8 @@ BEGIN
     g_sim_model               => g_sim_model,
     g_in_data_w               => c_io_ddr_data_w,
     g_nof_streams             => g_nof_streams,
-    g_data_w                  => g_data_w
+    g_data_w                  => g_data_w,
+    g_block_size              => g_block_size
   )
   PORT MAP(
     clk                       => clk,
@@ -236,7 +238,8 @@ BEGIN
     g_out_data_w              => g_data_w,
     g_wr_data_w               => c_io_ddr_data_w,
     g_rd_fifo_depth           => c_rd_fifo_depth,
-    g_rd_data_w               => c_io_ddr_data_w
+    g_rd_data_w               => c_io_ddr_data_w,
+    g_block_size              => g_block_size
   )
   PORT MAP(
     clk                       => clk,

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd

@@ -44,7 +44,8 @@ ENTITY ddrctrl_controller IS
     g_out_data_w              : NATURAL;
     g_wr_data_w               : NATURAL;
     g_rd_fifo_depth           : NATURAL;
-    g_rd_data_w               : NATURAL
+    g_rd_data_w               : NATURAL;
+    g_block_size              : NATURAL
   );
   PORT (
     clk                       : IN  STD_LOGIC;
@@ -255,7 +256,7 @@ BEGIN
         END IF;
       END LOOP;
 
-      v.outp_bsn := TO_UVEC(TO_UINT(inp_bsn)-((inp_bsn_adr+(c_max_adr-TO_UINT(q_reg.stop_adr)))*g_wr_data_w+v.outp_ds-inp_ds)/c_rd_data_w, c_dp_stream_bsn_w); -- WRONG, wil be fixed after L2SDP-705, 706, 707 and 708
+      v.outp_bsn := TO_UVEC(TO_UINT(inp_bsn), c_dp_stream_bsn_w); -- WRONG, wil be fixed after L2SDP-705, 706, 707 and 708
 
 
       IF rst = '1' THEN

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd

@@ -74,9 +74,12 @@ ARCHITECTURE str OF ddrctrl_input IS
   SIGNAL    data         : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0);
   SIGNAL    sosi         : t_dp_sosi  := c_dp_sosi_init;
   SIGNAL    a_of         : NATURAL    := 0;
-  SIGNAL    bsn          : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+  SIGNAL    bsn_p_rp     : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+  SIGNAL    bsn_rp_ac    : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
   SIGNAL    adr          : NATURAL    := 0;
   SIGNAL    bsn_wr       : STD_LOGIC  := '0';
+  SIGNAL    bsn_ds       : NATURAL    := 0;
+  SIGNAL    valid        : STD_LOGIC  := '0';
 
 BEGIN
 
@@ -91,7 +94,8 @@ BEGIN
   PORT MAP(
     in_sosi_arr       => in_sosi_arr,                                   -- input data
     out_data          => data,                                          -- output data
-    out_bsn           => bsn                                            -- output bsn
+    out_bsn           => bsn_p_rp,                                      -- output bsn
+    out_valid         => valid
   );
 
   -- resizes the input data vector so that the output data vector can be stored into the ddr memory
@@ -104,13 +108,14 @@ BEGIN
     clk               => clk,
     rst               => rst,
     in_data           => data,                                          -- input data
-    in_bsn            => bsn,
+    in_bsn            => bsn_p_rp,
     in_stop           => in_stop,
     in_adr            => adr,
+    in_valid          => valid,
     out_of            => a_of,                                          -- amount of internal overflow
     out_sosi          => sosi,                                          -- output data
-    out_bsn_ds        => out_bsn_ds,                                    -- amount of bits between adr [0] and sosi_arr[0][0] where bsn is assigned to
-    out_bsn           => out_bsn,
+    out_bsn_ds        => bsn_ds,                                        -- amount of bits between adr [0] and sosi_arr[0][0] where bsn is assigned to
+    out_bsn           => bsn_rp_ac,
     out_bsn_wr        => bsn_wr
   );
 
@@ -126,10 +131,14 @@ BEGIN
     in_sosi           => sosi,                                          -- input data
     in_of             => a_of,
     in_bsn_wr         => bsn_wr,
+    in_bsn_ds         => bsn_ds,
+    in_bsn            => bsn_rp_ac,
     out_sosi          => out_sosi,                                      -- output data
     out_of            => out_of,
     out_adr           => adr,
-    out_bsn_adr       => out_bsn_adr
+    out_bsn_adr       => out_bsn_adr,
+    out_bsn_ds        => out_bsn_ds,
+    out_bsn           => out_bsn
   );
 
 END str;

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd

@@ -50,10 +50,14 @@ ENTITY ddrctrl_input_address_counter IS
     in_sosi               : IN  t_dp_sosi;                                                                                                -- input data
     in_of                 : IN  NATURAL;
     in_bsn_wr             : IN  STD_LOGIC;
+    in_bsn_ds             : IN  NATURAL;
+    in_bsn                : IN  STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
     out_sosi              : OUT t_dp_sosi                         := c_dp_sosi_init;                                                      -- output data
     out_of                : OUT NATURAL;
     out_adr               : OUT NATURAL;
-    out_bsn_adr           : OUT NATURAL
+    out_bsn_adr           : OUT NATURAL;
+    out_bsn_ds            : OUT NATURAL;
+    out_bsn               : OUT STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0)
   );
 END ddrctrl_input_address_counter;
 
@@ -74,13 +78,17 @@ ARCHITECTURE rtl OF ddrctrl_input_address_counter IS
   out_sosi                : t_dp_sosi;
   out_of                  : NATURAL;
   out_bsn_adr             : NATURAL;
+  out_bsn_ds              : NATURAL;
+  out_bsn                 : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
   s_in_sosi               : t_dp_sosi;
   s_in_of                 : NATURAL;
+  s_in_bsn_wr             : STD_LOGIC;
+  s_in_bsn_ds             : NATURAL;
+  s_in_bsn                : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
   s_adr                   : NATURAL;
-  s_bsn_wr                : STD_LOGIC;
   END RECORD;
 
-  CONSTANT  c_t_reg_init  : t_reg                                 := (RESET, c_dp_sosi_init, 0, 0, c_dp_sosi_init, 0, 0, '0');
+  CONSTANT  c_t_reg_init  : t_reg                                 := (RESET, c_dp_sosi_init, 0, 0, 0, (OTHERS => '0'), c_dp_sosi_init, 0, '0', 0, (OTHERS => '0'), 0);
 
 
   -- signals for readability
@@ -98,41 +106,42 @@ BEGIN
 
   BEGIN
     v                                                             := q_reg;
+
+    -- compensate for delay in ddrctrl_input_address_counter
     v.out_sosi.data(c_data_w-1 DOWNTO 0)                          := q_reg.s_in_sosi.data(c_data_w - 1 DOWNTO 0);
     v.out_sosi.valid                                              := q_reg.s_in_sosi.valid;
     v.out_of                                                      := q_reg.s_in_of;
+    v.out_bsn_ds                                                  := q_reg.s_in_bsn_ds;
+    v.out_bsn                                                     := q_reg.s_in_bsn;
     v.s_in_sosi                                                   := in_sosi;
     v.s_in_of                                                     := in_of;
-    IF in_bsn_wr = '0' THEN
-      v.s_bsn_wr := '1';
-    END IF;
+    v.s_in_bsn_wr                                                 := in_bsn_wr;
+    v.s_in_bsn_ds                                                 := in_bsn_ds;
+    v.s_in_bsn                                                    := in_bsn;
 
 
     CASE q_reg.state IS
     WHEN RESET =>
       v.s_adr := c_max_adr-1;                                                                                                             -- when there is a reset the fifo in io_ddr always needs the first out_sosi.valid to stop flushing the data so the first data word always gets lost. if s_adr is set to 0 after a restart the word from s_adr 1 will be put at address 0 in memory.
 
-      IF in_bsn_wr = '1' AND v.s_bsn_wr = '1' THEN
+      IF q_reg.s_in_bsn_wr = '1' THEN
         v.out_bsn_adr := v.s_adr;
-        v.s_bsn_wr    := '0';
       END IF;
 
 
     WHEN COUNTING =>
       v.s_adr := q_reg.s_adr+1;
 
-      IF in_bsn_wr = '1' AND v.s_bsn_wr = '1' THEN
+      IF q_reg.s_in_bsn_wr = '1' THEN
         v.out_bsn_adr := v.s_adr;
-        v.s_bsn_wr    := '0';
       END IF;
 
 
     WHEN MAX =>
       v.s_adr := 0;
 
-      IF in_bsn_wr = '1' AND v.s_bsn_wr = '1' THEN
+      IF q_reg.s_in_bsn_wr = '1' THEN
         v.out_bsn_adr := v.s_adr;
-        v.s_bsn_wr    := '0';
       END IF;
 
 
@@ -158,5 +167,7 @@ BEGIN
   out_of      <= q_reg.out_of;
   out_adr     <= q_reg.s_adr;
   out_bsn_adr <= q_reg.out_bsn_adr;
+  out_bsn_ds  <= q_reg.out_bsn_ds;
+  out_bsn     <= q_reg.out_bsn;
 
 END rtl;

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd

@@ -33,17 +33,14 @@ USE dp_lib.dp_stream_pkg.ALL;
 
 ENTITY ddrctrl_input_pack IS
   GENERIC (
-
     g_nof_streams : POSITIVE := 12;                                           -- number of input streams
     g_data_w      : NATURAL  := 14                                            -- data with of input data vectors
-
   );
   PORT (
-
     in_sosi_arr   : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);                 -- input data
     out_data      : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0);  -- output data
-    out_bsn       : OUT STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0)          -- output bsn
-
+    out_bsn       : OUT STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);         -- output bsn
+    out_valid     : OUT STD_LOGIC
   );
 END ddrctrl_input_pack;
 
@@ -53,7 +50,15 @@ BEGIN
 
   -- Putting all the data from the different streams into one data vector.
   gen_extract_and_pack_data : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    p_generate : PROCESS(in_sosi_arr) IS
+    BEGIN
+      IF in_sosi_arr(0).valid = '1' THEN
         out_data(g_data_w*(I+1)-1 DOWNTO g_data_w*I) <= in_sosi_arr(I).data(g_data_w-1 DOWNTO 0);
+        out_valid <= '1';
+      ELSE
+        out_valid <= '0';
+      END IF;
+    END PROCESS;
   END GENERATE;
   out_bsn <= in_sosi_arr(0).bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
 

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd

@@ -46,6 +46,7 @@ ENTITY ddrctrl_input_repack IS
     in_bsn                  : IN  STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);                                                             -- input bsn
     in_stop                 : IN  STD_LOGIC := '0';
     in_adr                  : IN  NATURAL;
+    in_valid                : IN  STD_LOGIC;
     out_of                  : OUT NATURAL   := 0;                                                                                             -- amount of internal overflow this output
     out_sosi                : OUT t_dp_sosi := c_dp_sosi_init;                                                                                -- output data
     out_bsn_ds              : OUT NATURAL   := 0;
@@ -69,6 +70,9 @@ ARCHITECTURE rtl OF ddrctrl_input_repack IS
   state                     : t_state;                                                                                                        -- the state the process is currently in;
   c_v                       : STD_LOGIC_VECTOR(k_c_v_w-1 DOWNTO 0);                                                                           -- the vector that stores the input data until the data is put into the output data vector
   c_v_count                 : NATURAL;                                                                                                        -- the amount of times the c_v vector received data from the input since the last time it was filled completely
+  s_out_bsn_ds              : NATURAL;
+  s_out_bsn                 : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+  output_passed             : STD_LOGIC;
   out_data_count            : NATURAL;                                                                                                        -- the amount of times the output data vector has been filled since the last time c_v was filled completely
   out_bsn_written           : STD_LOGIC;                                                                                                      -- this signal gets high ones the out_bsn signal is updated, this is so in ddrctrl_input_address_counter the right address can be linked with the out_bsn signal
   out_of                    : NATURAL;                                                                                                        -- this is the amount of bits that the first data word(168) is shifted from the first bit in the data word(576)
@@ -77,7 +81,7 @@ ARCHITECTURE rtl OF ddrctrl_input_repack IS
   out_bsn                   : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);                                                                 -- this is the bsn corresponding to the data in memory
   END RECORD;
 
-  CONSTANT c_t_reg_init     : t_reg         := (RESET, (OTHERS => '0'), 0, 0, '0', 0, c_dp_sosi_init, 0, (OTHERS => '0'));
+  CONSTANT c_t_reg_init     : t_reg         := (RESET, (OTHERS => '0'), 0, 0, (OTHERS => '0'), '0', 0, '0', 0, c_dp_sosi_init, 0, (OTHERS => '0'));
 
 
   -- signals for readability
@@ -89,7 +93,7 @@ BEGIN
   q_reg <= d_reg WHEN rising_edge(clk);
 
   -- put the input data into c_v and fill the output vector from c_v
-  p_state : PROCESS(q_reg, rst)
+  p_state : PROCESS(q_reg, rst,in_data, in_bsn, in_stop, in_adr, in_valid)
 
     VARIABLE v                : t_reg;
 
@@ -104,19 +108,22 @@ BEGIN
       v.out_sosi.valid := '0';                                                                                                                -- out_sosi.valid 0
 
       -- BSN_INPUT
-      IF in_adr = 0 AND q_reg.out_bsn_written = '0' THEN
-        v.out_bsn         := in_bsn;                                                                                                          -- a bsn number is saved when adr ~ 0
+      IF NOT (in_bsn = q_reg.out_bsn) THEN
+        v.s_out_bsn         := in_bsn;                                                                                                          -- a bsn number is saved when the bsn changes
         IF g_in_data_w*q_reg.c_v_count+q_reg.out_of >= c_out_data_w THEN
-          v.out_bsn_ds    := g_in_data_w*q_reg.c_v_count+q_reg.out_of-c_out_data_w;                                                           -- the amount of bits between word[0] and data[0] where data is the data with the bsn
+          v.s_out_bsn_ds    := g_in_data_w*q_reg.c_v_count+q_reg.out_of-c_out_data_w;                                                           -- the amount of bits between word[0] and data[0] where data is the data with the bsn
         ELSE
-          v.out_bsn_ds    := g_in_data_w*q_reg.c_v_count+q_reg.out_of;                                                                        -- the amount of bits between word[0] and data[0] where data is the data with the bsn
+          v.s_out_bsn_ds    := g_in_data_w*q_reg.c_v_count+q_reg.out_of;                                                                        -- the amount of bits between word[0] and data[0] where data is the data with the bsn
         END IF;
         v.out_bsn_written := '1';                                                                                                             -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
+      ELSIF q_reg.output_passed = '1' THEN
+        v.out_bsn_written := '0';
+        v.output_passed := '0';
       END IF;
 
       IF rst = '1' THEN
         v.state := RESET;
-      ELSIF in_stop = '1' THEN
+      ELSIF in_stop = '1' OR in_valid = '0' THEN
         v.state := STOP;
       ELSIF ((g_in_data_w*(v.c_v_count+1))+v.out_of >= c_out_data_w*(v.out_data_count+1)) AND (v.out_data_count = 0) THEN
         v.state := FIRST_OUTPUT;
@@ -135,19 +142,26 @@ BEGIN
       v.out_data_count := q_reg.out_data_count+1;                                                                                             -- increase the counter of out_sosi.data with 1
 
       -- BSN_INPUT
-      IF in_adr = 0 AND q_reg.out_bsn_written = '0' THEN
-        v.out_bsn         := in_bsn;                                                                                                          -- a bsn number is saved when adr ~ 0
+      IF NOT (in_bsn = q_reg.out_bsn) THEN
+        v.out_bsn         := in_bsn;                                                                                                          -- a bsn number is saved when the bsn changes
         IF g_in_data_w*q_reg.c_v_count+q_reg.out_of >= c_out_data_w THEN
-          v.out_bsn_ds    := g_in_data_w*q_reg.c_v_count+q_reg.out_of-c_out_data_w;                                                           -- the amount of bits between word[0] and data[0] where data is the data with the bsn
+          v.s_out_bsn_ds    := g_in_data_w*q_reg.c_v_count+q_reg.out_of-c_out_data_w;                                                           -- the amount of bits between word[0] and data[0] where data is the data with the bsn
         ELSE
-          v.out_bsn_ds    := g_in_data_w*q_reg.c_v_count+q_reg.out_of;                                                                        -- the amount of bits between word[0] and data[0] where data is the data with the bsn
+          v.s_out_bsn_ds    := g_in_data_w*q_reg.c_v_count+q_reg.out_of;                                                                        -- the amount of bits between word[0] and data[0] where data is the data with the bsn
         END IF;
         v.out_bsn_written := '1';                                                                                                             -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
+        v.output_passed := '1';
+      END IF;
+      v.out_bsn_ds := v.s_out_bsn_ds;
+      v.out_bsn    := v.s_out_bsn;
+
+      IF q_reg.out_bsn_written = '1' THEN
+        v.output_passed := '1';
       END IF;
 
       IF rst = '1' THEN
         v.state := RESET;
-      ELSIF in_stop = '1' THEN
+      ELSIF in_stop = '1' OR in_valid = '0' THEN
         v.state := STOP;
       ELSIF ((g_in_data_w*(v.c_v_count+1))+v.out_of >= c_out_data_w*(v.out_data_count+1)) AND (v.out_data_count = 1) THEN
         v.state := OVERFLOW_OUTPUT;
@@ -166,19 +180,26 @@ BEGIN
       v.out_data_count := 0;                                                                                                                  -- reset counter
 
       -- BSN_INPUT
-      IF in_adr = 0 AND q_reg.out_bsn_written = '0' THEN
-        v.out_bsn         := in_bsn;                                                                                                          -- a bsn number is saved when adr ~ 0
+      IF NOT (in_bsn = q_reg.out_bsn) THEN
+        v.out_bsn         := in_bsn;                                                                                                          -- a bsn number is saved when the bsn changes
         IF g_in_data_w*q_reg.c_v_count+q_reg.out_of >= c_out_data_w THEN
-          v.out_bsn_ds    := g_in_data_w*q_reg.c_v_count+q_reg.out_of-c_out_data_w;                                                           -- the amount of bits between word[0] and data[0] where data is the data with the bsn
+          v.s_out_bsn_ds    := g_in_data_w*q_reg.c_v_count+q_reg.out_of-c_out_data_w;                                                           -- the amount of bits between word[0] and data[0] where data is the data with the bsn
         ELSE
-          v.out_bsn_ds    := g_in_data_w*q_reg.c_v_count+q_reg.out_of;                                                                        -- the amount of bits between word[0] and data[0] where data is the data with the bsn
+          v.s_out_bsn_ds    := g_in_data_w*q_reg.c_v_count+q_reg.out_of;                                                                        -- the amount of bits between word[0] and data[0] where data is the data with the bsn
         END IF;
         v.out_bsn_written := '1';                                                                                                             -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
+        v.output_passed := '1';
+      END IF;
+      v.out_bsn_ds := v.s_out_bsn_ds;
+      v.out_bsn    := v.s_out_bsn;
+
+      IF q_reg.out_bsn_written = '1' THEN
+        v.output_passed := '1';
       END IF;
 
       IF rst = '1' THEN
         v.state := RESET;
-      ELSIF in_stop = '1' THEN
+      ELSIF in_stop = '1' OR in_valid = '0' THEN
         v.state := STOP;
       ELSIF ((g_in_data_w*(v.c_v_count+1))+v.out_of >= c_out_data_w*(v.out_data_count+1)) AND (v.out_data_count = 0) THEN
         v.state := FIRST_OUTPUT;
@@ -191,7 +212,7 @@ BEGIN
 
       IF rst = '1' THEN
         v.state := RESET;
-      ELSIF in_stop = '1' THEN
+      ELSIF in_stop = '1' OR in_valid = '0' THEN
         v.state := STOP;
       ELSE
         v.state := FILL_VECTOR;
@@ -201,7 +222,7 @@ BEGIN
     WHEN STOP =>
       IF rst = '1' THEN
         v.state := RESET;
-      ELSIF in_stop = '1' THEN
+      ELSIF in_stop = '1' OR in_valid = '0' THEN
         v.state := STOP;
       ELSIF ((g_in_data_w*(v.c_v_count+1))+v.out_of >= c_out_data_w*(v.out_data_count+1)) AND (v.out_data_count = 0) THEN
         v.state := FIRST_OUTPUT;
@@ -216,10 +237,6 @@ BEGIN
 
     END CASE;
 
-    IF NOT (in_adr=0) THEN
-      v.out_bsn_written := '0';
-    END IF;
-
     d_reg <= v;
   END PROCESS;
 

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd

@@ -45,7 +45,8 @@ ENTITY ddrctrl_output IS
     g_sim_model       : BOOLEAN                                     := TRUE;                        -- determens if this is a simulation
     g_in_data_w       : NATURAL                                     := 576;
     g_nof_streams     : NATURAL                                     := 12;                          -- number of input streams
-    g_data_w          : NATURAL                                     := 14                           -- data with of input data vectors
+    g_data_w          : NATURAL                                     := 14;                          -- data with of input data vectors
+    g_block_size      : NATURAL                                     := 1024
   );
   PORT (
     clk               : IN  STD_LOGIC                               := '0';
@@ -74,7 +75,8 @@ BEGIN
   GENERIC MAP(
     g_tech_ddr        => g_tech_ddr,
     g_in_data_w       => g_in_data_w,
-    g_out_data_w      => c_out_data_w
+    g_out_data_w      => c_out_data_w,
+    g_block_size      => g_block_size
   )
   PORT MAP(
     clk               => clk,

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd

@@ -41,7 +41,8 @@ ENTITY ddrctrl_output_unpack IS
   GENERIC (
     g_tech_ddr      : t_c_tech_ddr;
     g_in_data_w     : NATURAL;
-    g_out_data_w    : NATURAL
+    g_out_data_w    : NATURAL;
+    g_block_size    : NATURAL
   );
   PORT (
     clk             : IN  STD_LOGIC;
@@ -69,11 +70,12 @@ ARCHITECTURE rtl OF ddrctrl_output_unpack IS
   dd_fresh        : STD_LOGIC;
   c_v             : STD_LOGIC_VECTOR(g_in_data_w*2-1 DOWNTO 0);
   sr_done         : STD_LOGIC;
+  bsn_cnt         : NATURAL;
   out_sosi        : t_dp_sosi;
   out_ready       : STD_LOGIC;
   END RECORD;
 
-  CONSTANT c_t_reg_init   : t_reg     := (RESET, 0, 0, (OTHERS => '0'), '0', (OTHERS => '0'), '0', c_dp_sosi_init, '0');
+  CONSTANT c_t_reg_init   : t_reg     := (RESET, 0, 0, (OTHERS => '0'), '0', (OTHERS => '0'), '0', 0, c_dp_sosi_init, '0');
 
 
   -- signals for readability
@@ -99,9 +101,14 @@ BEGIN
       v.out_ready := '0';
       v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := q_reg.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
       v.out_sosi.valid := '1';
-      v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
+      v.bsn_cnt := q_reg.bsn_cnt+1;
       v.op_data_cnt := q_reg.op_data_cnt+1;
 
+      IF q_reg.bsn_cnt = g_block_size-1 THEN
+        v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
+        v.bsn_cnt := 0;
+      END IF;
+
       IF in_sosi.valid = '1' THEN
         v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
         v.dd_fresh := '1';
@@ -125,13 +132,18 @@ BEGIN
       v.out_ready := '1';
       v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := q_reg.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
       v.out_sosi.valid := '1';
-      v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
+      v.bsn_cnt := q_reg.bsn_cnt+1;
       v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.c_v(g_in_data_w*2-1 DOWNTO g_in_data_w);
       v.c_v(g_in_data_w*2-1 DOWNTO g_in_data_w) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
       v.dd_fresh := '0';
       v.a_of := (g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-g_in_data_w;
       v.op_data_cnt := 0;
 
+      IF q_reg.bsn_cnt = g_block_size-1 THEN
+        v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
+        v.bsn_cnt := 0;
+      END IF;
+
       IF in_sosi.valid = '1' THEN
         v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
         v.dd_fresh := '1';
@@ -155,7 +167,7 @@ BEGIN
       v.out_ready := '0';
       v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
       v.dd_fresh := '0';
-      v.a_of := in_ds+2-((12-5)*14);  -- will be fixed after in_ds is fixed in ddrctrl_controller.
+      v.a_of := in_ds+2+((5)*14);  -- will be fixed after in_ds is fixed in ddrctrl_controller.
       v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := v.c_v(g_out_data_w+v.a_of-1 DOWNTO v.a_of);
       v.out_sosi.valid := '1';
       v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := in_bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
@@ -181,7 +193,7 @@ BEGIN
       v.dd_fresh        := '0';
       v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := v.c_v(g_out_data_w*2+q_reg.a_of-1 DOWNTO g_out_data_w+q_reg.a_of);
       v.out_sosi.valid  := '1';
-      v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
+      v.bsn_cnt         := 1;
       v.op_data_cnt     := 2;
       v.sr_done         := '1';
 

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd

@@ -44,7 +44,8 @@ ENTITY tb_ddrctrl IS
     g_technology              : NATURAL                                               := c_tech_select_default;
     g_tech_ddr3               : t_c_tech_ddr                                          := c_tech_ddr3_4g_800m_master;
     g_tech_ddr4               : t_c_tech_ddr                                          := c_tech_ddr4_4g_1600m;
-    g_stop_percentage         : NATURAL                                               := 80                                       -- percentage there needs to be already written in the ddr memory when a stop gets triggered
+    g_stop_percentage         : NATURAL                                               := 80;                                      -- percentage there needs to be already written in the ddr memory when a stop gets triggered
+    g_block_size              : NATURAL                                               := 1024                                     -- amount of samples that goes into one bsn
   );
 END tb_ddrctrl;
 
@@ -78,13 +79,14 @@ ARCHITECTURE tb OF tb_ddrctrl IS
   -- function for making total data vector
   FUNCTION  c_total_vector_init RETURN STD_LOGIC_VECTOR IS
     VARIABLE temp             : STD_LOGIC_VECTOR(c_in_data_w*c_sim_length-1 DOWNTO 0);
-    VARIABLE conv             : STD_LOGIC_VECTOR(32-1 DOWNTO 0);                                                                  -- removes a warning
+    VARIABLE conv             : STD_LOGIC_VECTOR(168-1 DOWNTO 0) := (OTHERS => '0');                                                                  -- removes a warning
   BEGIN
     FOR I IN 0 TO c_sim_length-1 LOOP
-      conv                                     := TO_UVEC(I, 32);
-      FOR J IN 0 TO g_nof_streams-1 LOOP
-        temp(g_data_w*((I*g_nof_streams)+J+1)-1 DOWNTO g_data_w*((I*g_nof_streams)+j)) := conv(g_data_w-1 DOWNTO 0);
-      END LOOP;
+      temp((g_data_w*(I+1)*g_nof_streams)-1 DOWNTO g_data_w*I*g_nof_streams) := conv(168-1 DOWNTO 0);
+      conv                                     := TO_UVEC(I, 168);
+      --FOR J IN 0 TO g_nof_streams-1 LOOP
+        --temp(g_data_w*((I*g_nof_streams)+J+1)-1 DOWNTO g_data_w*((I*g_nof_streams)+j)) := conv(g_data_w-1 DOWNTO 0);
+      --END LOOP;
     END LOOP;
     RETURN temp;
   END FUNCTION c_total_vector_init;
@@ -134,10 +136,9 @@ BEGIN
   p_test : PROCESS
   BEGIN
 
-    bsn(c_check-1 DOWNTO c_check_bottom) <= c_ones(c_check-c_check_bottom-1 DOWNTO 0);
-
     -- start the test
     tb_end          <= '0';
+    in_sosi_arr(0).valid <= '0';
     WAIT UNTIL rising_edge(clk);                                                                                                  -- align to rising edge
     WAIT FOR c_clk_period*4;
     rst <= '1';
@@ -155,9 +156,9 @@ BEGIN
         in_data_cnt     <= in_data_cnt+1;
         fill_in_sosi_arr_0 : FOR I IN 0 TO g_nof_streams-1 LOOP
           in_sosi_arr(I).data(g_data_w-1 DOWNTO 0)   <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
+          in_sosi_arr(I).valid <= '1';
         END LOOP;
         in_sosi_arr(0).bsn(c_dp_stream_bsn_w-1 DOWNTO 0) <= bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
-        bsn <= INCR_UVEC(bsn, 1);
         IF K = 1 AND J = 0 THEN
           stop_in <= '1';
         ELSE
@@ -166,6 +167,7 @@ BEGIN
         WAIT FOR c_clk_period*1;
       END LOOP;
     END LOOP;
+    in_sosi_arr(0).valid <= '0';
     test_running      <= '0';
 
 
@@ -175,6 +177,23 @@ BEGIN
     ASSERT FALSE                                                                                                                          REPORT "Test: OK"                                                                                                                             SEVERITY FAILURE;
   END PROCESS;
 
+  p_bsn : PROCESS
+    VARIABLE bsn_cnt : NATURAL := 0;
+  BEGIN
+    bsn(c_check-1 DOWNTO c_check_bottom) <= c_ones(c_check-c_check_bottom-1 DOWNTO 0);
+    FOR I IN 0 TO (c_sim_length*4)-1 LOOP
+      WAIT UNTIL rising_edge(clk);
+      IF in_sosi_arr(0).valid = '1' THEN
+        IF bsn_cnt = g_block_size-1 THEN
+          bsn_cnt := 0;
+          bsn <= INCR_UVEC(bsn, 1);
+        ELSE
+          bsn_cnt := bsn_cnt + 1;
+        END IF;
+      END IF;
+    END LOOP;
+  END PROCESS;
+
   p_checking_output_data : PROCESS  -- first do tickets L2SDP-708 and L2SDP-707 before finsishing this is worth time
   BEGIN
     WAIT UNTIL rising_edge(clk);
@@ -201,7 +220,8 @@ BEGIN
     g_technology      => g_technology,
     g_nof_streams     => g_nof_streams,
     g_data_w          => g_data_w,
-    g_stop_percentage => g_stop_percentage
+    g_stop_percentage => g_stop_percentage,
+    g_block_size      => g_block_size
   )
   PORT MAP (
     clk               => clk,