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Commit 87bc0cca authored by Eric Kooistra's avatar Eric Kooistra
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Merge branch 'L2SDP-514' into 'master'

Resolve L2SDP-514

Closes L2SDP-514

See merge request desp/hdl!161
parents 8a0bf9f5 9f3bc269
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1 merge request!161Resolve L2SDP-514
schema_name : args
schema_version: 1.0
schema_type : fpga
hdl_library_name: unb2c_test
fpga_name : unb2c_test
fpga_description: "FPGA design unb2c_test"
parameters:
- { name: c_nof_streams_1GbE_UDP, value: 2 }
- { name: c_def_1GbE_block_size, value: 20 }
- { name: c_nof_streams_10GbE_UDP, value: 72 }
- { name: c_def_10GbE_block_size, value: 900 }
- { name: c_nof_streams_qsfp, value: 24 }
- { name: c_nof_streams_ring, value: 24 }
- { name: c_nof_streams_back0, value: 24 }
- { name: c_ddr_db_buf_nof_data, value: 1024 }
- { name: c_nof_streams_jesd204b, value: 12 }
- { name: c_jesd_db_buf_nof_data, value: 131072 }
peripherals:
# ctrl_unb2c_board
- peripheral_name: unb2c_board/system_info
lock_base_address: 0x10000
mm_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
- peripheral_name: unb2c_board/wdi
mm_port_names:
- REG_WDI
- peripheral_name: unb2c_board/unb2_fpga_sens
mm_port_names:
- REG_FPGA_TEMP_SENS
- REG_FPGA_VOLTAGE_SENS
- peripheral_name: unb2c_board/ram_scrap
mm_port_names:
- RAM_SCRAP
- peripheral_name: eth/eth
mm_port_names:
- AVS_ETH_0_TSE
- AVS_ETH_0_REG
- AVS_ETH_0_RAM
- peripheral_name: ppsh/ppsh
mm_port_names:
- PIO_PPS
- peripheral_name: epcs/epcs
mm_port_names:
- REG_EPCS
- peripheral_name: dp/dpmm
mm_port_names:
- REG_DPMM_CTRL
- REG_DPMM_DATA
- peripheral_name: dp/mmdp
mm_port_names:
- REG_MMDP_CTRL
- REG_MMDP_DATA
- peripheral_name: remu/remu
mm_port_names:
- REG_REMU
# Heater
- peripheral_name: util/heater
mm_port_names:
- REG_HEATER
# 1GbE
- peripheral_name: diag/diag_block_gen
peripheral_group: eth_1gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
- { name: g_buf_dat_w, value: 32 }
- { name: g_buf_addr_w, value: ceil_log2(c_def_1GbE_block_size) }
mm_port_names:
- REG_DIAG_BG_1GBE
- RAM_DIAG_BG_1GBE
- peripheral_name: diag/diag_tx_seq
peripheral_group: eth_1gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
mm_port_names:
- REG_DIAG_TX_SEQ_1GBE
- peripheral_name: dp/dp_bsn_monitor
peripheral_group: eth_1gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
mm_port_names:
- REG_BSN_MONITOR_1GBE
- peripheral_name: diag/diag_data_buffer
peripheral_group: eth_1gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
- { name: g_data_w, value: 32 }
- { name: g_nof_data, value: c_def_1GbE_block_size }
mm_port_names:
- REG_DIAG_DATA_BUFFER_1GBE
- RAM_DIAG_DATA_BUFFER_1GBE
- peripheral_name: diag/diag_rx_seq
peripheral_group: eth_1gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
mm_port_names:
- REG_DIAG_TX_SEQ_1GBE
# 10GbE
- peripheral_name: diag/diag_block_gen
peripheral_group: eth_10gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_10GbE_UDP }
- { name: g_buf_dat_w, value: 64 }
- { name: g_buf_addr_w, value: ceil_log2(c_def_10GbE_block_size) }
mm_port_names:
- REG_DIAG_BG_10GBE
- RAM_DIAG_BG_10GBE
- peripheral_name: diag/diag_tx_seq
peripheral_group: eth_10gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_10GbE_UDP }
mm_port_names:
- REG_DIAG_TX_SEQ_10GBE
- peripheral_name: dp/dp_bsn_monitor
peripheral_group: eth_10gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_10GbE_UDP }
mm_port_names:
- REG_BSN_MONITOR_10GBE
- peripheral_name: diag/diag_data_buffer
peripheral_group: eth_10gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_10GbE_UDP }
- { name: g_data_w, value: 64 }
- { name: g_nof_data, value: c_def_10GbE_block_size }
mm_port_names:
- REG_DIAG_DATA_BUFFER_10GBE
- RAM_DIAG_DATA_BUFFER_10GBE
- peripheral_name: diag/diag_rx_seq
peripheral_group: eth_10gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_10GbE_UDP }
mm_port_names:
- REG_DIAG_TX_SEQ_10GBE
- peripheral_name: tr_10GbE/tr_10GbE_unb2legacy
peripheral_group: qsfp_ring
parameter_overrides:
- { name: g_nof_macs, value: c_nof_streams_qsfp + c_nof_streams_ring }
mm_port_names:
- REG_TR_10GBE_QSFP_RING
- peripheral_name: tr_10GbE/tr_10GbE_eth10g
peripheral_group: qsfp_ring
parameter_overrides:
- { name: g_nof_macs, value: c_nof_streams_qsfp + c_nof_streams_ring }
mm_port_names:
- REG_ETH10G_QSFP_RING
- peripheral_name: tr_10GbE/tr_10GbE_unb2legacy
peripheral_group: back0
parameter_overrides:
- { name: g_nof_macs, value: c_nof_streams_back0 }
mm_port_names:
- REG_TR_10GBE_BACK0
- peripheral_name: tr_10GbE/tr_10GbE_eth10g
peripheral_group: back0
parameter_overrides:
- { name: g_nof_macs, value: c_nof_streams_back0 }
mm_port_names:
- REG_ETH10G_BACK0
# DDR4 : MB I
- peripheral_name: ddr/io_ddr
peripheral_group: MB_I
mm_port_names:
- REG_IO_DDR_MB_I
- peripheral_name: diag/diag_tx_seq
peripheral_group: MB_I
mm_port_names:
- REG_DIAG_TX_SEQ_DDR_MB_I
- peripheral_name: diag/diag_rx_seq
peripheral_group: MB_I
mm_port_names:
- REG_DIAG_RX_SEQ_DDR_MB_I
- peripheral_name: diag/diag_data_buffer
peripheral_group: ddr_MB_I
parameter_overrides:
- { name: g_data_w, value: 32 }
- { name: g_nof_data, value: c_ddr_db_buf_nof_data }
mm_port_names:
- REG_DIAG_DATA_BUFFER_DDR_MB_I
- RAM_DIAG_DATA_BUFFER_DDR_MB_I
# DDR4 : MB II
- peripheral_name: ddr/io_ddr
peripheral_group: MB_II
mm_port_names:
- REG_IO_DDR_MB_II
- peripheral_name: diag/diag_tx_seq
peripheral_group: MB_II
mm_port_names:
- REG_DIAG_TX_SEQ_DDR_MB_II
- peripheral_name: diag/diag_rx_seq
peripheral_group: MB_II
mm_port_names:
- REG_DIAG_RX_SEQ_DDR_MB_II
- peripheral_name: diag/diag_data_buffer
peripheral_group: ddr_MB_II
parameter_overrides:
- { name: g_data_w, value: 32 }
- { name: g_nof_data, value: c_ddr_db_buf_nof_data }
mm_port_names:
- REG_DIAG_DATA_BUFFER_DDR_MB_II
- RAM_DIAG_DATA_BUFFER_DDR_MB_II
# JESD
- peripheral_name: tech_jesd204b/jesd_ctrl
mm_port_names:
- PIO_JESD_CTRL
- peripheral_name: tech_jesd204b/jesd204b_arria10
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_jesd204b }
mm_port_names:
- JESD204B
- peripheral_name: dp/dp_bsn_source
mm_port_names:
- REG_BSN_SOURCE
- peripheral_name: dp/dp_bsn_monitor
peripheral_group: input
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_jesd204b }
mm_port_names:
- REG_BSN_MONITOR_INPUT
- peripheral_name: diag/diag_data_buffer
peripheral_group: bsn
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_jesd204b }
- { name: g_data_w, value: 16 }
- { name: g_nof_data, value: c_jesd_db_buf_nof_data }
mm_port_names:
- REG_DIAG_DATA_BUFFER_BSN
- RAM_DIAG_DATA_BUFFER_BSN
fpga_name = unb2c_test
number_of_columns = 13
# There can be multiple lines with a single key. The host should ignore unknown keys.
# The lines with columns follow after the number_of_columns keys. The host should ignore
# the extra columns in case the mmap contains more columns than the host expects.
#
# col 1: mm_port_name, if - then it is part of previous MM port.
# col 2: number of peripherals, if - then it is part of previous peripheral.
# col 3: number of mm_ports, if - then it is part of previous MM port.
# col 4: mm_port_type, if - then it is part of previous MM port.
# col 5: field_name
# col 6: field start address (in MM words)
# col 7: number of fields, if - then it is part of previous field_name.
# col 8: field access_mode, if - then it is part of previous field_name.
# col 9: field radix, if - then it is part of previous field_name.
# col 10: field mm_mask
# col 11: field user_mask, if - then it is same as mm_mask
# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
#
# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
# ---------------------------- ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0] - -
PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] - - -
- - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] - - -
- - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] - - -
- - - - info_cs_sim 0x00008000 1 RO uint32 b[10:10] - - -
- - - - info_fw_version_major 0x00008000 1 RO uint32 b[19:16] - - -
- - - - info_fw_version_minor 0x00008000 1 RO uint32 b[23:20] - - -
- - - - info_rom_version 0x00008000 1 RO uint32 b[26:24] - - -
- - - - info_technology 0x00008000 1 RO uint32 b[31:27] - - -
- - - - use_phy 0x00008001 1 RO uint32 b[7:0] - - -
- - - - design_name 0x00008002 52 RO char8 b[31:0] b[7:0] - -
- - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
- - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
- - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
- - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00080000 1 WO uint32 b[31:0] - - -
REG_FPGA_TEMP_SENS 1 1 REG temp 0x00100000 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00100000 6 RO uint32 b[31:0] - - -
RAM_SCRAP 1 1 RAM data 0x00180000 512 RW uint32 b[31:0] - - -
AVS_ETH_0_TSE 1 1 REG status 0x00200000 1024 RO uint32 b[31:0] - - -
AVS_ETH_0_REG 1 1 REG status 0x00200000 12 RO uint32 b[31:0] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00200400 1024 RW uint32 b[31:0] - - -
PIO_PPS 1 1 REG capture_cnt 0x00280000 1 RO uint32 b[29:0] - - -
- - - - stable 0x00280000 1 RO uint32 b[30:30] - - -
- - - - toggle 0x00280000 1 RO uint32 b[31:31] - - -
- - - - expected_cnt 0x00280001 1 RW uint32 b[27:0] - - -
- - - - edge 0x00280001 1 RW uint32 b[31:31] - - -
- - - - offset_cnt 0x00280002 1 RO uint32 b[27:0] - - -
REG_EPCS 1 1 REG addr 0x00300000 1 WO uint32 b[23:0] - - -
- - - - rden 0x00300001 1 WO uint32 b[0:0] - - -
- - - - read_bit 0x00300002 1 WO uint32 b[0:0] - - -
- - - - write_bit 0x00300003 1 WO uint32 b[0:0] - - -
- - - - sector_erase 0x00300004 1 WO uint32 b[0:0] - - -
- - - - busy 0x00300005 1 RO uint32 b[0:0] - - -
- - - - unprotect 0x00300006 1 WO uint32 b[31:0] - - -
REG_DPMM_CTRL 1 1 REG rd_usedw 0x00380000 1 RO uint32 b[31:0] - - -
REG_DPMM_DATA 1 1 FIFO data 0x00380400 1 RO uint32 b[31:0] - - -
REG_MMDP_CTRL 1 1 REG wr_usedw 0x00400000 1 RO uint32 b[31:0] - - -
- - - - wr_availw 0x00400001 1 RO uint32 b[31:0] - - -
REG_MMDP_DATA 1 1 FIFO data 0x00400400 1 WO uint32 b[31:0] - - -
REG_REMU 1 1 REG reconfigure 0x00480000 1 WO uint32 b[31:0] - - -
- - - - param 0x00480001 1 WO uint32 b[2:0] - - -
- - - - read_param 0x00480002 1 WO uint32 b[0:0] - - -
- - - - write_param 0x00480003 1 WO uint32 b[0:0] - - -
- - - - data_out 0x00480004 1 RO uint32 b[23:0] - - -
- - - - data_in 0x00480005 1 WO uint32 b[23:0] - - -
- - - - busy 0x00480006 1 RO uint32 b[0:0] - - -
REG_HEATER 1 1 REG enable 0x00500000 25 RW uint32 b[31:0] - - -
REG_DIAG_BG_1GBE 1 1 REG enable 0x00580000 1 RW uint32 b[0:0] - - -
- - - - enable_sync 0x00580000 1 RW uint32 b[1:1] - - -
- - - - samples_per_packet 0x00580001 1 RW uint32 b[31:0] - - -
- - - - blocks_per_sync 0x00580002 1 RW uint32 b[31:0] - - -
- - - - gapsize 0x00580003 1 RW uint32 b[31:0] - - -
- - - - mem_low_adrs 0x00580004 1 RW uint32 b[31:0] - - -
- - - - mem_high_adrs 0x00580005 1 RW uint32 b[31:0] - - -
- - - - bsn_init 0x00580006 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00580007 - - - b[31:0] b[63:32] - -
RAM_DIAG_BG_1GBE 1 2 RAM data 0x00580400 32 RW uint32 b[31:0] - - 32
REG_DIAG_TX_SEQ_1GBE 1 2 REG control 0x00600000 1 RW uint32 b[2:0] - - 4
- - - - init 0x00600001 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00600002 1 RO uint32 b[31:0] - - -
- - - - modulo 0x00600003 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_1GBE 1 2 REG xon_stable 0x00680000 1 RO uint32 b[0:0] - - 16
- - - - ready_stable 0x00680000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00680000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00680001 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00680002 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00680003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00680004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00680005 1 RO uint32 b[31:0] - - -
- - - - bsn_first 0x00680006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00680007 - - - b[31:0] b[63:32] - -
- - - - bsn_first_cycle_cnt 0x00680008 1 RO uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_1GBE 1 2 REG sync_cnt 0x00700000 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x00700001 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_1GBE 1 2 RAM data 0x00700400 20 RW uint32 b[31:0] - - 32
REG_DIAG_TX_SEQ_1GBE 1 2 REG control 0x00780000 1 RW uint32 b[1:0] - - 8
- - - - result 0x00780001 1 RO uint32 b[1:0] - - -
- - - - rx_cnt 0x00780002 1 RO uint32 b[31:0] - - -
- - - - rx_sample 0x00780003 1 RO uint32 b[31:0] - - -
- - - - step_0 0x00780004 1 RW uint32 b[31:0] - - -
- - - - step_1 0x00780005 1 RW uint32 b[31:0] - - -
- - - - step_2 0x00780006 1 RW uint32 b[31:0] - - -
- - - - step_3 0x00780007 1 RW uint32 b[31:0] - - -
REG_DIAG_BG_10GBE 1 1 REG enable 0x00800000 1 RW uint32 b[0:0] - - -
- - - - enable_sync 0x00800000 1 RW uint32 b[1:1] - - -
- - - - samples_per_packet 0x00800001 1 RW uint32 b[31:0] - - -
- - - - blocks_per_sync 0x00800002 1 RW uint32 b[31:0] - - -
- - - - gapsize 0x00800003 1 RW uint32 b[31:0] - - -
- - - - mem_low_adrs 0x00800004 1 RW uint32 b[31:0] - - -
- - - - mem_high_adrs 0x00800005 1 RW uint32 b[31:0] - - -
- - - - bsn_init 0x00800006 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00800007 - - - b[31:0] b[63:32] - -
RAM_DIAG_BG_10GBE 1 72 RAM data 0x00840000 1024 RW uint32 b[31:0] b[31:0] - 2048
- - - - - 0x00840001 - - - b[31:0] b[63:32] - -
REG_DIAG_TX_SEQ_10GBE 1 72 REG control 0x00880000 1 RW uint32 b[2:0] - - 4
- - - - init 0x00880001 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00880002 1 RO uint32 b[31:0] - - -
- - - - modulo 0x00880003 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_10GBE 1 72 REG xon_stable 0x00900000 1 RO uint32 b[0:0] - - 16
- - - - ready_stable 0x00900000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00900000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00900001 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00900002 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00900003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00900004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00900005 1 RO uint32 b[31:0] - - -
- - - - bsn_first 0x00900006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00900007 - - - b[31:0] b[63:32] - -
- - - - bsn_first_cycle_cnt 0x00900008 1 RO uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_10GBE 1 72 REG sync_cnt 0x00980000 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x00980001 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_10GBE 1 72 RAM data 0x009c0000 900 RW uint32 b[31:0] b[31:0] - 2048
- - - - - 0x009c0001 - - - b[31:0] b[63:32] - -
REG_DIAG_TX_SEQ_10GBE 1 72 REG control 0x00a00000 1 RW uint32 b[1:0] - - 8
- - - - result 0x00a00001 1 RO uint32 b[1:0] - - -
- - - - rx_cnt 0x00a00002 1 RO uint32 b[31:0] - - -
- - - - rx_sample 0x00a00003 1 RO uint32 b[31:0] - - -
- - - - step_0 0x00a00004 1 RW uint32 b[31:0] - - -
- - - - step_1 0x00a00005 1 RW uint32 b[31:0] - - -
- - - - step_2 0x00a00006 1 RW uint32 b[31:0] - - -
- - - - step_3 0x00a00007 1 RW uint32 b[31:0] - - -
REG_TR_10GBE_QSFP_RING 1 48 REG rx_transfer_control 0x00a80000 1 RW uint32 b[0:0] - - 1
- - - - rx_transfer_status 0x00a80001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00a80002 1 RW uint32 b[0:0] - - -
- - - - rx_padcrc_control 0x00a80040 1 RW uint32 b[1:0] - - -
- - - - rx_crccheck_control 0x00a80080 1 RW uint32 b[1:0] - - -
- - - - rx_pktovrflow_error 0x00a800c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a800c1 - - - b[31:0] b[31:0] - -
- - - - rx_pktovrflow_etherstatsdropevents 0x00a800c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a800c3 - - - b[31:0] b[31:0] - -
- - - - rx_lane_decoder_preamble_control 0x00a80100 1 RW uint32 b[0:0] - - -
- - - - rx_preamble_inserter_control 0x00a80140 1 RW uint32 b[0:0] - - -
- - - - rx_frame_control 0x00a80800 1 RW uint32 b[19:0] - - -
- - - - rx_frame_maxlength 0x00a80801 1 RW uint32 b[15:0] - - -
- - - - rx_frame_addr0 0x00a80802 1 RW uint32 b[15:0] - - -
- - - - rx_frame_addr1 0x00a80803 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr0_0 0x00a80804 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr0_1 0x00a80805 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr1_0 0x00a80806 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr1_1 0x00a80807 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr2_0 0x00a80808 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr2_1 0x00a80809 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr3_0 0x00a8080a 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr3_1 0x00a8080b 1 RW uint32 b[15:0] - - -
- - - - rx_pfc_control 0x00a80818 1 RW uint32 b[16:0] - - -
- - - - rx_stats_clr 0x00a80c00 1 RW uint32 b[0:0] - - -
- - - - rx_stats_framesok 0x00a80c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c03 - - - b[31:0] b[31:0] - -
- - - - rx_stats_frameserr 0x00a80c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c05 - - - b[31:0] b[31:0] - -
- - - - rx_stats_framescrcerr 0x00a80c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c07 - - - b[31:0] b[31:0] - -
- - - - rx_stats_octetsok 0x00a80c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c09 - - - b[31:0] b[31:0] - -
- - - - rx_stats_pausemacctrl_frames 0x00a80c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c0b - - - b[31:0] b[31:0] - -
- - - - rx_stats_iferrors 0x00a80c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c0d - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicast_framesok 0x00a80c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c0f - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicast_frameserr 0x00a80c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c11 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicastframesok 0x00a80c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c13 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicast_frameserr 0x00a80c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c15 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcastframesok 0x00a80c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c17 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcast_frameserr 0x00a80c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c19 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatsoctets 0x00a80c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c1b - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatspkts 0x00a80c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c1d - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_undersizepkts 0x00a80c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c1f - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_oversizepkts 0x00a80c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c21 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts64octets 0x00a80c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c23 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts65to127octets 0x00a80c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c25 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts128to255octets 0x00a80c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c27 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts256to511octets 0x00a80c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c29 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts512to1023octets 0x00a80c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c2b - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstat_pkts1024to1518octets 0x00a80c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c2d - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts1519toxoctets 0x00a80c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c2f - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_fragments 0x00a80c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c31 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_jabbers 0x00a80c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c33 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatscrcerr 0x00a80c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c35 - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicastmacctrlframes 0x00a80c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c37 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicastmac_ctrlframes 0x00a80c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c39 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcastmac_ctrlframes 0x00a80c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c3b - - - b[31:0] b[31:0] - -
- - - - rx_stats_pfcmacctrlframes 0x00a80c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c3d - - - b[31:0] b[31:0] - -
- - - - tx_transfer_status 0x00a81001 1 RO uint32 b[0:0] - - -
- - - - tx_padins_control 0x00a81040 1 RW uint32 b[0:0] - - -
- - - - tx_crcins_control 0x00a81080 1 RW uint32 b[1:0] - - -
- - - - tx_pktunderflow_error 0x00a810c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a810c1 - - - b[31:0] b[31:0] - -
- - - - tx_preamble_control 0x00a81100 1 RW uint32 b[0:0] - - -
- - - - tx_pauseframe_control 0x00a81140 1 RW uint32 b[1:0] - - -
- - - - tx_pauseframe_quanta 0x00a81141 1 RW uint32 b[15:0] - - -
- - - - tx_pauseframe_enable 0x00a81142 1 RW uint32 b[0:0] - - -
- - - - pfc_pause_quanta_0 0x00a81180 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_1 0x00a81181 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_2 0x00a81182 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_3 0x00a81183 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_4 0x00a81184 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_5 0x00a81185 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_6 0x00a81186 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_7 0x00a81187 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_0 0x00a81190 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_1 0x00a81191 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_2 0x00a81192 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_3 0x00a81193 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_4 0x00a81194 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_5 0x00a81195 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_6 0x00a81196 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_7 0x00a81197 1 RW uint32 b[31:0] - - -
- - - - tx_pfc_priority_enable 0x00a811a0 1 RW uint32 b[7:0] - - -
- - - - tx_addrins_control 0x00a81200 1 RW uint32 b[0:0] - - -
- - - - tx_addrins_macaddr0 0x00a81201 1 RW uint32 b[31:0] - - -
- - - - tx_addrins_macaddr1 0x00a81202 1 RW uint32 b[15:0] - - -
- - - - tx_frame_maxlength 0x00a81801 1 RW uint32 b[15:0] - - -
- - - - tx_stats_clr 0x00a81c00 1 RW uint32 b[0:0] - - -
- - - - tx_stats_framesok 0x00a81c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c03 - - - b[31:0] b[31:0] - -
- - - - tx_stats_frameserr 0x00a81c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c05 - - - b[31:0] b[31:0] - -
- - - - tx_stats_framescrcerr 0x00a81c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c07 - - - b[31:0] b[31:0] - -
- - - - tx_stats_octetsok 0x00a81c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c09 - - - b[31:0] b[31:0] - -
- - - - tx_stats_pausemacctrl_frames 0x00a81c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c0b - - - b[31:0] b[31:0] - -
- - - - tx_stats_iferrors 0x00a81c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c0d - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicast_framesok 0x00a81c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c0f - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicast_frameserr 0x00a81c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c11 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicastframesok 0x00a81c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c13 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicast_frameserr 0x00a81c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c15 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcastframesok 0x00a81c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c17 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcast_frameserr 0x00a81c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c19 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatsoctets 0x00a81c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c1b - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatspkts 0x00a81c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c1d - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_undersizepkts 0x00a81c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c1f - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_oversizepkts 0x00a81c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c21 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts64octets 0x00a81c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c23 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts65to127octets 0x00a81c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c25 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts128to255octets 0x00a81c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c27 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts256to511octets 0x00a81c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c29 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts512to1023octets 0x00a81c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c2b - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstat_pkts1024to1518octets 0x00a81c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c2d - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts1519toxoctets 0x00a81c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c2f - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_fragments 0x00a81c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c31 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_jabbers 0x00a81c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c33 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatscrcerr 0x00a81c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c35 - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicastmacctrlframes 0x00a81c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c37 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicastmac_ctrlframes 0x00a81c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c39 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcastmac_ctrlframes 0x00a81c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00a81c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c3d - - - b[31:0] b[31:0] - -
REG_ETH10G_QSFP_RING 1 48 REG tx_snk_out_xon 0x00b00000 1 RO uint32 b[0:0] - - 1
- - - - xgmii_tx_ready 0x00b00000 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x00b00000 1 RO uint32 b[3:2] - - -
REG_TR_10GBE_BACK0 1 24 REG rx_transfer_control 0x00b80000 1 RW uint32 b[0:0] - - 1
- - - - rx_transfer_status 0x00b80001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00b80002 1 RW uint32 b[0:0] - - -
- - - - rx_padcrc_control 0x00b80040 1 RW uint32 b[1:0] - - -
- - - - rx_crccheck_control 0x00b80080 1 RW uint32 b[1:0] - - -
- - - - rx_pktovrflow_error 0x00b800c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b800c1 - - - b[31:0] b[31:0] - -
- - - - rx_pktovrflow_etherstatsdropevents 0x00b800c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b800c3 - - - b[31:0] b[31:0] - -
- - - - rx_lane_decoder_preamble_control 0x00b80100 1 RW uint32 b[0:0] - - -
- - - - rx_preamble_inserter_control 0x00b80140 1 RW uint32 b[0:0] - - -
- - - - rx_frame_control 0x00b80800 1 RW uint32 b[19:0] - - -
- - - - rx_frame_maxlength 0x00b80801 1 RW uint32 b[15:0] - - -
- - - - rx_frame_addr0 0x00b80802 1 RW uint32 b[15:0] - - -
- - - - rx_frame_addr1 0x00b80803 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr0_0 0x00b80804 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr0_1 0x00b80805 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr1_0 0x00b80806 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr1_1 0x00b80807 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr2_0 0x00b80808 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr2_1 0x00b80809 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr3_0 0x00b8080a 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr3_1 0x00b8080b 1 RW uint32 b[15:0] - - -
- - - - rx_pfc_control 0x00b80818 1 RW uint32 b[16:0] - - -
- - - - rx_stats_clr 0x00b80c00 1 RW uint32 b[0:0] - - -
- - - - rx_stats_framesok 0x00b80c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c03 - - - b[31:0] b[31:0] - -
- - - - rx_stats_frameserr 0x00b80c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c05 - - - b[31:0] b[31:0] - -
- - - - rx_stats_framescrcerr 0x00b80c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c07 - - - b[31:0] b[31:0] - -
- - - - rx_stats_octetsok 0x00b80c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c09 - - - b[31:0] b[31:0] - -
- - - - rx_stats_pausemacctrl_frames 0x00b80c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c0b - - - b[31:0] b[31:0] - -
- - - - rx_stats_iferrors 0x00b80c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c0d - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicast_framesok 0x00b80c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c0f - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicast_frameserr 0x00b80c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c11 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicastframesok 0x00b80c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c13 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicast_frameserr 0x00b80c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c15 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcastframesok 0x00b80c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c17 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcast_frameserr 0x00b80c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c19 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatsoctets 0x00b80c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c1b - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatspkts 0x00b80c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c1d - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_undersizepkts 0x00b80c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c1f - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_oversizepkts 0x00b80c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c21 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts64octets 0x00b80c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c23 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts65to127octets 0x00b80c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c25 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts128to255octets 0x00b80c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c27 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts256to511octets 0x00b80c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c29 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts512to1023octets 0x00b80c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c2b - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstat_pkts1024to1518octets 0x00b80c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c2d - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts1519toxoctets 0x00b80c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c2f - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_fragments 0x00b80c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c31 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_jabbers 0x00b80c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c33 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatscrcerr 0x00b80c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c35 - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicastmacctrlframes 0x00b80c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c37 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicastmac_ctrlframes 0x00b80c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c39 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcastmac_ctrlframes 0x00b80c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c3b - - - b[31:0] b[31:0] - -
- - - - rx_stats_pfcmacctrlframes 0x00b80c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c3d - - - b[31:0] b[31:0] - -
- - - - tx_transfer_status 0x00b81001 1 RO uint32 b[0:0] - - -
- - - - tx_padins_control 0x00b81040 1 RW uint32 b[0:0] - - -
- - - - tx_crcins_control 0x00b81080 1 RW uint32 b[1:0] - - -
- - - - tx_pktunderflow_error 0x00b810c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b810c1 - - - b[31:0] b[31:0] - -
- - - - tx_preamble_control 0x00b81100 1 RW uint32 b[0:0] - - -
- - - - tx_pauseframe_control 0x00b81140 1 RW uint32 b[1:0] - - -
- - - - tx_pauseframe_quanta 0x00b81141 1 RW uint32 b[15:0] - - -
- - - - tx_pauseframe_enable 0x00b81142 1 RW uint32 b[0:0] - - -
- - - - pfc_pause_quanta_0 0x00b81180 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_1 0x00b81181 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_2 0x00b81182 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_3 0x00b81183 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_4 0x00b81184 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_5 0x00b81185 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_6 0x00b81186 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_7 0x00b81187 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_0 0x00b81190 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_1 0x00b81191 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_2 0x00b81192 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_3 0x00b81193 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_4 0x00b81194 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_5 0x00b81195 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_6 0x00b81196 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_7 0x00b81197 1 RW uint32 b[31:0] - - -
- - - - tx_pfc_priority_enable 0x00b811a0 1 RW uint32 b[7:0] - - -
- - - - tx_addrins_control 0x00b81200 1 RW uint32 b[0:0] - - -
- - - - tx_addrins_macaddr0 0x00b81201 1 RW uint32 b[31:0] - - -
- - - - tx_addrins_macaddr1 0x00b81202 1 RW uint32 b[15:0] - - -
- - - - tx_frame_maxlength 0x00b81801 1 RW uint32 b[15:0] - - -
- - - - tx_stats_clr 0x00b81c00 1 RW uint32 b[0:0] - - -
- - - - tx_stats_framesok 0x00b81c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c03 - - - b[31:0] b[31:0] - -
- - - - tx_stats_frameserr 0x00b81c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c05 - - - b[31:0] b[31:0] - -
- - - - tx_stats_framescrcerr 0x00b81c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c07 - - - b[31:0] b[31:0] - -
- - - - tx_stats_octetsok 0x00b81c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c09 - - - b[31:0] b[31:0] - -
- - - - tx_stats_pausemacctrl_frames 0x00b81c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c0b - - - b[31:0] b[31:0] - -
- - - - tx_stats_iferrors 0x00b81c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c0d - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicast_framesok 0x00b81c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c0f - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicast_frameserr 0x00b81c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c11 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicastframesok 0x00b81c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c13 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicast_frameserr 0x00b81c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c15 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcastframesok 0x00b81c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c17 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcast_frameserr 0x00b81c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c19 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatsoctets 0x00b81c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c1b - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatspkts 0x00b81c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c1d - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_undersizepkts 0x00b81c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c1f - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_oversizepkts 0x00b81c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c21 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts64octets 0x00b81c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c23 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts65to127octets 0x00b81c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c25 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts128to255octets 0x00b81c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c27 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts256to511octets 0x00b81c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c29 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts512to1023octets 0x00b81c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c2b - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstat_pkts1024to1518octets 0x00b81c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c2d - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts1519toxoctets 0x00b81c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c2f - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_fragments 0x00b81c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c31 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_jabbers 0x00b81c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c33 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatscrcerr 0x00b81c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c35 - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicastmacctrlframes 0x00b81c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c37 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicastmac_ctrlframes 0x00b81c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c39 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcastmac_ctrlframes 0x00b81c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00b81c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c3d - - - b[31:0] b[31:0] - -
REG_ETH10G_BACK0 1 24 REG tx_snk_out_xon 0x00c00000 1 RO uint32 b[0:0] - - 1
- - - - xgmii_tx_ready 0x00c00000 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x00c00000 1 RO uint32 b[3:2] - - -
REG_IO_DDR_MB_I 1 1 REG burstbegin 0x00c80000 1 WO uint32 b[0:0] - - -
- - - - wr_not_rd 0x00c80001 1 WO uint32 b[0:0] - - -
- - - - done 0x00c80002 1 RO uint32 b[0:0] - - -
- - - - address 0x00c80005 1 WO uint32 b[31:0] - - -
- - - - burstsize 0x00c80006 1 WO uint32 b[31:0] - - -
- - - - flush 0x00c80007 1 RW uint32 b[0:0] - - -
REG_DIAG_TX_SEQ_DDR_MB_I 1 1 REG control 0x00d00000 1 RW uint32 b[2:0] - - -
- - - - init 0x00d00001 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00d00002 1 RO uint32 b[31:0] - - -
- - - - modulo 0x00d00003 1 RW uint32 b[31:0] - - -
REG_DIAG_RX_SEQ_DDR_MB_I 1 1 REG control 0x00d80000 1 RW uint32 b[1:0] - - -
- - - - result 0x00d80001 1 RO uint32 b[1:0] - - -
- - - - rx_cnt 0x00d80002 1 RO uint32 b[31:0] - - -
- - - - rx_sample 0x00d80003 1 RO uint32 b[31:0] - - -
- - - - step_0 0x00d80004 1 RW uint32 b[31:0] - - -
- - - - step_1 0x00d80005 1 RW uint32 b[31:0] - - -
- - - - step_2 0x00d80006 1 RW uint32 b[31:0] - - -
- - - - step_3 0x00d80007 1 RW uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_DDR_MB_I 1 1 REG sync_cnt 0x00e00000 1 RO uint32 b[31:0] - - -
- - - - word_cnt 0x00e00001 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_DDR_MB_I 1 1 RAM data 0x00e00400 1024 RW uint32 b[31:0] - - -
REG_IO_DDR_MB_II 1 1 REG burstbegin 0x00e80000 1 WO uint32 b[0:0] - - -
- - - - wr_not_rd 0x00e80001 1 WO uint32 b[0:0] - - -
- - - - done 0x00e80002 1 RO uint32 b[0:0] - - -
- - - - address 0x00e80005 1 WO uint32 b[31:0] - - -
- - - - burstsize 0x00e80006 1 WO uint32 b[31:0] - - -
- - - - flush 0x00e80007 1 RW uint32 b[0:0] - - -
REG_DIAG_TX_SEQ_DDR_MB_II 1 1 REG control 0x00f00000 1 RW uint32 b[2:0] - - -
- - - - init 0x00f00001 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00f00002 1 RO uint32 b[31:0] - - -
- - - - modulo 0x00f00003 1 RW uint32 b[31:0] - - -
REG_DIAG_RX_SEQ_DDR_MB_II 1 1 REG control 0x00f80000 1 RW uint32 b[1:0] - - -
- - - - result 0x00f80001 1 RO uint32 b[1:0] - - -
- - - - rx_cnt 0x00f80002 1 RO uint32 b[31:0] - - -
- - - - rx_sample 0x00f80003 1 RO uint32 b[31:0] - - -
- - - - step_0 0x00f80004 1 RW uint32 b[31:0] - - -
- - - - step_1 0x00f80005 1 RW uint32 b[31:0] - - -
- - - - step_2 0x00f80006 1 RW uint32 b[31:0] - - -
- - - - step_3 0x00f80007 1 RW uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_DDR_MB_II 1 1 REG sync_cnt 0x01000000 1 RO uint32 b[31:0] - - -
- - - - word_cnt 0x01000001 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_DDR_MB_II 1 1 RAM data 0x01000400 1024 RW uint32 b[31:0] - - -
PIO_JESD_CTRL 1 1 REG enable 0x01080000 1 RW uint32 b[30:0] - - -
- - - - reset 0x01080000 1 RW uint32 b[31:31] - - -
JESD204B 1 12 REG rx_dll_ctrl 0x01100014 1 RW uint32 b[16:0] - - 256
- - - - rx_syncn_sysref_ctrl 0x01100015 1 RW uint32 b[24:0] - - -
- - - - rx_csr_sysref_always_on 0x01100015 1 RW uint32 b[1:1] - - -
- - - - rx_csr_rbd_offset 0x01100015 1 RW uint32 b[10:3] - - -
- - - - rx_csr_lmfc_offset 0x01100015 1 RW uint32 b[19:12] - - -
- - - - rx_err0 0x01100018 1 RW uint32 b[8:0] - - -
- - - - rx_err1 0x01100019 1 RW uint32 b[9:0] - - -
- - - - csr_dev_syncn 0x01100020 1 RO uint32 b[0:0] - - -
- - - - csr_rbd_count 0x01100020 1 RO uint32 b[10:3] - - -
- - - - rx_status1 0x01100021 1 RW uint32 b[23:0] - - -
- - - - rx_status2 0x01100022 1 RW uint32 b[23:0] - - -
- - - - rx_status3 0x01100023 1 RW uint32 b[7:0] - - -
- - - - rx_ilas_csr_l 0x01100025 1 RW uint32 b[4:0] - - -
- - - - rx_ilas_csr_f 0x01100025 1 RW uint32 b[15:8] - - -
- - - - rx_ilas_csr_k 0x01100025 1 RW uint32 b[20:16] - - -
- - - - rx_ilas_csr_m 0x01100025 1 RW uint32 b[31:24] - - -
- - - - rx_ilas_csr_n 0x01100026 1 RW uint32 b[4:0] - - -
- - - - rx_ilas_csr_cs 0x01100026 1 RW uint32 b[7:6] - - -
- - - - rx_ilas_csr_np 0x01100026 1 RW uint32 b[12:8] - - -
- - - - rx_ilas_csr_subclassv 0x01100026 1 RW uint32 b[15:13] - - -
- - - - rx_ilas_csr_s 0x01100026 1 RW uint32 b[20:16] - - -
- - - - rx_ilas_csr_jesdv 0x01100026 1 RW uint32 b[23:21] - - -
- - - - rx_ilas_csr_cf 0x01100026 1 RW uint32 b[28:24] - - -
- - - - rx_ilas_csr_hd 0x01100026 1 RW uint32 b[31:31] - - -
- - - - rx_status4 0x0110003c 1 RW uint32 b[15:0] - - -
- - - - rx_status5 0x0110003d 1 RW uint32 b[15:0] - - -
- - - - rx_status6 0x0110003e 1 RW uint32 b[23:0] - - -
- - - - rx_status7 0x0110003f 1 RO uint32 b[31:0] - - -
REG_BSN_SOURCE 1 1 REG dp_on 0x01180000 1 RW uint32 b[0:0] - - -
- - - - dp_on_pps 0x01180000 1 RW uint32 b[1:1] - - -
- - - - nof_block_per_sync 0x01180001 1 RW uint32 b[31:0] - - -
- - - - bsn 0x01180002 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x01180003 - - - b[31:0] b[63:32] - -
REG_BSN_MONITOR_INPUT 1 12 REG xon_stable 0x01200000 1 RO uint32 b[0:0] - - 16
- - - - ready_stable 0x01200000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x01200000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x01200001 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x01200002 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x01200003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x01200004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x01200005 1 RO uint32 b[31:0] - - -
- - - - bsn_first 0x01200006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x01200007 - - - b[31:0] b[63:32] - -
- - - - bsn_first_cycle_cnt 0x01200008 1 RO uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x01280000 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x01280001 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x01400000 131072 RW uint32 b[31:0] b[15:0] - 131072
\ No newline at end of file
fpga_name = unb2c_test
number_of_columns = 13
# There can be multiple lines with a single key. The host should ignore unknown keys.
# The lines with columns follow after the number_of_columns keys. The host should ignore
# the extra columns in case the mmap contains more columns than the host expects.
#
# col 1: mm_port_name, if - then it is part of previous MM port.
# col 2: number of peripherals, if - then it is part of previous peripheral.
# col 3: number of mm_ports, if - then it is part of previous MM port.
# col 4: mm_port_type, if - then it is part of previous MM port.
# col 5: field_name
# col 6: field start address (in MM words)
# col 7: number of fields, if - then it is part of previous field_name.
# col 8: field access_mode, if - then it is part of previous field_name.
# col 9: field radix, if - then it is part of previous field_name.
# col 10: field mm_mask
# col 11: field user_mask, if - then it is same as mm_mask
# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
#
# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
# ---------------------------- ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
ROM_SYSTEM_INFO 1 1 RAM data 0x00004000 32768 RO char8 b[31:0] b[7:0] - -
PIO_SYSTEM_INFO 1 1 REG info 0x00000000 1 RO uint32 b[31:0] - - -
- - - - info_gn_index 0x00000000 1 RO uint32 b[7:0] - - -
- - - - info_hw_version 0x00000000 1 RO uint32 b[9:8] - - -
- - - - info_cs_sim 0x00000000 1 RO uint32 b[10:10] - - -
- - - - info_fw_version_major 0x00000000 1 RO uint32 b[19:16] - - -
- - - - info_fw_version_minor 0x00000000 1 RO uint32 b[23:20] - - -
- - - - info_rom_version 0x00000000 1 RO uint32 b[26:24] - - -
- - - - info_technology 0x00000000 1 RO uint32 b[31:27] - - -
- - - - use_phy 0x00000001 1 RO uint32 b[7:0] - - -
- - - - design_name 0x00000002 52 RO char8 b[31:0] b[7:0] - -
- - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - -
- - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - -
- - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
- - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
REG_FPGA_TEMP_SENS 1 1 REG temp 0x00000da8 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00000d60 6 RO uint32 b[31:0] - - -
RAM_SCRAP 1 1 RAM data 0x00000e00 512 RW uint32 b[31:0] - - -
AVS_ETH_0_TSE 1 1 REG status 0x00000800 1024 RO uint32 b[31:0] - - -
AVS_ETH_0_REG 1 1 REG status 0x00000d40 12 RO uint32 b[31:0] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00007c00 1024 RW uint32 b[31:0] - - -
PIO_PPS 1 1 REG capture_cnt 0x00000dc0 1 RO uint32 b[29:0] - - -
- - - - stable 0x00000dc0 1 RO uint32 b[30:30] - - -
- - - - toggle 0x00000dc0 1 RO uint32 b[31:31] - - -
- - - - expected_cnt 0x00000dc1 1 RW uint32 b[27:0] - - -
- - - - edge 0x00000dc1 1 RW uint32 b[31:31] - - -
- - - - offset_cnt 0x00000dc2 1 RO uint32 b[27:0] - - -
REG_EPCS 1 1 REG addr 0x00000d98 1 WO uint32 b[23:0] - - -
- - - - rden 0x00000d99 1 WO uint32 b[0:0] - - -
- - - - read_bit 0x00000d9a 1 WO uint32 b[0:0] - - -
- - - - write_bit 0x00000d9b 1 WO uint32 b[0:0] - - -
- - - - sector_erase 0x00000d9c 1 WO uint32 b[0:0] - - -
- - - - busy 0x00000d9d 1 RO uint32 b[0:0] - - -
- - - - unprotect 0x00000d9e 1 WO uint32 b[31:0] - - -
REG_DPMM_CTRL 1 1 REG rd_usedw 0x00000dcc 1 RO uint32 b[31:0] - - -
REG_DPMM_DATA 1 1 FIFO data 0x00000dca 1 RO uint32 b[31:0] - - -
REG_MMDP_CTRL 1 1 REG wr_usedw 0x00000dc8 1 RO uint32 b[31:0] - - -
- - - - wr_availw 0x00000dc9 1 RO uint32 b[31:0] - - -
REG_MMDP_DATA 1 1 FIFO data 0x00000dc6 1 WO uint32 b[31:0] - - -
REG_REMU 1 1 REG reconfigure 0x00000da0 1 WO uint32 b[31:0] - - -
- - - - param 0x00000da1 1 WO uint32 b[2:0] - - -
- - - - read_param 0x00000da2 1 WO uint32 b[0:0] - - -
- - - - write_param 0x00000da3 1 WO uint32 b[0:0] - - -
- - - - data_out 0x00000da4 1 RO uint32 b[23:0] - - -
- - - - data_in 0x00000da5 1 WO uint32 b[23:0] - - -
- - - - busy 0x00000da6 1 RO uint32 b[0:0] - - -
REG_HEATER 1 1 REG enable 0x00000020 25 RW uint32 b[31:0] - - -
REG_DIAG_BG_1GBE 1 1 REG enable 0x00000d90 1 RW uint32 b[0:0] - - -
- - - - enable_sync 0x00000d90 1 RW uint32 b[1:1] - - -
- - - - samples_per_packet 0x00000d91 1 RW uint32 b[31:0] - - -
- - - - blocks_per_sync 0x00000d92 1 RW uint32 b[31:0] - - -
- - - - gapsize 0x00000d93 1 RW uint32 b[31:0] - - -
- - - - mem_low_adrs 0x00000d94 1 RW uint32 b[31:0] - - -
- - - - mem_high_adrs 0x00000d95 1 RW uint32 b[31:0] - - -
- - - - bsn_init 0x00000d96 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000d97 - - - b[31:0] b[63:32] - -
RAM_DIAG_BG_1GBE 1 2 RAM data 0x00006000 32 RW uint32 b[31:0] - - 32
REG_DIAG_TX_SEQ_1GBE 1 2 REG control 0x00000dbc 1 RW uint32 b[2:0] - - 4
- - - - init 0x00000dbd 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00000dbe 1 RO uint32 b[31:0] - - -
- - - - modulo 0x00000dbf 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_1GBE 1 2 REG xon_stable 0x00000d20 1 RO uint32 b[0:0] - - 16
- - - - ready_stable 0x00000d20 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000d20 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00000d21 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00000d22 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00000d23 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00000d24 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000d25 1 RO uint32 b[31:0] - - -
- - - - bsn_first 0x00000d26 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00000d27 - - - b[31:0] b[63:32] - -
- - - - bsn_first_cycle_cnt 0x00000d28 1 RO uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_1GBE 1 2 REG sync_cnt 0x00000d00 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x00000d01 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_1GBE 1 2 RAM data 0x00006800 20 RW uint32 b[31:0] - - 32
REG_DIAG_TX_SEQ_1GBE 1 2 REG control 0x00000dbc 1 RW uint32 b[1:0] - - 8
- - - - result 0x00000dbd 1 RO uint32 b[1:0] - - -
- - - - rx_cnt 0x00000dbe 1 RO uint32 b[31:0] - - -
- - - - rx_sample 0x00000dbf 1 RO uint32 b[31:0] - - -
- - - - step_0 0x00000dc0 1 RW uint32 b[31:0] - - -
- - - - step_1 0x00000dc1 1 RW uint32 b[31:0] - - -
- - - - step_2 0x00000dc2 1 RW uint32 b[31:0] - - -
- - - - step_3 0x00000dc3 1 RW uint32 b[31:0] - - -
REG_DIAG_BG_10GBE 1 1 REG enable 0x00000d88 1 RW uint32 b[0:0] - - -
- - - - enable_sync 0x00000d88 1 RW uint32 b[1:1] - - -
- - - - samples_per_packet 0x00000d89 1 RW uint32 b[31:0] - - -
- - - - blocks_per_sync 0x00000d8a 1 RW uint32 b[31:0] - - -
- - - - gapsize 0x00000d8b 1 RW uint32 b[31:0] - - -
- - - - mem_low_adrs 0x00000d8c 1 RW uint32 b[31:0] - - -
- - - - mem_high_adrs 0x00000d8d 1 RW uint32 b[31:0] - - -
- - - - bsn_init 0x00000d8e 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000d8f - - - b[31:0] b[63:32] - -
RAM_DIAG_BG_10GBE 1 72 RAM data 0x00020000 1024 RW uint32 b[31:0] b[31:0] - 2048
- - - - - 0x00020001 - - - b[31:0] b[63:32] - -
REG_DIAG_TX_SEQ_10GBE 1 72 REG control 0x00000d50 1 RW uint32 b[2:0] - - 4
- - - - init 0x00000d51 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00000d52 1 RO uint32 b[31:0] - - -
- - - - modulo 0x00000d53 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_10GBE 1 72 REG xon_stable 0x00007000 1 RO uint32 b[0:0] - - 16
- - - - ready_stable 0x00007000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00007000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00007001 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00007002 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00007003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00007004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00007005 1 RO uint32 b[31:0] - - -
- - - - bsn_first 0x00007006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00007007 - - - b[31:0] b[63:32] - -
- - - - bsn_first_cycle_cnt 0x00007008 1 RO uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_10GBE 1 72 REG sync_cnt 0x00000040 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x00000041 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_10GBE 1 72 RAM data 0x00140000 900 RW uint32 b[31:0] b[31:0] - 2048
- - - - - 0x00140001 - - - b[31:0] b[63:32] - -
REG_DIAG_TX_SEQ_10GBE 1 72 REG control 0x00000d50 1 RW uint32 b[1:0] - - 8
- - - - result 0x00000d51 1 RO uint32 b[1:0] - - -
- - - - rx_cnt 0x00000d52 1 RO uint32 b[31:0] - - -
- - - - rx_sample 0x00000d53 1 RO uint32 b[31:0] - - -
- - - - step_0 0x00000d54 1 RW uint32 b[31:0] - - -
- - - - step_1 0x00000d55 1 RW uint32 b[31:0] - - -
- - - - step_2 0x00000d56 1 RW uint32 b[31:0] - - -
- - - - step_3 0x00000d57 1 RW uint32 b[31:0] - - -
REG_TR_10GBE_QSFP_RING 1 48 REG rx_transfer_control 0x00080000 1 RW uint32 b[0:0] - - 1
- - - - rx_transfer_status 0x00080001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00080002 1 RW uint32 b[0:0] - - -
- - - - rx_padcrc_control 0x00080040 1 RW uint32 b[1:0] - - -
- - - - rx_crccheck_control 0x00080080 1 RW uint32 b[1:0] - - -
- - - - rx_pktovrflow_error 0x000800c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x000800c1 - - - b[31:0] b[31:0] - -
- - - - rx_pktovrflow_etherstatsdropevents 0x000800c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x000800c3 - - - b[31:0] b[31:0] - -
- - - - rx_lane_decoder_preamble_control 0x00080100 1 RW uint32 b[0:0] - - -
- - - - rx_preamble_inserter_control 0x00080140 1 RW uint32 b[0:0] - - -
- - - - rx_frame_control 0x00080800 1 RW uint32 b[19:0] - - -
- - - - rx_frame_maxlength 0x00080801 1 RW uint32 b[15:0] - - -
- - - - rx_frame_addr0 0x00080802 1 RW uint32 b[15:0] - - -
- - - - rx_frame_addr1 0x00080803 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr0_0 0x00080804 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr0_1 0x00080805 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr1_0 0x00080806 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr1_1 0x00080807 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr2_0 0x00080808 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr2_1 0x00080809 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr3_0 0x0008080a 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr3_1 0x0008080b 1 RW uint32 b[15:0] - - -
- - - - rx_pfc_control 0x00080818 1 RW uint32 b[16:0] - - -
- - - - rx_stats_clr 0x00080c00 1 RW uint32 b[0:0] - - -
- - - - rx_stats_framesok 0x00080c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c03 - - - b[31:0] b[31:0] - -
- - - - rx_stats_frameserr 0x00080c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c05 - - - b[31:0] b[31:0] - -
- - - - rx_stats_framescrcerr 0x00080c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c07 - - - b[31:0] b[31:0] - -
- - - - rx_stats_octetsok 0x00080c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c09 - - - b[31:0] b[31:0] - -
- - - - rx_stats_pausemacctrl_frames 0x00080c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c0b - - - b[31:0] b[31:0] - -
- - - - rx_stats_iferrors 0x00080c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c0d - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicast_framesok 0x00080c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c0f - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicast_frameserr 0x00080c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c11 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicastframesok 0x00080c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c13 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicast_frameserr 0x00080c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c15 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcastframesok 0x00080c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c17 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcast_frameserr 0x00080c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c19 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatsoctets 0x00080c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c1b - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatspkts 0x00080c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c1d - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_undersizepkts 0x00080c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c1f - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_oversizepkts 0x00080c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c21 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts64octets 0x00080c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c23 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts65to127octets 0x00080c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c25 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts128to255octets 0x00080c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c27 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts256to511octets 0x00080c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c29 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts512to1023octets 0x00080c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c2b - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstat_pkts1024to1518octets 0x00080c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c2d - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts1519toxoctets 0x00080c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c2f - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_fragments 0x00080c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c31 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_jabbers 0x00080c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c33 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatscrcerr 0x00080c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c35 - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicastmacctrlframes 0x00080c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c37 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicastmac_ctrlframes 0x00080c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c39 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcastmac_ctrlframes 0x00080c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c3b - - - b[31:0] b[31:0] - -
- - - - rx_stats_pfcmacctrlframes 0x00080c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00080c3d - - - b[31:0] b[31:0] - -
- - - - tx_transfer_status 0x00081001 1 RO uint32 b[0:0] - - -
- - - - tx_padins_control 0x00081040 1 RW uint32 b[0:0] - - -
- - - - tx_crcins_control 0x00081080 1 RW uint32 b[1:0] - - -
- - - - tx_pktunderflow_error 0x000810c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x000810c1 - - - b[31:0] b[31:0] - -
- - - - tx_preamble_control 0x00081100 1 RW uint32 b[0:0] - - -
- - - - tx_pauseframe_control 0x00081140 1 RW uint32 b[1:0] - - -
- - - - tx_pauseframe_quanta 0x00081141 1 RW uint32 b[15:0] - - -
- - - - tx_pauseframe_enable 0x00081142 1 RW uint32 b[0:0] - - -
- - - - pfc_pause_quanta_0 0x00081180 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_1 0x00081181 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_2 0x00081182 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_3 0x00081183 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_4 0x00081184 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_5 0x00081185 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_6 0x00081186 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_7 0x00081187 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_0 0x00081190 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_1 0x00081191 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_2 0x00081192 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_3 0x00081193 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_4 0x00081194 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_5 0x00081195 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_6 0x00081196 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_7 0x00081197 1 RW uint32 b[31:0] - - -
- - - - tx_pfc_priority_enable 0x000811a0 1 RW uint32 b[7:0] - - -
- - - - tx_addrins_control 0x00081200 1 RW uint32 b[0:0] - - -
- - - - tx_addrins_macaddr0 0x00081201 1 RW uint32 b[31:0] - - -
- - - - tx_addrins_macaddr1 0x00081202 1 RW uint32 b[15:0] - - -
- - - - tx_frame_maxlength 0x00081801 1 RW uint32 b[15:0] - - -
- - - - tx_stats_clr 0x00081c00 1 RW uint32 b[0:0] - - -
- - - - tx_stats_framesok 0x00081c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c03 - - - b[31:0] b[31:0] - -
- - - - tx_stats_frameserr 0x00081c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c05 - - - b[31:0] b[31:0] - -
- - - - tx_stats_framescrcerr 0x00081c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c07 - - - b[31:0] b[31:0] - -
- - - - tx_stats_octetsok 0x00081c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c09 - - - b[31:0] b[31:0] - -
- - - - tx_stats_pausemacctrl_frames 0x00081c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c0b - - - b[31:0] b[31:0] - -
- - - - tx_stats_iferrors 0x00081c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c0d - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicast_framesok 0x00081c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c0f - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicast_frameserr 0x00081c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c11 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicastframesok 0x00081c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c13 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicast_frameserr 0x00081c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c15 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcastframesok 0x00081c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c17 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcast_frameserr 0x00081c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c19 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatsoctets 0x00081c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c1b - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatspkts 0x00081c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c1d - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_undersizepkts 0x00081c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c1f - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_oversizepkts 0x00081c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c21 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts64octets 0x00081c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c23 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts65to127octets 0x00081c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c25 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts128to255octets 0x00081c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c27 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts256to511octets 0x00081c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c29 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts512to1023octets 0x00081c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c2b - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstat_pkts1024to1518octets 0x00081c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c2d - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts1519toxoctets 0x00081c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c2f - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_fragments 0x00081c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c31 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_jabbers 0x00081c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c33 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatscrcerr 0x00081c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c35 - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicastmacctrlframes 0x00081c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c37 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicastmac_ctrlframes 0x00081c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c39 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcastmac_ctrlframes 0x00081c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00081c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00081c3d - - - b[31:0] b[31:0] - -
REG_ETH10G_QSFP_RING 1 48 REG tx_snk_out_xon 0x00000080 1 RO uint32 b[0:0] - - 1
- - - - xgmii_tx_ready 0x00000080 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x00000080 1 RO uint32 b[3:2] - - -
REG_TR_10GBE_BACK0 1 24 REG rx_transfer_control 0x00100000 1 RW uint32 b[0:0] - - 1
- - - - rx_transfer_status 0x00100001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00100002 1 RW uint32 b[0:0] - - -
- - - - rx_padcrc_control 0x00100040 1 RW uint32 b[1:0] - - -
- - - - rx_crccheck_control 0x00100080 1 RW uint32 b[1:0] - - -
- - - - rx_pktovrflow_error 0x001000c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x001000c1 - - - b[31:0] b[31:0] - -
- - - - rx_pktovrflow_etherstatsdropevents 0x001000c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x001000c3 - - - b[31:0] b[31:0] - -
- - - - rx_lane_decoder_preamble_control 0x00100100 1 RW uint32 b[0:0] - - -
- - - - rx_preamble_inserter_control 0x00100140 1 RW uint32 b[0:0] - - -
- - - - rx_frame_control 0x00100800 1 RW uint32 b[19:0] - - -
- - - - rx_frame_maxlength 0x00100801 1 RW uint32 b[15:0] - - -
- - - - rx_frame_addr0 0x00100802 1 RW uint32 b[15:0] - - -
- - - - rx_frame_addr1 0x00100803 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr0_0 0x00100804 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr0_1 0x00100805 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr1_0 0x00100806 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr1_1 0x00100807 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr2_0 0x00100808 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr2_1 0x00100809 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr3_0 0x0010080a 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr3_1 0x0010080b 1 RW uint32 b[15:0] - - -
- - - - rx_pfc_control 0x00100818 1 RW uint32 b[16:0] - - -
- - - - rx_stats_clr 0x00100c00 1 RW uint32 b[0:0] - - -
- - - - rx_stats_framesok 0x00100c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c03 - - - b[31:0] b[31:0] - -
- - - - rx_stats_frameserr 0x00100c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c05 - - - b[31:0] b[31:0] - -
- - - - rx_stats_framescrcerr 0x00100c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c07 - - - b[31:0] b[31:0] - -
- - - - rx_stats_octetsok 0x00100c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c09 - - - b[31:0] b[31:0] - -
- - - - rx_stats_pausemacctrl_frames 0x00100c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c0b - - - b[31:0] b[31:0] - -
- - - - rx_stats_iferrors 0x00100c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c0d - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicast_framesok 0x00100c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c0f - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicast_frameserr 0x00100c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c11 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicastframesok 0x00100c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c13 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicast_frameserr 0x00100c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c15 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcastframesok 0x00100c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c17 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcast_frameserr 0x00100c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c19 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatsoctets 0x00100c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c1b - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatspkts 0x00100c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c1d - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_undersizepkts 0x00100c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c1f - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_oversizepkts 0x00100c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c21 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts64octets 0x00100c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c23 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts65to127octets 0x00100c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c25 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts128to255octets 0x00100c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c27 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts256to511octets 0x00100c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c29 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts512to1023octets 0x00100c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c2b - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstat_pkts1024to1518octets 0x00100c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c2d - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts1519toxoctets 0x00100c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c2f - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_fragments 0x00100c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c31 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_jabbers 0x00100c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c33 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatscrcerr 0x00100c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c35 - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicastmacctrlframes 0x00100c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c37 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicastmac_ctrlframes 0x00100c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c39 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcastmac_ctrlframes 0x00100c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c3b - - - b[31:0] b[31:0] - -
- - - - rx_stats_pfcmacctrlframes 0x00100c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00100c3d - - - b[31:0] b[31:0] - -
- - - - tx_transfer_status 0x00101001 1 RO uint32 b[0:0] - - -
- - - - tx_padins_control 0x00101040 1 RW uint32 b[0:0] - - -
- - - - tx_crcins_control 0x00101080 1 RW uint32 b[1:0] - - -
- - - - tx_pktunderflow_error 0x001010c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x001010c1 - - - b[31:0] b[31:0] - -
- - - - tx_preamble_control 0x00101100 1 RW uint32 b[0:0] - - -
- - - - tx_pauseframe_control 0x00101140 1 RW uint32 b[1:0] - - -
- - - - tx_pauseframe_quanta 0x00101141 1 RW uint32 b[15:0] - - -
- - - - tx_pauseframe_enable 0x00101142 1 RW uint32 b[0:0] - - -
- - - - pfc_pause_quanta_0 0x00101180 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_1 0x00101181 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_2 0x00101182 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_3 0x00101183 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_4 0x00101184 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_5 0x00101185 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_6 0x00101186 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_7 0x00101187 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_0 0x00101190 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_1 0x00101191 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_2 0x00101192 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_3 0x00101193 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_4 0x00101194 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_5 0x00101195 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_6 0x00101196 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_7 0x00101197 1 RW uint32 b[31:0] - - -
- - - - tx_pfc_priority_enable 0x001011a0 1 RW uint32 b[7:0] - - -
- - - - tx_addrins_control 0x00101200 1 RW uint32 b[0:0] - - -
- - - - tx_addrins_macaddr0 0x00101201 1 RW uint32 b[31:0] - - -
- - - - tx_addrins_macaddr1 0x00101202 1 RW uint32 b[15:0] - - -
- - - - tx_frame_maxlength 0x00101801 1 RW uint32 b[15:0] - - -
- - - - tx_stats_clr 0x00101c00 1 RW uint32 b[0:0] - - -
- - - - tx_stats_framesok 0x00101c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c03 - - - b[31:0] b[31:0] - -
- - - - tx_stats_frameserr 0x00101c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c05 - - - b[31:0] b[31:0] - -
- - - - tx_stats_framescrcerr 0x00101c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c07 - - - b[31:0] b[31:0] - -
- - - - tx_stats_octetsok 0x00101c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c09 - - - b[31:0] b[31:0] - -
- - - - tx_stats_pausemacctrl_frames 0x00101c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c0b - - - b[31:0] b[31:0] - -
- - - - tx_stats_iferrors 0x00101c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c0d - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicast_framesok 0x00101c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c0f - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicast_frameserr 0x00101c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c11 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicastframesok 0x00101c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c13 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicast_frameserr 0x00101c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c15 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcastframesok 0x00101c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c17 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcast_frameserr 0x00101c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c19 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatsoctets 0x00101c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c1b - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatspkts 0x00101c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c1d - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_undersizepkts 0x00101c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c1f - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_oversizepkts 0x00101c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c21 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts64octets 0x00101c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c23 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts65to127octets 0x00101c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c25 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts128to255octets 0x00101c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c27 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts256to511octets 0x00101c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c29 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts512to1023octets 0x00101c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c2b - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstat_pkts1024to1518octets 0x00101c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c2d - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts1519toxoctets 0x00101c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c2f - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_fragments 0x00101c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c31 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_jabbers 0x00101c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c33 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatscrcerr 0x00101c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c35 - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicastmacctrlframes 0x00101c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c37 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicastmac_ctrlframes 0x00101c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c39 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcastmac_ctrlframes 0x00101c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00101c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00101c3d - - - b[31:0] b[31:0] - -
REG_ETH10G_BACK0 1 24 REG tx_snk_out_xon 0x00000c80 1 RO uint32 b[0:0] - - 1
- - - - xgmii_tx_ready 0x00000c80 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x00000c80 1 RO uint32 b[3:2] - - -
REG_IO_DDR_MB_I 1 1 REG burstbegin 0x00160000 1 WO uint32 b[0:0] - - -
- - - - wr_not_rd 0x00160001 1 WO uint32 b[0:0] - - -
- - - - done 0x00160002 1 RO uint32 b[0:0] - - -
- - - - address 0x00160005 1 WO uint32 b[31:0] - - -
- - - - burstsize 0x00160006 1 WO uint32 b[31:0] - - -
- - - - flush 0x00160007 1 RW uint32 b[0:0] - - -
REG_DIAG_TX_SEQ_DDR_MB_I 1 1 REG control 0x00000db8 1 RW uint32 b[2:0] - - -
- - - - init 0x00000db9 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00000dba 1 RO uint32 b[31:0] - - -
- - - - modulo 0x00000dbb 1 RW uint32 b[31:0] - - -
REG_DIAG_RX_SEQ_DDR_MB_I 1 1 REG control 0x00000d78 1 RW uint32 b[1:0] - - -
- - - - result 0x00000d79 1 RO uint32 b[1:0] - - -
- - - - rx_cnt 0x00000d7a 1 RO uint32 b[31:0] - - -
- - - - rx_sample 0x00000d7b 1 RO uint32 b[31:0] - - -
- - - - step_0 0x00000d7c 1 RW uint32 b[31:0] - - -
- - - - step_1 0x00000d7d 1 RW uint32 b[31:0] - - -
- - - - step_2 0x00000d7e 1 RW uint32 b[31:0] - - -
- - - - step_3 0x00000d7f 1 RW uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_DDR_MB_I 1 1 REG sync_cnt 0x00000cc0 1 RO uint32 b[31:0] - - -
- - - - word_cnt 0x00000cc1 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_DDR_MB_I 1 1 RAM data 0x00003800 1024 RW uint32 b[31:0] - - -
REG_IO_DDR_MB_II 1 1 REG burstbegin 0x00010000 1 WO uint32 b[0:0] - - -
- - - - wr_not_rd 0x00010001 1 WO uint32 b[0:0] - - -
- - - - done 0x00010002 1 RO uint32 b[0:0] - - -
- - - - address 0x00010005 1 WO uint32 b[31:0] - - -
- - - - burstsize 0x00010006 1 WO uint32 b[31:0] - - -
- - - - flush 0x00010007 1 RW uint32 b[0:0] - - -
REG_DIAG_TX_SEQ_DDR_MB_II 1 1 REG control 0x00000db4 1 RW uint32 b[2:0] - - -
- - - - init 0x00000db5 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00000db6 1 RO uint32 b[31:0] - - -
- - - - modulo 0x00000db7 1 RW uint32 b[31:0] - - -
REG_DIAG_RX_SEQ_DDR_MB_II 1 1 REG control 0x00000d70 1 RW uint32 b[1:0] - - -
- - - - result 0x00000d71 1 RO uint32 b[1:0] - - -
- - - - rx_cnt 0x00000d72 1 RO uint32 b[31:0] - - -
- - - - rx_sample 0x00000d73 1 RO uint32 b[31:0] - - -
- - - - step_0 0x00000d74 1 RW uint32 b[31:0] - - -
- - - - step_1 0x00000d75 1 RW uint32 b[31:0] - - -
- - - - step_2 0x00000d76 1 RW uint32 b[31:0] - - -
- - - - step_3 0x00000d77 1 RW uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_DDR_MB_II 1 1 REG sync_cnt 0x00000c20 1 RO uint32 b[31:0] - - -
- - - - word_cnt 0x00000c21 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_DDR_MB_II 1 1 RAM data 0x00003000 1024 RW uint32 b[31:0] - - -
PIO_JESD_CTRL 1 1 REG enable 0x00000c02 1 RW uint32 b[30:0] - - -
- - - - reset 0x00000c02 1 RW uint32 b[31:31] - - -
JESD204B 1 12 REG rx_dll_ctrl 0x00002014 1 RW uint32 b[16:0] - - 256
- - - - rx_syncn_sysref_ctrl 0x00002015 1 RW uint32 b[24:0] - - -
- - - - rx_csr_sysref_always_on 0x00002015 1 RW uint32 b[1:1] - - -
- - - - rx_csr_rbd_offset 0x00002015 1 RW uint32 b[10:3] - - -
- - - - rx_csr_lmfc_offset 0x00002015 1 RW uint32 b[19:12] - - -
- - - - rx_err0 0x00002018 1 RW uint32 b[8:0] - - -
- - - - rx_err1 0x00002019 1 RW uint32 b[9:0] - - -
- - - - csr_dev_syncn 0x00002020 1 RO uint32 b[0:0] - - -
- - - - csr_rbd_count 0x00002020 1 RO uint32 b[10:3] - - -
- - - - rx_status1 0x00002021 1 RW uint32 b[23:0] - - -
- - - - rx_status2 0x00002022 1 RW uint32 b[23:0] - - -
- - - - rx_status3 0x00002023 1 RW uint32 b[7:0] - - -
- - - - rx_ilas_csr_l 0x00002025 1 RW uint32 b[4:0] - - -
- - - - rx_ilas_csr_f 0x00002025 1 RW uint32 b[15:8] - - -
- - - - rx_ilas_csr_k 0x00002025 1 RW uint32 b[20:16] - - -
- - - - rx_ilas_csr_m 0x00002025 1 RW uint32 b[31:24] - - -
- - - - rx_ilas_csr_n 0x00002026 1 RW uint32 b[4:0] - - -
- - - - rx_ilas_csr_cs 0x00002026 1 RW uint32 b[7:6] - - -
- - - - rx_ilas_csr_np 0x00002026 1 RW uint32 b[12:8] - - -
- - - - rx_ilas_csr_subclassv 0x00002026 1 RW uint32 b[15:13] - - -
- - - - rx_ilas_csr_s 0x00002026 1 RW uint32 b[20:16] - - -
- - - - rx_ilas_csr_jesdv 0x00002026 1 RW uint32 b[23:21] - - -
- - - - rx_ilas_csr_cf 0x00002026 1 RW uint32 b[28:24] - - -
- - - - rx_ilas_csr_hd 0x00002026 1 RW uint32 b[31:31] - - -
- - - - rx_status4 0x0000203c 1 RW uint32 b[15:0] - - -
- - - - rx_status5 0x0000203d 1 RW uint32 b[15:0] - - -
- - - - rx_status6 0x0000203e 1 RW uint32 b[23:0] - - -
- - - - rx_status7 0x0000203f 1 RO uint32 b[31:0] - - -
REG_BSN_SOURCE 1 1 REG dp_on 0x00000db0 1 RW uint32 b[0:0] - - -
- - - - dp_on_pps 0x00000db0 1 RW uint32 b[1:1] - - -
- - - - nof_block_per_sync 0x00000db1 1 RW uint32 b[31:0] - - -
- - - - bsn 0x00000db2 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000db3 - - - b[31:0] b[63:32] - -
REG_BSN_MONITOR_INPUT 1 12 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - 16
- - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00000102 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
- - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00000107 - - - b[31:0] b[63:32] - -
- - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00001000 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x00001001 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 131072 RW uint32 b[31:0] b[15:0] - 131072
\ No newline at end of file
......@@ -31,22 +31,22 @@ peripherals:
1 = calc, uses WG buffer waveform to output sinus with ampl * sin(freq * t + phase
2 = repeat, outputs WG buffer waveform repeatedly
3 = single, outputs WG buffer waveform once"
address_offset: 0x0
address_offset: 0 * MM_BUS_SIZE
bit_offset: 0
mm_width: 8
- - field_name: phase
field_description: "Phase of WG sinus, phase = int('phase in degrees' * 2**width / 360)."
address_offset: 0x4
address_offset: 1 * MM_BUS_SIZE
bit_offset: 0
mm_width: 16
- - field_name: freq
field_description: "Frequency of WG sinus, freq = int('frequency in range 0 to 1' * f_adc * 2**width), where f_adc is sample frequency in Hz."
address_offset: 0x8
address_offset: 2 * MM_BUS_SIZE
bit_offset: 0
mm_width: 31
- - field_name: ampl
field_description: "Amplitude of WG sinus, ampl = int('amplitude in range 0 to 2' * 2**(width-1), where amplitude > 1 causes clipping."
address_offset: 0xC
address_offset: 3 * MM_BUS_SIZE
bit_offset: 0
mm_width: 17
# MM port for mms_diag_wg_wideband.vhd
......@@ -59,7 +59,7 @@ peripherals:
- - field_name: data
field_description: "Waveform default is one sinus period (diag_sin_1024x18.hex)."
number_of_fields: 1024 # = 2**c_wg_buf_addr_w in node_adc_input_and_timing.vhd
address_offset: 0x0
address_offset: 0 * MM_BUS_SIZE
mm_width: 18 # = c_wg_buf_dat_w in node_adc_input_and_timing.vhd
- peripheral_name: diag_data_buffer # pi_diag_data_buffer.py
......@@ -80,11 +80,11 @@ peripherals:
fields:
- - field_name: sync_cnt
field_description: "Number of times the DB has been written."
address_offset: 0x0
address_offset: 0 * MM_BUS_SIZE
access_mode: RO
- - field_name: word_cnt
field_description: "Number data words in the DB."
address_offset: 0x4
address_offset: 1 * MM_BUS_SIZE
access_mode: RO
# MM port for mms_diag_data_buffer.vhd
- mm_port_name: RAM_DIAG_DB
......@@ -96,6 +96,170 @@ peripherals:
- - field_name: data
field_description: ""
number_of_fields: g_nof_data
address_offset: 0x0
mm_width: g_data_w
address_offset: 0 * MM_BUS_SIZE
user_width: g_data_w
- peripheral_name: diag_block_gen # pi_diag_block_gen.py
peripheral_description: "Block generator (BG)"
parameters:
# Parameters of mms_diag_block_gen.vhd
- { name: g_nof_streams, value: 1 }
- { name: g_buf_dat_w, value: 16 }
- { name: g_buf_addr_w, value: 7 }
mm_ports:
# MM port for mms_diag_block_gen.vhd
- mm_port_name: REG_DIAG_BG
mm_port_type: REG
mm_port_span: 8 * MM_BUS_SIZE
mm_port_description: "Block generator control."
number_of_mm_ports: 1
fields:
- - field_name: enable
field_description: "Starts the block generator."
address_offset: 0 * MM_BUS_SIZE
bit_offset: 0
mm_width: 1
- - field_name: enable_sync
field_description: "Starts the block generator at the next sync pulse when enable is set to 1."
address_offset: 0 * MM_BUS_SIZE
bit_offset: 1
mm_width: 1
- - field_name: samples_per_packet
field_description: "Number of samples per packet."
address_offset: 1 * MM_BUS_SIZE
- - field_name: blocks_per_sync
field_description: "Number blocks per sync interval."
address_offset: 2 * MM_BUS_SIZE
- - field_name: gapsize
field_description: "The gap size between blocks in clock cycles."
address_offset: 3 * MM_BUS_SIZE
- - field_name: mem_low_adrs
field_description: "Start address of memory to use for block generator"
address_offset: 4 * MM_BUS_SIZE
- - field_name: mem_high_adrs
field_description: "End address of memory to use for block generator."
address_offset: 5 * MM_BUS_SIZE
- - field_name: bsn_init
field_description: "Initial BSN."
address_offset: 6 * MM_BUS_SIZE
user_width: 64
radix: uint64
# MM port for mms_diag_block_gen.vhd
- mm_port_name: RAM_DIAG_BG
mm_port_type: RAM
mm_port_span: ceil_pow2( 2**g_buf_addr_w * ceil_div(g_buf_dat_w, c_word_w)) * MM_BUS_SIZE
mm_port_description: "Block generator buffer memory, contains the data patterns to be generated."
number_of_mm_ports: g_nof_streams
fields:
- - field_name: data
field_description: "Block generator buffer memory."
number_of_fields: 2**g_buf_addr_w
address_offset: 0 * MM_BUS_SIZE
user_width: g_buf_dat_w
- peripheral_name: diag_tx_seq # pi_diag_tx_seq.py
peripheral_description: "TX test sequence"
parameters:
# Parameters of mms_diag_tx_seq.vhd
- { name: g_nof_streams, value: 1 }
- { name: g_mm_broadcast, value: False }
mm_ports:
# MM port for mms_diag_tx_seq.vhd
- mm_port_name: REG_DIAG_TX_SEQ
mm_port_type: REG
mm_port_span: 4 * MM_BUS_SIZE
mm_port_description: "TX test sequence control."
number_of_mm_ports: sel_a_b(g_mm_broadcast, 1, g_nof_streams)
fields:
- - field_name: control
field_description: |
"Control register containing diag_dc = [2], diag_sel = [1], diag_en = [0].
diag_en
'0' = init and disable output sequence
'1' = enable output sequence
diag_sel
'0' = generate PSRG data
'1' = generate CNTR data
diag_dc
'0' = Output sequence data (as selected by diag_sel)
'1' = Output constant data (value as set by diag_init)"
address_offset: 0 * MM_BUS_SIZE
mm_width: 3
- - field_name: init
field_description: "Initial data value."
address_offset: 1 * MM_BUS_SIZE
- - field_name: tx_cnt
field_description: |
"Counts the number of valid output data that was transmitted on stream 0
since diag_en went active. An incrementing tx_cnt shows that data is
being transmitted."
address_offset: 2 * MM_BUS_SIZE
access_mode: RO
- - field_name: modulo
field_description: "A modulo can be used with CNTR data which results in a sequence with values of (cnt MOD modulo)"
address_offset: 3 * MM_BUS_SIZE
- peripheral_name: diag_rx_seq # pi_diag_rx_seq.py
peripheral_description: "RX test sequence"
parameters:
# Parameters of mms_diag_rx_seq.vhd
- { name: g_nof_streams, value: 1 }
mm_ports:
# MM port for mms_diag_rx_seq.vhd
- mm_port_name: REG_DIAG_RX_SEQ
mm_port_type: REG
mm_port_span: 8 * MM_BUS_SIZE
mm_port_description: "RX test sequence control."
number_of_mm_ports: g_nof_streams
fields:
- - field_name: control
field_description: |
"Control register containing diag_sel = [1], diag_en = [0].
diag_en
'0' = stop and reset input sequence verification
'1' = enable input sequence verification
diag_sel
'0' = verify PSRG data
'1' = verify CNTR data"
address_offset: 0 * MM_BUS_SIZE
mm_width: 2
- - field_name: result
field_description: |
"result register containing res_val_n = [1], res_ok_n = [0].
res_val_n
'0' = No valid data is being received.
'1' = At least two valid data have been received.
res_ok_n
'0' = All data that has been received so far is correct.
'1' = At least 1 data word was received with errors"
address_offset: 1 * MM_BUS_SIZE
access_mode: RO
mm_width: 2
- - field_name: rx_cnt
field_description: |
"the number of valid input data that was received since diag_en
went active. An incrementing rx_cnt shows that data is being received."
address_offset: 2 * MM_BUS_SIZE
access_mode: RO
- - field_name: rx_sample
field_description: |
"The rx_sample keeps the last valid in_dat value. When diag_en='0' it is
reset to 0. Reading rx_sample via MM gives an impression of the valid
in_dat activity."
address_offset: 3 * MM_BUS_SIZE
access_mode: RO
- - field_name: step_0
field_description: "step_0 = diag_steps_arr[0] which defines the allowed COUNTER increment values"
address_offset: 4 * MM_BUS_SIZE
- - field_name: step_1
field_description: "step_1 = diag_steps_arr[1] which defines the allowed COUNTER increment values"
address_offset: 5 * MM_BUS_SIZE
- - field_name: step_2
field_description: "step_2 = diag_steps_arr[2] which defines the allowed COUNTER increment values"
address_offset: 6 * MM_BUS_SIZE
- - field_name: step_3
field_description: "step_3 = diag_steps_arr[3] which defines the allowed COUNTER increment values"
address_offset: 7 * MM_BUS_SIZE
schema_name: args
schema_version: 1.0
schema_type: peripheral
hdl_library_name: util
hdl_library_description: "Util Heater."
peripherals:
- peripheral_name: heater # pi_heater.py
peripheral_description: "Heater component, see util_heater.vhd"
parameters:
- { name: c_nof_mac4_max, value: 800 }
- { name: c_reg_nof_words, value: c_nof_mac4_max // 32 } # = 25
mm_ports:
# MM port for util_heater.vhd
- mm_port_name: REG_HEATER
mm_port_type: REG
mm_port_span: ceil_pow2(25) * MM_BUS_SIZE #ceil_pow2(c_reg_nof_words) * MM_BUS_SIZE
mm_port_description: "Heater control."
fields:
- - field_name: enable
field_description: |
"The heater elements can be enabled or disabled via this MM register.
Each heater element consists of a MAC4. A MAC4 uses 4 18x18 multipliers.
The MM register allows enabling 0, 1, more or all MAC4 under SW control.
In this way it is possible to vary the power consumption during run time."
number_of_fields: 25 #c_reg_nof_words
address_offset: 0x0
schema_name: args
schema_version: 1.0
schema_type: peripheral
hdl_library_name: ddr
hdl_library_description: "Double data rate memory"
peripherals:
- peripheral_name: io_ddr # pi_io_ddr.py
peripheral_description: "DDR controller"
mm_ports:
# MM port for io_ddr_reg.vhd
- mm_port_name: REG_IO_DDR
mm_port_type: REG
mm_port_span: 8 * MM_BUS_SIZE
mm_port_description: "DDR controller registers."
number_of_mm_ports: 1
fields:
- - field_name: reg_io_ddr
field_description: |
"IO DDR status bits concatenated:
ctlr_tech_mosi.wr & ctlr_tech_miso.rdval & ctlr_tech_miso.cal_fail & ctlr_tech_miso.cal_ok
ctlr_rst_out_i & ctlr_wr_flush_en & ctlr_tech_miso.waitrequest_n & ctlr_tech_miso.done"
address_offset: 0 * MM_BUS_SIZE
access_mode: RO
- - field_name: reg_rd_fifo_used
field_description: "Read FIFO fill level."
address_offset: 1 * MM_BUS_SIZE
access_mode: RO
- - field_name: reg_wr_fifo_used
field_description: "Write FIFO fill level."
address_offset: 2 * MM_BUS_SIZE
access_mode: RO
- - field_name: reg_fifo_full
field_description: "Read FIFO full bit & Write FIFO full bit"
address_offset: 3 * MM_BUS_SIZE
access_mode: RO
- - field_name: reg_burstbegin
field_description: "Start write or read access to DDR when reg_burstbegin = 1."
address_offset: 8 * MM_BUS_SIZE
access_mode: WO
- - field_name: reg_wr_not_rd
field_description: "Set read / write mode. reg_wr_not_rd = 1 = write mode, reg_wr_not_rd = 0 = read mode."
address_offset: 9 * MM_BUS_SIZE
access_mode: WO
- - field_name: reg_done
field_description: "reg_done = 1 when memory access is finished."
address_offset: 10 * MM_BUS_SIZE
access_mode: RO
- - field_name: reg_address
field_description: "Start address for memory access."
address_offset: 13 * MM_BUS_SIZE
access_mode: WO
- - field_name: reg_burstsize
field_description: "Access size for memory access"
address_offset: 14 * MM_BUS_SIZE
access_mode: WO
- - field_name: reg_flush
field_description: |
"Flush the write FIFO
The user input to the write FIFO sohuld be off. Internally the method waits sufficient us to
ensure that the write FIFO is read empty."
address_offset: 15 * MM_BUS_SIZE
schema_name: args
schema_version: 1.0
schema_type: peripheral
hdl_library_name: tr_10GbE # copy of nw_10GbE.
hdl_library_description: "Network peripherals for 10GbE."
peripherals:
- peripheral_name: tr_10GbE_unb2legacy # pi_nw_10GbE_unb2legacy.py / pi_tr_10GbE.py / pi_tr_10GbE_unb2.py
peripheral_description: |
"M&C of Intel Low Latency (LL) 10GbE MAC control status register (CSR) see [1]
The LL 10GbE MAC is used with the legacy address map option of the old 10GbE MAC, see [2], this implies:
. Some registers have a different address offset in [1] and [2]
. The 36 bit registers are stored at word 0 = [31:0] and word 1 = [3:0] = [35:32] in [1], but in [2]
they are stored with their 4 most significant bits first and their 32 least significant bits last, so
with word 0 = [3:0] = [35:32] and word 1 = [31:0].
Here the address map and 36 bit word order from [2] are used.
[1] LL 10GbE MAC, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_32b_10g_ethernet_mac.pdf
[2] Legacy 10GbE MAC, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/10gbps_mac.pdf
"
parameters:
# Parameters of nw_10GbE.vhd / tr_10GbE.vhd
- { name: g_nof_macs, value: 1 }
mm_ports:
# MM port for reg_mac_mosi = mac_mosi in ip_arria10_e1sg_eth_10g.vhd
# Use tr_10GbE_word_to_byte_address.py to derive the byte addresses from the word addresses
- mm_port_name: REG_TR_10GBE_MAC
mm_port_type: REG
mm_port_description: "MAC registers"
number_of_mm_ports: g_nof_macs
fields:
- - {field_name: rx_transfer_control, mm_width: 1, access_mode: RW, address_offset: 0x0000 } # = 0x0000
- - {field_name: rx_transfer_status, mm_width: 1, access_mode: RO, address_offset: 0x0004 } # = 0x0001
- - {field_name: rx_padcrc_control, mm_width: 2, access_mode: RW, address_offset: 0x0100 } # = 0x0040
- - {field_name: rx_crccheck_control, mm_width: 2, access_mode: RW, address_offset: 0x0200 } # = 0x0080
- - {field_name: rx_pktovrflow_error, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x0300 } # = 0x00C0
- - {field_name: rx_pktovrflow_etherStatsDropEvents, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x0308 } # = 0x00C2
- - {field_name: rx_lane_decoder_preamble_control, mm_width: 1, access_mode: RW, address_offset: 0x0400 } # = 0x0100
- - {field_name: rx_preamble_inserter_control, mm_width: 1, access_mode: RW, address_offset: 0x0500 } # = 0x0140
- - {field_name: rx_frame_control, mm_width: 20, access_mode: RW, address_offset: 0x2000 } # = 0x0800
- - {field_name: rx_frame_maxlength, mm_width: 16, access_mode: RW, address_offset: 0x2004 } # = 0x0801
- - {field_name: rx_frame_addr0, mm_width: 16, access_mode: RW, address_offset: 0x2008 } # = 0x0802
- - {field_name: rx_frame_addr1, mm_width: 16, access_mode: RW, address_offset: 0x200c } # = 0x0803
- - {field_name: rx_frame_spaddr0_0, mm_width: 16, access_mode: RW, address_offset: 0x2010 } # = 0x0804
- - {field_name: rx_frame_spaddr0_1, mm_width: 16, access_mode: RW, address_offset: 0x2014 } # = 0x0805
- - {field_name: rx_frame_spaddr1_0, mm_width: 16, access_mode: RW, address_offset: 0x2018 } # = 0x0806
- - {field_name: rx_frame_spaddr1_1, mm_width: 16, access_mode: RW, address_offset: 0x201c } # = 0x0807
- - {field_name: rx_frame_spaddr2_0, mm_width: 16, access_mode: RW, address_offset: 0x2020 } # = 0x0808
- - {field_name: rx_frame_spaddr2_1, mm_width: 16, access_mode: RW, address_offset: 0x2024 } # = 0x0809
- - {field_name: rx_frame_spaddr3_0, mm_width: 16, access_mode: RW, address_offset: 0x2028 } # = 0x080A
- - {field_name: rx_frame_spaddr3_1, mm_width: 16, access_mode: RW, address_offset: 0x202c } # = 0x080B
- - {field_name: rx_pfc_control, mm_width: 17, access_mode: RW, address_offset: 0x2060 } # = 0x0818
- - {field_name: tx_transfer_control, mm_width: 1, access_mode: RW, address_offset: 0x4000 } # = 0x1000
- - {field_name: tx_transfer_status, mm_width: 1, access_mode: RO, address_offset: 0x4004 } # = 0x1001
- - {field_name: tx_padins_control, mm_width: 1, access_mode: RW, address_offset: 0x4100 } # = 0x1040
- - {field_name: tx_crcins_control, mm_width: 2, access_mode: RW, address_offset: 0x4200 } # = 0x1080
- - {field_name: tx_pktunderflow_error, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x4300 } # = 0x10C0
- - {field_name: tx_preamble_control, mm_width: 1, access_mode: RW, address_offset: 0x4400 } # = 0x1100
- - {field_name: tx_pauseframe_control, mm_width: 2, access_mode: RW, address_offset: 0x4500 } # = 0x1140
- - {field_name: tx_pauseframe_quanta, mm_width: 16, access_mode: RW, address_offset: 0x4504 } # = 0x1141
- - {field_name: tx_pauseframe_enable, mm_width: 1, access_mode: RW, address_offset: 0x4508 } # = 0x1142
# Altera is unclear about the width of the quanta registers. Assuming 32 bits, where bits 16:31 are reserved:
- - {field_name: pfc_pause_quanta_0, mm_width: 32, access_mode: RW, address_offset: 0x4600 } # = 0x1180
- - {field_name: pfc_pause_quanta_1, mm_width: 32, access_mode: RW, address_offset: 0x4604 } # = 0x1181
- - {field_name: pfc_pause_quanta_2, mm_width: 32, access_mode: RW, address_offset: 0x4608 } # = 0x1182
- - {field_name: pfc_pause_quanta_3, mm_width: 32, access_mode: RW, address_offset: 0x460c } # = 0x1183
- - {field_name: pfc_pause_quanta_4, mm_width: 32, access_mode: RW, address_offset: 0x4610 } # = 0x1184
- - {field_name: pfc_pause_quanta_5, mm_width: 32, access_mode: RW, address_offset: 0x4614 } # = 0x1185
- - {field_name: pfc_pause_quanta_6, mm_width: 32, access_mode: RW, address_offset: 0x4618 } # = 0x1186
- - {field_name: pfc_pause_quanta_7, mm_width: 32, access_mode: RW, address_offset: 0x461c } # = 0x1187
- - {field_name: pfc_holdoff_quanta_0, mm_width: 32, access_mode: RW, address_offset: 0x4640 } # = 0x1190
- - {field_name: pfc_holdoff_quanta_1, mm_width: 32, access_mode: RW, address_offset: 0x4644 } # = 0x1191
- - {field_name: pfc_holdoff_quanta_2, mm_width: 32, access_mode: RW, address_offset: 0x4648 } # = 0x1192
- - {field_name: pfc_holdoff_quanta_3, mm_width: 32, access_mode: RW, address_offset: 0x464c } # = 0x1193
- - {field_name: pfc_holdoff_quanta_4, mm_width: 32, access_mode: RW, address_offset: 0x4650 } # = 0x1194
- - {field_name: pfc_holdoff_quanta_5, mm_width: 32, access_mode: RW, address_offset: 0x4654 } # = 0x1195
- - {field_name: pfc_holdoff_quanta_6, mm_width: 32, access_mode: RW, address_offset: 0x4658 } # = 0x1196
- - {field_name: pfc_holdoff_quanta_7, mm_width: 32, access_mode: RW, address_offset: 0x465c } # = 0x1197
- - {field_name: tx_pfc_priority_enable, mm_width: 8, access_mode: RW, address_offset: 0x4680 } # = 0x11A0
- - {field_name: tx_addrins_control, mm_width: 1, access_mode: RW, address_offset: 0x4800 } # = 0x1200
- - {field_name: tx_addrins_macaddr0, mm_width: 32, access_mode: RW, address_offset: 0x4804 } # = 0x1201
- - {field_name: tx_addrins_macaddr1, mm_width: 16, access_mode: RW, address_offset: 0x4808 } # = 0x1202
- - {field_name: tx_frame_maxlength, mm_width: 16, access_mode: RW, address_offset: 0x6004 } # = 0x1801
- - {field_name: rx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x3000 } # = 0x0C00
- - {field_name: tx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x7000 } # = 0x1C00
- - {field_name: rx_stats_framesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3008 } # = 0x0C02
- - {field_name: tx_stats_framesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7008 } # = 0x1C02
- - {field_name: rx_stats_framesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3010 } # = 0x0C04
- - {field_name: tx_stats_framesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7010 } # = 0x1C04
- - {field_name: rx_stats_framesCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3018 } # = 0x0C06
- - {field_name: tx_stats_framesCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7018 } # = 0x1C06
- - {field_name: rx_stats_octetsOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3020 } # = 0x0C08
- - {field_name: tx_stats_octetsOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7020 } # = 0x1C08
- - {field_name: rx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3028 } # = 0x0C0A
- - {field_name: tx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7028 } # = 0x1C0A
- - {field_name: rx_stats_ifErrors, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3030 } # = 0x0C0C
- - {field_name: tx_stats_ifErrors, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7030 } # = 0x1C0C
- - {field_name: rx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3038 } # = 0x0C0E
- - {field_name: tx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7038 } # = 0x1C0E
- - {field_name: rx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3040 } # = 0x0C10
- - {field_name: tx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7040 } # = 0x1C10
- - {field_name: rx_stats_multicastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3048 } # = 0x0C12
- - {field_name: tx_stats_multicastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7048 } # = 0x1C12
- - {field_name: rx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3050 } # = 0x0C14
- - {field_name: tx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7050 } # = 0x1C14
- - {field_name: rx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3058 } # = 0x0C16
- - {field_name: tx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7058 } # = 0x1C16
- - {field_name: rx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3060 } # = 0x0C18
- - {field_name: tx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7060 } # = 0x1C18
- - {field_name: rx_stats_etherStatsOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3068 } # = 0x0C1A
- - {field_name: tx_stats_etherStatsOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7068 } # = 0x1C1A
- - {field_name: rx_stats_etherStatsPkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3070 } # = 0x0C1C
- - {field_name: tx_stats_etherStatsPkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7070 } # = 0x1C1C
- - {field_name: rx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3078 } # = 0x0C1E
- - {field_name: tx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7078 } # = 0x1C1E
- - {field_name: rx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3080 } # = 0x0C20
- - {field_name: tx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7080 } # = 0x1C20
- - {field_name: rx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3088 } # = 0x0C22
- - {field_name: tx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7088 } # = 0x1C22
- - {field_name: rx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3090 } # = 0x0C24
- - {field_name: tx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7090 } # = 0x1C24
- - {field_name: rx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3098 } # = 0x0C26
- - {field_name: tx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7098 } # = 0x1C26
- - {field_name: rx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30a0 } # = 0x0C28
- - {field_name: tx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70a0 } # = 0x1C28
- - {field_name: rx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30a8 } # = 0x0C2A
- - {field_name: tx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70a8 } # = 0x1C2A
- - {field_name: rx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30b0 } # = 0x0C2C
- - {field_name: tx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70b0 } # = 0x1C2C
- - {field_name: rx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30b8 } # = 0x0C2E
- - {field_name: tx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70b8 } # = 0x1C2E
- - {field_name: rx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30c0 } # = 0x0C30
- - {field_name: tx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70c0 } # = 0x1C30
- - {field_name: rx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30c8 } # = 0x0C32
- - {field_name: tx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70c8 } # = 0x1C32
- - {field_name: rx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30d0 } # = 0x0C34
- - {field_name: tx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70d0 } # = 0x1C34
- - {field_name: rx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30d8 } # = 0x0C36
- - {field_name: tx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70d8 } # = 0x1C36
- - {field_name: rx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30e0 } # = 0x0C38
- - {field_name: tx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70e0 } # = 0x1C38
- - {field_name: rx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30e8 } # = 0x0C3A
- - {field_name: tx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70e8 } # = 0x1C3A
- - {field_name: rx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30f0 } # = 0x0C3C
- - {field_name: tx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70f0 } # = 0x1C3C
- peripheral_name: tr_10GbE_eth10g # pi_nw_10GbE_eth10g.py / pi_10GbE.py
peripheral_description: "10GbE link status register"
parameters:
# Parameters of nw_10GbE.vhd / tr_10GbE.vhd
- { name: g_nof_macs, value: 1 }
mm_ports:
# MM port for reg_eth10g_mosi in ip_arria10_e1sg_eth_10g.vhd / common_reg_r_w_dc.vhd
- mm_port_name: REG_TR_10GBE_ETH10G
mm_port_type: REG
mm_port_description: ""
number_of_mm_ports: g_nof_macs
fields:
- - field_name: tx_snk_out_xon
field_description: ""
address_offset: 0x0
mm_width: 1
bit_offset: 0
access_mode: RO
- - field_name: xgmii_tx_ready
field_description: ""
address_offset: 0x0
mm_width: 1
bit_offset: 1
access_mode: RO
- - field_name: xgmii_link_status
field_description: ""
address_offset: 0x0
mm_width: 2
bit_offset: 2
access_mode: RO
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