- Added dp_sync_checker and dp_packet_merge

- Removed functionality for sync_ok detection. 

libraries/base/reorder/src/vhdl/reorder_transpose.vhd

@@ -132,15 +132,21 @@ ARCHITECTURE str OF reorder_transpose IS
   CONSTANT c_nof_ch_in        : NATURAL  := g_frame_size_in*g_reorder_seq.rd_chunksize;
   CONSTANT c_nof_ch_sel       : NATURAL  := c_nof_ch_in;
                                          
-  CONSTANT c_cnt_sop_w        : NATURAL  := ceil_log2(g_nof_blk_per_sync)+1;
-
   CONSTANT c_ctlr_data_w      : NATURAL := func_tech_ddr_ctlr_data_w(g_tech_ddr);
   CONSTANT c_data_w_ratio     : POSITIVE := c_ctlr_data_w/c_data_w;
+
+  SIGNAL sync_check_in_sosi   : t_dp_sosi;          
+  SIGNAL sync_check_in_siso   : t_dp_siso := c_dp_siso_rdy;          
+  
+  SIGNAL dp_sync_chk_out_sosi : t_dp_sosi;
+  
+  SIGNAL packet_merge_in_sosi : t_dp_sosi;          
+  SIGNAL packet_merge_in_siso : t_dp_siso; 
                               
   SIGNAL ss_in_sosi           : t_dp_sosi;          
-  SIGNAL ss_in_siso           : t_dp_siso;          
+  SIGNAL ss_in_siso           : t_dp_siso := c_dp_siso_rdy;          
   
-    -- ctrl & status DDR3 driver
+  -- ctrl & status DDR3 driver
   SIGNAL dvr_done             : STD_LOGIC;
   SIGNAL dvr_en               : STD_LOGIC;
   SIGNAL dvr_wr_not_rd        : STD_LOGIC;
@@ -158,23 +164,16 @@ ARCHITECTURE str OF reorder_transpose IS
   SIGNAL rd_req_i             : STD_LOGIC;
   SIGNAL rd_dat_i             : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
   SIGNAL rd_val_i             : STD_LOGIC;
-  
-  SIGNAL cnt_sop              : STD_LOGIC_VECTOR(c_cnt_sop_w-1 DOWNTO 0);
-  SIGNAL nof_sop              : STD_LOGIC_VECTOR(c_cnt_sop_w-1 DOWNTO 0);
-  SIGNAL i_mon_nof_sop        : STD_LOGIC_VECTOR(c_cnt_sop_w-1 DOWNTO 0);
-  SIGNAL nxt_mon_nof_sop      : STD_LOGIC_VECTOR(c_cnt_sop_w-1 DOWNTO 0);
-  SIGNAL sync_ok_in           : STD_LOGIC;
-  SIGNAL sync_ok_out          : STD_LOGIC;  
-    
+     
 BEGIN 
 
   g_merge_in_complex : IF g_use_complex = TRUE GENERATE 
     PROCESS(snk_in_arr)
     BEGIN 
-      ss_in_sosi <= snk_in_arr(0);
+      sync_check_in_sosi <= snk_in_arr(0);
       FOR i IN 0 TO g_nof_streams-1 LOOP
-        ss_in_sosi.data((2*i+1)*g_in_dat_w-1 DOWNTO 2*i*g_in_dat_w)     <= snk_in_arr(i).re(g_in_dat_w-1 DOWNTO 0);
-        ss_in_sosi.data((2*i+2)*g_in_dat_w-1 DOWNTO (2*i+1)*g_in_dat_w) <= snk_in_arr(i).im(g_in_dat_w-1 DOWNTO 0);
+        sync_check_in_sosi.data((2*i+1)*g_in_dat_w-1 DOWNTO 2*i*g_in_dat_w)     <= snk_in_arr(i).re(g_in_dat_w-1 DOWNTO 0);
+        sync_check_in_sosi.data((2*i+2)*g_in_dat_w-1 DOWNTO (2*i+1)*g_in_dat_w) <= snk_in_arr(i).im(g_in_dat_w-1 DOWNTO 0);
       END LOOP;
     END PROCESS;     
   END GENERATE;
@@ -182,12 +181,46 @@ BEGIN
   g_merge_in_data : IF g_use_complex = FALSE GENERATE 
     PROCESS(snk_in_arr)
     BEGIN 
-      ss_in_sosi <= snk_in_arr(0);
+      sync_check_in_sosi <= snk_in_arr(0);
       FOR i IN 0 TO g_nof_streams-1 LOOP
-        ss_in_sosi.data((i+1)*g_in_dat_w-1 DOWNTO i*g_in_dat_w) <= snk_in_arr(i).data(g_in_dat_w-1 DOWNTO 0);
+        sync_check_in_sosi.data((i+1)*g_in_dat_w-1 DOWNTO i*g_in_dat_w) <= snk_in_arr(i).data(g_in_dat_w-1 DOWNTO 0);
       END LOOP;
     END PROCESS;     
   END GENERATE;  
+  
+  g_siso : FOR J IN 0 TO g_nof_streams-1 GENERATE
+    snk_out_arr(J) <= sync_check_in_siso;
+  END GENERATE;
+  
+  u_sync_check_and_restore : ENTITY dp_lib.dp_sync_checker
+  GENERIC MAP (
+    g_nof_blk_per_sync => g_nof_blk_per_sync
+  )
+  PORT MAP (
+    mm_rst  => mm_rst,
+    mm_clk  => mm_clk,
+    dp_rst  => dp_rst,
+    dp_clk  => dp_clk,
+    snk_out => sync_check_in_siso,     
+    snk_in  => sync_check_in_sosi,
+    src_in  => packet_merge_in_siso,    
+    src_out => packet_merge_in_sosi
+  );
+  
+  u_dp_packet_merge : ENTITY dp_lib.dp_packet_merge
+  GENERIC MAP (
+    g_nof_pkt => g_reorder_seq.rd_chunksize
+  )
+  PORT MAP (
+    rst         => dp_rst,
+    clk         => dp_clk,
+
+    snk_out     => packet_merge_in_siso,
+    snk_in      => packet_merge_in_sosi,
+
+    src_in      => ss_in_siso,
+    src_out     => ss_in_sosi
+  );
 
   gen_pre_transpose : IF g_ena_pre_transp = TRUE GENERATE 
     u_single_ss : ENTITY work.ss
@@ -210,11 +243,12 @@ BEGIN
       
       -- Streaming
       input_sosi     => ss_in_sosi,
-      input_siso     => ss_in_siso,
+      input_siso     => OPEN,                  -- Don't allow backpressure. 
                      
       output_sosi    => to_mem_src_out_i,
       output_siso    => to_mem_src_in
     );
+    
   END GENERATE;  
   
   to_mem_src_out <= to_mem_src_out_i;
@@ -223,66 +257,33 @@ BEGIN
     to_mem_src_out_i <= ss_in_sosi;
     ss_in_siso       <= to_mem_src_in;
   END GENERATE;  
-    
-  g_siso : FOR J IN 0 TO g_nof_streams-1 GENERATE
-    snk_out_arr(J) <= ss_in_siso;
-  END GENERATE;
    
   -- Map original dvr interface signals to t_mem_ctlr_mosi/miso
-  dvr_done              <= dvr_miso.done;           -- Requested wr or rd sequence is done
-  dvr_mosi.burstbegin   <= dvr_en;
-  dvr_mosi.wr           <= dvr_wr_not_rd;           -- No need to use dvr_mosi.rd
-  dvr_mosi.address      <= RESIZE_MEM_CTLR_ADDRESS(dvr_start_address);
-  dvr_mosi.burstsize    <= RESIZE_MEM_CTLR_BURSTSIZE(dvr_nof_data);
-  dvr_mosi.flush        <= dvr_wr_flush_en;
-
-  dvr_wr_flush_en <= NOT(sync_ok_out); 
-
+  dvr_done            <= dvr_miso.done;           -- Requested wr or rd sequence is done
+  dvr_mosi.burstbegin <= dvr_en;
+  dvr_mosi.wr         <= dvr_wr_not_rd;           -- No need to use dvr_mosi.rd
+  dvr_mosi.address    <= RESIZE_MEM_CTLR_ADDRESS(dvr_start_address);
+  dvr_mosi.burstsize  <= RESIZE_MEM_CTLR_BURSTSIZE(dvr_nof_data);
+  dvr_mosi.flush      <= dvr_wr_flush_en;
+  dvr_wr_flush_en     <= '0';
+  
   u_ddr_sequencer: ENTITY work.reorder_sequencer
   GENERIC MAP(
     g_reorder_seq  => g_reorder_seq,
     g_data_w_ratio => c_data_w_ratio
   )                      
   PORT MAP (       
-    dp_rst      => dp_rst,
-    dp_clk      => dp_clk,
-                
-    en_evt      => dvr_en, 
-    wr_not_rd   => dvr_wr_not_rd,
-                
-    address     => dvr_start_address,
-    burstsize   => dvr_nof_data,
-                
-    done        =>  dvr_done,
-                
-    sync_ok_in  => sync_ok_in,
-    sync_ok_out => sync_ok_out
-  );
-    
-  u_cnt_sop : ENTITY common_lib.common_counter
-  GENERIC MAP (
-    g_width => c_cnt_sop_w
-  )
-  PORT MAP (
-    rst     => dp_rst,
-    clk     => dp_clk,
-    cnt_clr => to_mem_src_out_i.sync,
-    cnt_en  => to_mem_src_out_i.sop,
-    count   => cnt_sop
+    dp_rst    => dp_rst,
+    dp_clk    => dp_clk,
+              
+    en_evt    => dvr_en, 
+    wr_not_rd => dvr_wr_not_rd,
+              
+    address   => dvr_start_address,
+    burstsize => dvr_nof_data,
+              
+    done      =>  dvr_done
   );
-  
-  nof_sop         <= INCR_UVEC(cnt_sop, 1);    -- +1 because the sop at the sync also counts
-  nxt_mon_nof_sop <= nof_sop WHEN to_mem_src_out_i.sync='1' ELSE i_mon_nof_sop;
-  sync_ok_in      <= '1'     WHEN TO_UINT(i_mon_nof_sop) = g_nof_blk_per_sync AND TO_UINT(nof_sop) <= g_nof_blk_per_sync ELSE '0';
-  
-  p_clk : PROCESS(dp_rst, dp_clk)
-  BEGIN
-    IF dp_rst = '1' THEN
-      i_mon_nof_sop <= (OTHERS=>'0');
-    ELSIF rising_edge(dp_clk) THEN
-      i_mon_nof_sop <= nxt_mon_nof_sop;
-    END IF;
-  END PROCESS;
     
   ---------------------------------------------------------------
   -- FIFO FOR SYNC-BSN