- Removed sync_ok_in en sync_ok_out

libraries/base/reorder/src/vhdl/reorder_sequencer.vhd

@@ -110,10 +110,7 @@ ENTITY reorder_sequencer IS
     address     : OUT STD_LOGIC_VECTOR;
     burstsize   : OUT STD_LOGIC_VECTOR;
                 
-    done        : IN  STD_LOGIC;
-    
-    sync_ok_in  : IN  STD_LOGIC;
-    sync_ok_out : OUT STD_LOGIC
+    done        : IN  STD_LOGIC
    );
 END reorder_sequencer;
 
@@ -144,7 +141,6 @@ ARCHITECTURE rtl OF reorder_sequencer IS
     switch_cnt       : NATURAL;   -- Counter that counts the write and read accesses to determine the switch between read and write phase. 
     page_cnt         : NATURAL;   -- Counter that counts the number of write accesses to determuine the page-swap. 
     first_write      : STD_LOGIC;
-    sync_ok_out      : STD_LOGIC;
     start_addr       : STD_LOGIC_VECTOR(c_address_w - 1 DOWNTO 0);
     burstsize        : STD_LOGIC_VECTOR(c_address_w - 1 DOWNTO 0);
     state            : state_type;  -- The state machine. 
@@ -159,7 +155,7 @@ BEGIN
   ---------------------------------------------------------------
   ASSERT NOT((g_reorder_seq.wr_nof_chunks*g_reorder_seq.wr_chunksize) /= (g_reorder_seq.rd_nof_chunks*g_reorder_seq.rd_chunksize) AND rising_edge(dp_clk)) REPORT "Total write configuration is different from total read configuration!!!" SEVERITY FAILURE;
     
-  p_comb : PROCESS(r, dp_rst, done, sync_ok_in)
+  p_comb : PROCESS(r, dp_rst, done)
     VARIABLE v : reg_type;
   BEGIN
    
@@ -168,9 +164,8 @@ BEGIN
     
     CASE r.state IS
       WHEN s_idle => 
-        IF(done = '1' AND sync_ok_in = '1') THEN     
+        IF(done = '1') THEN     
           v.first_write := '1';
-          v.sync_ok_out := sync_ok_in;
           v.state       := s_first_write;  
         END IF;
 
@@ -185,9 +180,7 @@ BEGIN
       WHEN s_write =>  
         IF(done = '1') THEN 
           v.wr_not_rd  := '1'; 
-          IF(sync_ok_in = '1') THEN   -- Only write when good sync pattern on the input.
-            v.ddr3_en    := '1';
-          END IF;
+          v.ddr3_en    := '1';
           v.start_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset + r.wr_chunks_offset, c_address_w);                   
           v.burstsize  := TO_UVEC(g_reorder_seq.wr_chunksize, c_address_w);
           v.switch_cnt := r.switch_cnt + 1;
@@ -228,7 +221,6 @@ BEGIN
           v.burstsize   := TO_UVEC(g_reorder_seq.rd_chunksize, c_address_w);
           v.switch_cnt  := r.switch_cnt + 1; 
           v.state       := s_wait_rd;
-          v.sync_ok_out := sync_ok_in;
         END IF;
   
       WHEN s_wait_rd => 
@@ -249,9 +241,9 @@ BEGIN
             v.wr_page_offset := r.rd_page_offset;
             v.page_cnt       := 0;  
             v.first_write    := '0';
-            IF(sync_ok_in = '0') THEN
-              v.state := s_idle;
-            END IF;
+--            IF(sync_ok_in = '0') THEN
+--              v.state := s_idle;
+--            END IF;
           END IF; 
         ELSIF(r.rd_block_cnt = g_reorder_seq.nof_blocks-1) THEN 
           v.rd_block_offset  := 0;
@@ -283,7 +275,6 @@ BEGIN
       v.rd_chunks_offset := 0;
       v.rd_block_cnt     := 0;
       v.rd_chunks_cnt    := 0;
-      v.sync_ok_out      := '0';
       v.start_addr       := (OTHERS => '0');
       v.burstsize        := (OTHERS => '0');
       v.first_write      := '1';
@@ -303,7 +294,6 @@ BEGIN
 
   en_evt      <= r.ddr3_en;
   wr_not_rd   <= r.wr_not_rd;
-  sync_ok_out <= r.sync_ok_out;
   address     <= RESIZE_UVEC(r.start_addr(c_address_w-1 DOWNTO c_address_shift_w), address'LENGTH);
   burstsize   <= RESIZE_UVEC(r.burstsize(c_address_w-1 DOWNTO c_address_shift_w),  burstsize'LENGTH);