-Added experimental myHDL.

applications/apertif/designs/apertif_unb1_fn_bf_emu/src/myhdl/gen_mms_diag_block_gen.py

+###############################################################################
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+"""
+Purpose:
+. Instantiate mms_diag_block_gen.vhd in myHDL and generate a new VHDL wrapper
+  around it.
+Description:
+. This a first test to integrate myHDL-generated code in the existing RadioHDL
+  environment. DS used following directory for reference/examples:
+  . RadioHDL/trunk/tools/oneclick/prestudy/myHDL
+Remarks:
+. The following ports of the VHDL entity are not connected (left at default):
+  . en_sync
+  . all MM buses
+  . usr_siso_arr, usr_sosi_arr
+  . out_siso_arr
+. MyHDL does not support our types such as t_mem_mosi and t_dp_sosi. This is 
+  not a problem as we include user-defined code to map our types onto myHDL
+  compatible types. This code is literally pasted into the file and therefor
+  falls outside of the myHDL scope.
+  . We use separate DP signals for now, but we may also combine them into a
+    Python record as this is fully supported my myHDL.
+"""
+
+from myhdl import *
+
+###############################################################################
+# MyHDL function definition
+# . VHDL entity I/O ports
+#   . We need to declare the same I/O ports as exist on the VHDL entity. We
+#     declare them as function arguments.
+# . VHDL Architecture
+#   . Not described here (pass). We set the .vhdl_code attribute later on to 
+#     insert literal VHDL.
+###############################################################################
+def myhdl_mms_diag_block_gen_wrap(mm_rst,mm_clk,dp_rst,dp_clk,out_sosi_arr):
+
+    @always(dp_clk)
+    def wrap():
+        # Nothing to do here.
+        pass
+
+    # Important: explicitely say this output is driven, otherwise myHDL makes
+    # these all inputs.
+    out_sosi_arr.driven = "wire"
+
+    return wrap
+
+###############################################################################
+# Architecture VHDL code: Instantiate mms_diag_block_gen
+###############################################################################
+myhdl_mms_diag_block_gen_wrap.vhdl_code =\
+"""
+  u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
+  GENERIC MAP (
+    g_nof_streams        => 4,
+    g_buf_dat_w          => 16,
+    g_buf_addr_w         => 256,
+    g_file_name_prefix   => "hex/bg_data",
+    g_diag_block_gen_rst => c_bg_ctrl
+  )
+  PORT MAP (
+    mm_rst           => mm_rst,
+    mm_clk           => mm_clk,
+  
+    dp_rst           => dp_rst,
+    dp_clk           => dp_clk,
+
+    out_sosi_arr     => out_sosi_arr
+  );
+"""
+
+###############################################################################
+# Convert to VHDL
+###############################################################################
+toVHDL(myhdl_mms_diag_block_gen_wrap,mm_rst,mm_clk,dp_rst,dp_clk,out_sosi_arr)
+