-Added inc_comb.py + description in readme_myHDL.txt.

tools/oneclick/prestudy/myHDL/inc_comb.py

+from myhdl import *
+
+def inc_comb(nextCount, count, n):
+
+    @always(count)
+    def logic():
+        # do nothing here
+        pass
+
+    nextCount.driven = "wire"
+
+    return logic
+
+inc_comb.verilog_code =\
+"""
+assign $nextCount = ($count + 1) % $n;
+"""
+
+inc_comb.vhdl_code =\
+"""
+$nextCount <= ($count + 1) mod $n;
+"""
+
+def convert():
+
+    nextCount = Signal(intbv(0)[8:])
+    count = Signal(intbv(0)[8:])
+
+    toVerilog(inc_comb, nextCount, count, 256 )
+    toVHDL(inc_comb, nextCount, count, 256)
+
+convert()

tools/oneclick/prestudy/myHDL/readme_myHDL.txt

@@ -24,4 +24,5 @@ This dir contains:
    -> Creates tb_muxed_block_gens.v (template TB file)
    -> Creates pck_myhdl_081.vhd (a package file)
    -> Creates muxed_block_gens.vhd
-
+-inc_comb.py: example code from the myHDL Manual, but completed so it generates
+ output files. It demonstrates how to include user defined code.