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Commit 86455877 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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added fifo in between bg and dp_offload

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boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
+ 248
− 165
View file @ 86455877
...@@ -65,59 +65,59 @@ ...@@ -65,59 +65,59 @@
type = "String"; type = "String";
} }
} }
element reg_tr_10GbE.mem element reg_dpmm_ctrl.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "524288"; value = "12432";
type = "long"; type = "long";
} }
} }
element reg_unb_sens.mem element reg_dpmm_data.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "12416"; value = "12440";
type = "long"; type = "long";
} }
} }
element reg_diag_data_buffer.mem element reg_mmdp_data.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "128"; value = "12456";
type = "long"; type = "long";
} }
} }
element reg_diag_bg.mem element reg_dp_offload_rx_hdr_dat.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "12544"; value = "1024";
type = "long"; type = "long";
} }
} }
element pio_pps.mem element reg_remu.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "12624"; value = "12320";
type = "long"; type = "long";
} }
} }
element reg_dp_offload_tx_hdr_dat.mem element reg_unb_sens.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "13312"; value = "480";
type = "long"; type = "long";
} }
} }
element reg_epcs.mem element reg_diag_bg.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "12480"; value = "12384";
type = "long"; type = "long";
} }
} }
...@@ -129,113 +129,113 @@ ...@@ -129,113 +129,113 @@
type = "long"; type = "long";
} }
} }
element reg_dpmm_data.mem element pio_pps.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "12600"; value = "12464";
type = "long"; type = "long";
} }
} }
element reg_io_ddr.mem element reg_dp_offload_tx.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "12576"; value = "320";
type = "long"; type = "long";
} }
} }
element rom_system_info.mem element reg_diag_data_buffer.mem
{
datum _lockedAddress
{ {
value = "1";
type = "boolean";
}
datum baseAddress datum baseAddress
{ {
value = "4096"; value = "128";
type = "long"; type = "long";
} }
} }
element reg_dp_offload_rx_hdr_dat.mem element reg_dp_offload_tx_1gbe_hdr_dat.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1024"; value = "28672";
type = "long"; type = "long";
} }
} }
element reg_dpmm_ctrl.mem element reg_tr_10GbE.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "12592"; value = "262144";
type = "long"; type = "long";
} }
} }
element reg_mmdp_data.mem element ram_diag_bg.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "12616"; value = "32768";
type = "long"; type = "long";
} }
} }
element reg_dp_offload_tx_hdr_ovr.mem element ram_ss_ss_wide.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "512"; value = "393216";
type = "long"; type = "long";
} }
} }
element ram_diag_bg.mem element pio_system_info.mem
{
datum _lockedAddress
{ {
value = "1";
type = "boolean";
}
datum baseAddress datum baseAddress
{ {
value = "262144"; value = "0";
type = "long"; type = "long";
} }
} }
element ram_diag_data_buffer.mem element rom_system_info.mem
{
datum _lockedAddress
{ {
value = "1";
type = "boolean";
}
datum baseAddress datum baseAddress
{ {
value = "65536"; value = "4096";
type = "long"; type = "long";
} }
} }
element ram_ss_ss_wide.mem element reg_io_ddr.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "655360"; value = "12416";
type = "long"; type = "long";
} }
} }
element reg_wdi.mem element reg_dp_offload_tx_hdr_dat.mem
{
datum _lockedAddress
{ {
value = "1";
type = "boolean";
}
datum baseAddress datum baseAddress
{ {
value = "12288"; value = "13312";
type = "long"; type = "long";
} }
} }
element reg_bsn_monitor.mem element reg_epcs.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "256"; value = "12352";
type = "long"; type = "long";
} }
} }
element pio_system_info.mem element reg_wdi.mem
{ {
datum _lockedAddress datum _lockedAddress
{ {
...@@ -244,7 +244,15 @@ ...@@ -244,7 +244,15 @@
} }
datum baseAddress datum baseAddress
{ {
value = "0"; value = "12288";
type = "long";
}
}
element reg_bsn_monitor.mem
{
datum baseAddress
{
value = "512";
type = "long"; type = "long";
} }
} }
...@@ -252,23 +260,23 @@ ...@@ -252,23 +260,23 @@
{ {
datum baseAddress datum baseAddress
{ {
value = "12608"; value = "12448";
type = "long"; type = "long";
} }
} }
element reg_dp_offload_tx.mem element ram_diag_data_buffer.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "12512"; value = "65536";
type = "long"; type = "long";
} }
} }
element reg_remu.mem element reg_dp_offload_tx_1gbe.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "12448"; value = "384";
type = "long"; type = "long";
} }
} }
...@@ -284,7 +292,7 @@ ...@@ -284,7 +292,7 @@
{ {
datum baseAddress datum baseAddress
{ {
value = "12352"; value = "256";
type = "long"; type = "long";
} }
} }
...@@ -342,7 +350,7 @@ ...@@ -342,7 +350,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "28"; value = "27";
type = "int"; type = "int";
} }
} }
...@@ -350,7 +358,7 @@ ...@@ -350,7 +358,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "26"; value = "25";
type = "int"; type = "int";
} }
} }
...@@ -358,7 +366,7 @@ ...@@ -358,7 +366,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "29"; value = "28";
type = "int"; type = "int";
} }
} }
...@@ -374,7 +382,7 @@ ...@@ -374,7 +382,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "27"; value = "26";
type = "int"; type = "int";
} }
} }
...@@ -382,7 +390,7 @@ ...@@ -382,7 +390,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "25"; value = "24";
type = "int"; type = "int";
} }
} }
...@@ -402,19 +410,27 @@ ...@@ -402,19 +410,27 @@
type = "int"; type = "int";
} }
} }
element reg_dp_offload_tx_hdr_dat element reg_dp_offload_tx_1gbe
{ {
datum _sortIndex datum _sortIndex
{ {
value = "22"; value = "30";
type = "int"; type = "int";
} }
} }
element reg_dp_offload_tx_hdr_ovr element reg_dp_offload_tx_1gbe_hdr_dat
{ {
datum _sortIndex datum _sortIndex
{ {
value = "24"; value = "31";
type = "int";
}
}
element reg_dp_offload_tx_hdr_dat
{
datum _sortIndex
{
value = "22";
type = "int"; type = "int";
} }
} }
...@@ -446,7 +462,7 @@ ...@@ -446,7 +462,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "30"; value = "29";
type = "int"; type = "int";
} }
} }
...@@ -514,6 +530,14 @@ ...@@ -514,6 +530,14 @@
type = "int"; type = "int";
} }
} }
element pio_wdi.s1
{
datum baseAddress
{
value = "12304";
type = "long";
}
}
element onchip_memory2_0.s1 element onchip_memory2_0.s1
{ {
datum _lockedAddress datum _lockedAddress
...@@ -527,19 +551,11 @@ ...@@ -527,19 +551,11 @@
type = "long"; type = "long";
} }
} }
element pio_wdi.s1
{
datum baseAddress
{
value = "12304";
type = "long";
}
}
element timer_0.s1 element timer_0.s1
{ {
datum baseAddress datum baseAddress
{ {
value = "12320"; value = "448";
type = "long"; type = "long";
} }
} }
...@@ -566,7 +582,7 @@ ...@@ -566,7 +582,7 @@
<parameter name="projectName" value="" /> <parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" /> <parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" /> <parameter name="systemHash" value="1" />
<parameter name="timeStamp" value="1427787271744" /> <parameter name="timeStamp" value="1429017518755" />
<parameter name="useTestBenchNamingPattern" value="false" /> <parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript> <instanceScript></instanceScript>
<interface <interface
...@@ -1664,41 +1680,6 @@ ...@@ -1664,41 +1680,6 @@
internal="reg_dp_offload_rx_hdr_dat.reset" internal="reg_dp_offload_rx_hdr_dat.reset"
type="conduit" type="conduit"
dir="end" /> dir="end" />
<interface
name="reg_dp_offload_tx_hdr_ovr_readdata"
internal="reg_dp_offload_tx_hdr_ovr.readdata"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_hdr_ovr_read"
internal="reg_dp_offload_tx_hdr_ovr.read"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_hdr_ovr_writedata"
internal="reg_dp_offload_tx_hdr_ovr.writedata"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_hdr_ovr_write"
internal="reg_dp_offload_tx_hdr_ovr.write"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_hdr_ovr_address"
internal="reg_dp_offload_tx_hdr_ovr.address"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_hdr_ovr_clk"
internal="reg_dp_offload_tx_hdr_ovr.clk"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_hdr_ovr_reset"
internal="reg_dp_offload_tx_hdr_ovr.reset"
type="conduit"
dir="end" />
<interface <interface
name="reg_diag_data_buffer_readdata" name="reg_diag_data_buffer_readdata"
internal="reg_diag_data_buffer.readdata" internal="reg_diag_data_buffer.readdata"
...@@ -1909,6 +1890,76 @@ ...@@ -1909,6 +1890,76 @@
internal="reg_io_ddr.reset" internal="reg_io_ddr.reset"
type="conduit" type="conduit"
dir="end" /> dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_readdata"
internal="reg_dp_offload_tx_1gbe.readdata"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_read"
internal="reg_dp_offload_tx_1gbe.read"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_writedata"
internal="reg_dp_offload_tx_1gbe.writedata"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_write"
internal="reg_dp_offload_tx_1gbe.write"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_address"
internal="reg_dp_offload_tx_1gbe.address"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_clk"
internal="reg_dp_offload_tx_1gbe.clk"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_reset"
internal="reg_dp_offload_tx_1gbe.reset"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_hdr_dat_readdata"
internal="reg_dp_offload_tx_1gbe_hdr_dat.readdata"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_hdr_dat_read"
internal="reg_dp_offload_tx_1gbe_hdr_dat.read"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_hdr_dat_writedata"
internal="reg_dp_offload_tx_1gbe_hdr_dat.writedata"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_hdr_dat_write"
internal="reg_dp_offload_tx_1gbe_hdr_dat.write"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_hdr_dat_address"
internal="reg_dp_offload_tx_1gbe_hdr_dat.address"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_hdr_dat_clk"
internal="reg_dp_offload_tx_1gbe_hdr_dat.clk"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_hdr_dat_reset"
internal="reg_dp_offload_tx_1gbe_hdr_dat.reset"
type="conduit"
dir="end" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0"> <module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="125000000" /> <parameter name="clockFrequency" value="125000000" />
<parameter name="clockFrequencyKnown" value="true" /> <parameter name="clockFrequencyKnown" value="true" />
...@@ -2139,7 +2190,7 @@ q]]></parameter> ...@@ -2139,7 +2190,7 @@ q]]></parameter>
<parameter name="dcache_numTCDM" value="0" /> <parameter name="dcache_numTCDM" value="0" />
<parameter name="dcache_lineSize" value="32" /> <parameter name="dcache_lineSize" value="32" />
<parameter name="instAddrWidth" value="18" /> <parameter name="instAddrWidth" value="18" />
<parameter name="dataAddrWidth" value="20" /> <parameter name="dataAddrWidth" value="19" />
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" /> <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" /> <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" /> <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
...@@ -2149,7 +2200,7 @@ q]]></parameter> ...@@ -2149,7 +2200,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" /> <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" /> <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter> <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='reg_bsn_monitor.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_unb_sens.mem' start='0x3080' end='0x30A0' /><slave name='reg_remu.mem' start='0x30A0' end='0x30C0' /><slave name='reg_epcs.mem' start='0x30C0' end='0x30E0' /><slave name='reg_dp_offload_tx.mem' start='0x30E0' end='0x3100' /><slave name='reg_diag_bg.mem' start='0x3100' end='0x3120' /><slave name='reg_io_ddr.mem' start='0x3120' end='0x3130' /><slave name='reg_dpmm_ctrl.mem' start='0x3130' end='0x3138' /><slave name='reg_dpmm_data.mem' start='0x3138' end='0x3140' /><slave name='reg_mmdp_ctrl.mem' start='0x3140' end='0x3148' /><slave name='reg_mmdp_data.mem' start='0x3148' end='0x3150' /><slave name='pio_pps.mem' start='0x3150' end='0x3158' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_bg.mem' start='0x40000' end='0x80000' /><slave name='reg_tr_10GbE.mem' start='0x80000' end='0xA0000' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' /></address-map>]]></parameter> <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='avs_eth_0.mms_reg' start='0x100' end='0x140' /><slave name='reg_dp_offload_tx.mem' start='0x140' end='0x180' /><slave name='reg_dp_offload_tx_1gbe.mem' start='0x180' end='0x1C0' /><slave name='timer_0.s1' start='0x1C0' end='0x1E0' /><slave name='reg_unb_sens.mem' start='0x1E0' end='0x200' /><slave name='reg_bsn_monitor.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='reg_remu.mem' start='0x3020' end='0x3040' /><slave name='reg_epcs.mem' start='0x3040' end='0x3060' /><slave name='reg_diag_bg.mem' start='0x3060' end='0x3080' /><slave name='reg_io_ddr.mem' start='0x3080' end='0x3090' /><slave name='reg_dpmm_ctrl.mem' start='0x3090' end='0x3098' /><slave name='reg_dpmm_data.mem' start='0x3098' end='0x30A0' /><slave name='reg_mmdp_ctrl.mem' start='0x30A0' end='0x30A8' /><slave name='reg_mmdp_data.mem' start='0x30A8' end='0x30B0' /><slave name='pio_pps.mem' start='0x30B0' end='0x30B8' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='reg_dp_offload_tx_1gbe_hdr_dat.mem' start='0x7000' end='0x7400' /><slave name='ram_diag_bg.mem' start='0x8000' end='0x10000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="125000000" /> <parameter name="clockFrequency" value="125000000" />
<parameter name="deviceFamilyName" value="Stratix IV" /> <parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" /> <parameter name="internalIrqMaskSystemInfo" value="7" />
...@@ -2165,7 +2216,7 @@ q]]></parameter> ...@@ -2165,7 +2216,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" /> <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
</module> </module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="reg_bsn_monitor"> <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_bsn_monitor">
<parameter name="g_adr_w" value="6" /> <parameter name="g_adr_w" value="7" />
<parameter name="g_dat_w" value="32" /> <parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" /> <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module> </module>
...@@ -2174,7 +2225,7 @@ q]]></parameter> ...@@ -2174,7 +2225,7 @@ q]]></parameter>
version="1.0" version="1.0"
enabled="1" enabled="1"
name="reg_dp_offload_tx"> name="reg_dp_offload_tx">
<parameter name="g_adr_w" value="3" /> <parameter name="g_adr_w" value="4" />
<parameter name="g_dat_w" value="32" /> <parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" /> <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module> </module>
...@@ -2196,15 +2247,6 @@ q]]></parameter> ...@@ -2196,15 +2247,6 @@ q]]></parameter>
<parameter name="g_dat_w" value="32" /> <parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" /> <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module> </module>
<module
kind="avs_common_mm"
version="1.0"
enabled="1"
name="reg_dp_offload_tx_hdr_ovr">
<parameter name="g_adr_w" value="7" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
<module <module
kind="avs_common_mm" kind="avs_common_mm"
version="1.0" version="1.0"
...@@ -2229,7 +2271,7 @@ q]]></parameter> ...@@ -2229,7 +2271,7 @@ q]]></parameter>
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" /> <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module> </module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="ram_diag_bg"> <module kind="avs_common_mm" version="1.0" enabled="1" name="ram_diag_bg">
<parameter name="g_adr_w" value="16" /> <parameter name="g_adr_w" value="13" />
<parameter name="g_dat_w" value="32" /> <parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" /> <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module> </module>
...@@ -2243,6 +2285,24 @@ q]]></parameter> ...@@ -2243,6 +2285,24 @@ q]]></parameter>
<parameter name="g_dat_w" value="32" /> <parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" /> <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module> </module>
<module
kind="avs_common_mm"
version="1.0"
enabled="1"
name="reg_dp_offload_tx_1gbe">
<parameter name="g_adr_w" value="4" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
<module
kind="avs_common_mm"
version="1.0"
enabled="1"
name="reg_dp_offload_tx_1gbe_hdr_dat">
<parameter name="g_adr_w" value="8" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
<connection <connection
kind="avalon" kind="avalon"
version="11.1" version="11.1"
...@@ -2304,7 +2364,7 @@ q]]></parameter> ...@@ -2304,7 +2364,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="timer_0.s1"> end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3020" /> <parameter name="baseAddress" value="0x01c0" />
</connection> </connection>
<connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq"> <connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq">
<parameter name="irqNumber" value="1" /> <parameter name="irqNumber" value="1" />
...@@ -2315,7 +2375,7 @@ q]]></parameter> ...@@ -2315,7 +2375,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="reg_unb_sens.mem"> end="reg_unb_sens.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3080" /> <parameter name="baseAddress" value="0x01e0" />
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
...@@ -2347,7 +2407,7 @@ q]]></parameter> ...@@ -2347,7 +2407,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="reg_remu.mem"> end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x30a0" /> <parameter name="baseAddress" value="0x3020" />
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
...@@ -2355,7 +2415,7 @@ q]]></parameter> ...@@ -2355,7 +2415,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem"> end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3130" /> <parameter name="baseAddress" value="0x3090" />
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
...@@ -2363,7 +2423,7 @@ q]]></parameter> ...@@ -2363,7 +2423,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="reg_dpmm_data.mem"> end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3138" /> <parameter name="baseAddress" value="0x3098" />
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
...@@ -2371,7 +2431,7 @@ q]]></parameter> ...@@ -2371,7 +2431,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem"> end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3140" /> <parameter name="baseAddress" value="0x30a0" />
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
...@@ -2379,7 +2439,7 @@ q]]></parameter> ...@@ -2379,7 +2439,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="reg_mmdp_data.mem"> end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3148" /> <parameter name="baseAddress" value="0x30a8" />
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
...@@ -2387,7 +2447,7 @@ q]]></parameter> ...@@ -2387,7 +2447,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="reg_epcs.mem"> end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x30c0" /> <parameter name="baseAddress" value="0x3040" />
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
...@@ -2395,7 +2455,7 @@ q]]></parameter> ...@@ -2395,7 +2455,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="pio_pps.mem"> end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3150" /> <parameter name="baseAddress" value="0x30b0" />
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
...@@ -2403,7 +2463,7 @@ q]]></parameter> ...@@ -2403,7 +2463,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="reg_tr_10GbE.mem"> end="reg_tr_10GbE.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00080000" /> <parameter name="baseAddress" value="0x00040000" />
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
...@@ -2419,7 +2479,7 @@ q]]></parameter> ...@@ -2419,7 +2479,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="avs_eth_0.mms_reg"> end="avs_eth_0.mms_reg">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3040" /> <parameter name="baseAddress" value="0x0100" />
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
...@@ -2645,7 +2705,7 @@ q]]></parameter> ...@@ -2645,7 +2705,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="reg_bsn_monitor.mem"> end="reg_bsn_monitor.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0100" /> <parameter name="baseAddress" value="0x0200" />
</connection> </connection>
<connection <connection
kind="reset" kind="reset"
...@@ -2696,7 +2756,7 @@ q]]></parameter> ...@@ -2696,7 +2756,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="reg_dp_offload_tx.mem"> end="reg_dp_offload_tx.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x30e0" /> <parameter name="baseAddress" value="0x0140" />
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
...@@ -2706,14 +2766,6 @@ q]]></parameter> ...@@ -2706,14 +2766,6 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3400" /> <parameter name="baseAddress" value="0x3400" />
</connection> </connection>
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="reg_dp_offload_tx_hdr_ovr.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0200" />
</connection>
<connection <connection
kind="avalon" kind="avalon"
version="11.1" version="11.1"
...@@ -2730,11 +2782,6 @@ q]]></parameter> ...@@ -2730,11 +2782,6 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010000" /> <parameter name="baseAddress" value="0x00010000" />
</connection> </connection>
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
end="reg_dp_offload_tx_hdr_ovr.system_reset" />
<connection <connection
kind="reset" kind="reset"
version="11.1" version="11.1"
...@@ -2745,11 +2792,6 @@ q]]></parameter> ...@@ -2745,11 +2792,6 @@ q]]></parameter>
version="11.1" version="11.1"
start="cpu_0.jtag_debug_module_reset" start="cpu_0.jtag_debug_module_reset"
end="ram_diag_data_buffer.system_reset" /> end="ram_diag_data_buffer.system_reset" />
<connection
kind="reset"
version="11.1"
start="clk_0.clk_reset"
end="reg_dp_offload_tx_hdr_ovr.system_reset" />
<connection <connection
kind="reset" kind="reset"
version="11.1" version="11.1"
...@@ -2766,7 +2808,7 @@ q]]></parameter> ...@@ -2766,7 +2808,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="reg_diag_bg.mem"> end="reg_diag_bg.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3100" /> <parameter name="baseAddress" value="0x3060" />
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
...@@ -2774,7 +2816,7 @@ q]]></parameter> ...@@ -2774,7 +2816,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="ram_diag_bg.mem"> end="ram_diag_bg.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00040000" /> <parameter name="baseAddress" value="0x8000" />
</connection> </connection>
<connection <connection
kind="reset" kind="reset"
...@@ -2812,7 +2854,7 @@ q]]></parameter> ...@@ -2812,7 +2854,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="ram_ss_ss_wide.mem"> end="ram_ss_ss_wide.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x000a0000" /> <parameter name="baseAddress" value="0x00060000" />
</connection> </connection>
<connection kind="clock" version="11.1" start="clk_0.clk" end="cpu_0.clk" /> <connection kind="clock" version="11.1" start="clk_0.clk" end="cpu_0.clk" />
<connection <connection
...@@ -2893,11 +2935,6 @@ q]]></parameter> ...@@ -2893,11 +2935,6 @@ q]]></parameter>
version="11.1" version="11.1"
start="clk_0.clk" start="clk_0.clk"
end="reg_dp_offload_rx_hdr_dat.system" /> end="reg_dp_offload_rx_hdr_dat.system" />
<connection
kind="clock"
version="11.1"
start="clk_0.clk"
end="reg_dp_offload_tx_hdr_ovr.system" />
<connection <connection
kind="clock" kind="clock"
version="11.1" version="11.1"
...@@ -2940,6 +2977,52 @@ q]]></parameter> ...@@ -2940,6 +2977,52 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="reg_io_ddr.mem"> end="reg_io_ddr.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3120" /> <parameter name="baseAddress" value="0x3080" />
</connection>
<connection
kind="reset"
version="11.1"
start="clk_0.clk_reset"
end="reg_dp_offload_tx_1gbe.system_reset" />
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
end="reg_dp_offload_tx_1gbe.system_reset" />
<connection
kind="reset"
version="11.1"
start="clk_0.clk_reset"
end="reg_dp_offload_tx_1gbe_hdr_dat.system_reset" />
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
end="reg_dp_offload_tx_1gbe_hdr_dat.system_reset" />
<connection
kind="clock"
version="11.1"
start="clk_0.clk"
end="reg_dp_offload_tx_1gbe.system" />
<connection
kind="clock"
version="11.1"
start="clk_0.clk"
end="reg_dp_offload_tx_1gbe_hdr_dat.system" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="reg_dp_offload_tx_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0180" />
</connection>
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="reg_dp_offload_tx_1gbe_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x7000" />
</connection> </connection>
</system> </system>
boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+ 58
− 45
View file @ 86455877
...@@ -46,10 +46,12 @@ ENTITY mmm_unb1_test IS ...@@ -46,10 +46,12 @@ ENTITY mmm_unb1_test IS
g_sim : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O g_sim : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0; g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0; g_sim_node_nr : NATURAL := 0;
g_nof_streams_1GbE : NATURAL;
g_nof_streams_10GbE : NATURAL; g_nof_streams_10GbE : NATURAL;
g_nof_streams_ddr : NATURAL; g_nof_streams_ddr : NATURAL;
g_bg_block_size : NATURAL; g_bg_block_size : NATURAL;
g_hdr_field_arr : t_common_field_arr g_hdr_field_arr : t_common_field_arr;
g_nof_dp_offload_tx : NATURAL
); );
PORT ( PORT (
mm_rst : IN STD_LOGIC; mm_rst : IN STD_LOGIC;
...@@ -110,14 +112,11 @@ ENTITY mmm_unb1_test IS ...@@ -110,14 +112,11 @@ ENTITY mmm_unb1_test IS
reg_diag_bg_mosi : OUT t_mem_mosi; reg_diag_bg_mosi : OUT t_mem_mosi;
reg_diag_bg_miso : IN t_mem_miso; reg_diag_bg_miso : IN t_mem_miso;
reg_dp_offload_tx_mosi : OUT t_mem_mosi; reg_dp_offload_tx_mosi_arr : OUT t_mem_mosi_arr(g_nof_dp_offload_tx-1 DOWNTO 0);
reg_dp_offload_tx_miso : IN t_mem_miso; reg_dp_offload_tx_miso_arr : IN t_mem_miso_arr(g_nof_dp_offload_tx-1 DOWNTO 0);
reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi; reg_dp_offload_tx_hdr_dat_mosi_arr : OUT t_mem_mosi_arr(g_nof_dp_offload_tx-1 DOWNTO 0);
reg_dp_offload_tx_hdr_dat_miso : IN t_mem_miso; reg_dp_offload_tx_hdr_dat_miso_arr : IN t_mem_miso_arr(g_nof_dp_offload_tx-1 DOWNTO 0);
reg_dp_offload_tx_hdr_ovr_mosi : OUT t_mem_mosi;
reg_dp_offload_tx_hdr_ovr_miso : IN t_mem_miso;
reg_dp_offload_rx_hdr_dat_mosi : OUT t_mem_mosi; reg_dp_offload_rx_hdr_dat_mosi : OUT t_mem_mosi;
reg_dp_offload_rx_hdr_dat_miso : IN t_mem_miso; reg_dp_offload_rx_hdr_dat_miso : IN t_mem_miso;
...@@ -145,27 +144,23 @@ END mmm_unb1_test; ...@@ -145,27 +144,23 @@ END mmm_unb1_test;
ARCHITECTURE str OF mmm_unb1_test IS ARCHITECTURE str OF mmm_unb1_test IS
--FIXME CONSTANT g_nof_streams : NATURAL := g_nof_streams_1GbE + g_nof_streams_10GbE + g_nof_streams_ddr;
--CONSTANT g_nof_streams : NATURAL := g_nof_streams_10GbE + g_nof_streams_ddr; CONSTANT g_nof_streams_eth : NATURAL := g_nof_streams_1GbE + g_nof_streams_10GbE;
CONSTANT g_nof_streams : NATURAL := g_nof_streams_10GbE + 1;
-- Block generator -- Block generator
CONSTANT c_ram_diag_bg_addr_w : NATURAL := ceil_log2(g_nof_streams* pow2(ceil_log2(g_bg_block_size))); CONSTANT c_ram_diag_bg_addr_w : NATURAL := ceil_log2(g_nof_streams* pow2(ceil_log2(g_bg_block_size))); -- 5*10 --> 13
-- dp_offload -- dp_offload
CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb1_board_peripherals_mm_reg_default CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb1_board_peripherals_mm_reg_default
CONSTANT c_reg_dp_offload_tx_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_dp_offload_tx_adr_w)); CONSTANT c_reg_dp_offload_tx_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_eth * pow2(c_reg_dp_offload_tx_adr_w)); -- 4*1
CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w); CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words); CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words);
CONSTANT c_reg_dp_offload_tx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_dp_offload_tx_hdr_dat_adr_w)); CONSTANT c_reg_dp_offload_tx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_eth * pow2(c_reg_dp_offload_tx_hdr_dat_adr_w));
CONSTANT c_reg_dp_offload_tx_hdr_ovr_nof_words : NATURAL := g_hdr_field_arr'LENGTH;
CONSTANT c_reg_dp_offload_tx_hdr_ovr_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_ovr_nof_words);
CONSTANT c_reg_dp_offload_tx_hdr_ovr_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_dp_offload_tx_hdr_ovr_adr_w));
CONSTANT c_reg_dp_offload_rx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w); CONSTANT c_reg_dp_offload_rx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
CONSTANT c_reg_dp_offload_rx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_hdr_dat_nof_words); CONSTANT c_reg_dp_offload_rx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_hdr_dat_nof_words);
CONSTANT c_reg_dp_offload_rx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_dp_offload_rx_hdr_dat_adr_w)); CONSTANT c_reg_dp_offload_rx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_eth * pow2(c_reg_dp_offload_rx_hdr_dat_adr_w));
-- reorder -- reorder
-- v--- FIXME: g_frame_size_in -- v--- FIXME: g_frame_size_in
...@@ -180,7 +175,7 @@ ARCHITECTURE str OF mmm_unb1_test IS ...@@ -180,7 +175,7 @@ ARCHITECTURE str OF mmm_unb1_test IS
CONSTANT c_reg_tr_xaui_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_tr_xaui_adr_w)); CONSTANT c_reg_tr_xaui_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_tr_xaui_adr_w));
-- BSN monitors -- BSN monitors
CONSTANT c_reg_rsp_bsn_monitor_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w)); CONSTANT c_reg_rsp_bsn_monitor_adr_w : NATURAL := ceil_log2(g_nof_streams * pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
CONSTANT c_dp_reg_mm_nof_words : NATURAL := 1; CONSTANT c_dp_reg_mm_nof_words : NATURAL := 1;
...@@ -255,14 +250,20 @@ BEGIN ...@@ -255,14 +250,20 @@ BEGIN
u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG") u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso); PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
u_mm_file_reg_dp_offload_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_mosi, reg_dp_offload_tx_miso );
u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT") u_mm_file_reg_dp_offload_tx_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso ); PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_mosi_arr(1), reg_dp_offload_tx_miso_arr(1) );
u_mm_file_reg_dp_offload_tx_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_mosi_arr(0), reg_dp_offload_tx_miso_arr(0) );
u_mm_file_reg_dp_offload_tx_1_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi_arr(1), reg_dp_offload_tx_hdr_dat_miso_arr(1) );
u_mm_file_reg_dp_offload_tx_0_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT_1GBE")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi_arr(0), reg_dp_offload_tx_hdr_dat_miso_arr(0) );
u_mm_file_reg_dp_offload_tx_hdr_ovr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_OVR")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_ovr_mosi, reg_dp_offload_tx_hdr_ovr_miso );
u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT") u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso ); PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
...@@ -505,32 +506,44 @@ BEGIN ...@@ -505,32 +506,44 @@ BEGIN
ram_diag_bg_write_export => ram_diag_bg_mosi.wr, ram_diag_bg_write_export => ram_diag_bg_mosi.wr,
ram_diag_bg_writedata_export => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0), ram_diag_bg_writedata_export => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_offload_tx -- the_reg_dp_offload_tx
reg_dp_offload_tx_address_export => reg_dp_offload_tx_mosi.address(c_reg_dp_offload_tx_multi_adr_w-1 DOWNTO 0), reg_dp_offload_tx_address_export => reg_dp_offload_tx_mosi_arr(1).address(c_reg_dp_offload_tx_multi_adr_w-1 DOWNTO 0),
reg_dp_offload_tx_clk_export => OPEN, reg_dp_offload_tx_clk_export => OPEN,
reg_dp_offload_tx_read_export => reg_dp_offload_tx_mosi.rd, reg_dp_offload_tx_read_export => reg_dp_offload_tx_mosi_arr(1).rd,
reg_dp_offload_tx_readdata_export => reg_dp_offload_tx_miso.rddata(c_word_w-1 DOWNTO 0), reg_dp_offload_tx_readdata_export => reg_dp_offload_tx_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
reg_dp_offload_tx_reset_export => OPEN, reg_dp_offload_tx_reset_export => OPEN,
reg_dp_offload_tx_write_export => reg_dp_offload_tx_mosi.wr, reg_dp_offload_tx_write_export => reg_dp_offload_tx_mosi_arr(1).wr,
reg_dp_offload_tx_writedata_export => reg_dp_offload_tx_mosi.wrdata(c_word_w-1 DOWNTO 0), reg_dp_offload_tx_writedata_export => reg_dp_offload_tx_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_offload_tx_hdr_dat -- the_reg_dp_offload_tx_hdr_dat
reg_dp_offload_tx_hdr_dat_address_export => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w-1 DOWNTO 0), reg_dp_offload_tx_hdr_dat_address_export => reg_dp_offload_tx_hdr_dat_mosi_arr(1).address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w-1 DOWNTO 0),
reg_dp_offload_tx_hdr_dat_clk_export => OPEN, reg_dp_offload_tx_hdr_dat_clk_export => OPEN,
reg_dp_offload_tx_hdr_dat_read_export => reg_dp_offload_tx_hdr_dat_mosi.rd, reg_dp_offload_tx_hdr_dat_read_export => reg_dp_offload_tx_hdr_dat_mosi_arr(1).rd,
reg_dp_offload_tx_hdr_dat_readdata_export => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0), reg_dp_offload_tx_hdr_dat_readdata_export => reg_dp_offload_tx_hdr_dat_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
reg_dp_offload_tx_hdr_dat_reset_export => OPEN, reg_dp_offload_tx_hdr_dat_reset_export => OPEN,
reg_dp_offload_tx_hdr_dat_write_export => reg_dp_offload_tx_hdr_dat_mosi.wr, reg_dp_offload_tx_hdr_dat_write_export => reg_dp_offload_tx_hdr_dat_mosi_arr(1).wr,
reg_dp_offload_tx_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0), reg_dp_offload_tx_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_offload_tx_hdr_ovr
reg_dp_offload_tx_hdr_ovr_address_export => reg_dp_offload_tx_hdr_ovr_mosi.address(c_reg_dp_offload_tx_hdr_ovr_multi_adr_w-1 DOWNTO 0), -- the_reg_dp_offload_tx_1gbe
reg_dp_offload_tx_hdr_ovr_clk_export => OPEN, reg_dp_offload_tx_1gbe_address_export => reg_dp_offload_tx_mosi_arr(0).address(c_reg_dp_offload_tx_multi_adr_w-1 DOWNTO 0),
reg_dp_offload_tx_hdr_ovr_read_export => reg_dp_offload_tx_hdr_ovr_mosi.rd, reg_dp_offload_tx_1gbe_clk_export => OPEN,
reg_dp_offload_tx_hdr_ovr_readdata_export => reg_dp_offload_tx_hdr_ovr_miso.rddata(c_word_w-1 DOWNTO 0), reg_dp_offload_tx_1gbe_read_export => reg_dp_offload_tx_mosi_arr(0).rd,
reg_dp_offload_tx_hdr_ovr_reset_export => OPEN, reg_dp_offload_tx_1gbe_readdata_export => reg_dp_offload_tx_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
reg_dp_offload_tx_hdr_ovr_write_export => reg_dp_offload_tx_hdr_ovr_mosi.wr, reg_dp_offload_tx_1gbe_reset_export => OPEN,
reg_dp_offload_tx_hdr_ovr_writedata_export => reg_dp_offload_tx_hdr_ovr_mosi.wrdata(c_word_w-1 DOWNTO 0), reg_dp_offload_tx_1gbe_write_export => reg_dp_offload_tx_mosi_arr(0).wr,
reg_dp_offload_tx_1gbe_writedata_export => reg_dp_offload_tx_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_offload_tx_1gbe_hdr_dat
reg_dp_offload_tx_1gbe_hdr_dat_address_export => reg_dp_offload_tx_hdr_dat_mosi_arr(0).address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w-1 DOWNTO 0),
reg_dp_offload_tx_1gbe_hdr_dat_clk_export => OPEN,
reg_dp_offload_tx_1gbe_hdr_dat_read_export => reg_dp_offload_tx_hdr_dat_mosi_arr(0).rd,
reg_dp_offload_tx_1gbe_hdr_dat_readdata_export => reg_dp_offload_tx_hdr_dat_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
reg_dp_offload_tx_1gbe_hdr_dat_reset_export => OPEN,
reg_dp_offload_tx_1gbe_hdr_dat_write_export => reg_dp_offload_tx_hdr_dat_mosi_arr(0).wr,
reg_dp_offload_tx_1gbe_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_offload_rx_hdr_dat -- the_reg_dp_offload_rx_hdr_dat
reg_dp_offload_rx_hdr_dat_address_export => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0), reg_dp_offload_rx_hdr_dat_address_export => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0),
......
boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
+ 19
− 9
View file @ 86455877
...@@ -150,9 +150,10 @@ PACKAGE qsys_unb1_test_pkg IS ...@@ -150,9 +150,10 @@ PACKAGE qsys_unb1_test_pkg IS
reg_bsn_monitor_read_export : out std_logic; -- export reg_bsn_monitor_read_export : out std_logic; -- export
reg_bsn_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export reg_bsn_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_bsn_monitor_write_export : out std_logic; -- export reg_bsn_monitor_write_export : out std_logic; -- export
reg_bsn_monitor_address_export : out std_logic_vector(5 downto 0); -- export reg_bsn_monitor_address_export : out std_logic_vector(6 downto 0); -- export
reg_bsn_monitor_clk_export : out std_logic; -- export reg_bsn_monitor_clk_export : out std_logic; -- export
reg_bsn_monitor_reset_export : out std_logic; -- export reg_bsn_monitor_reset_export : out std_logic; -- export
reg_dp_offload_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export reg_dp_offload_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dp_offload_tx_read_export : out std_logic; -- export reg_dp_offload_tx_read_export : out std_logic; -- export
reg_dp_offload_tx_writedata_export : out std_logic_vector(31 downto 0); -- export reg_dp_offload_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
...@@ -167,6 +168,22 @@ PACKAGE qsys_unb1_test_pkg IS ...@@ -167,6 +168,22 @@ PACKAGE qsys_unb1_test_pkg IS
reg_dp_offload_tx_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export reg_dp_offload_tx_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
reg_dp_offload_tx_hdr_dat_clk_export : out std_logic; -- export reg_dp_offload_tx_hdr_dat_clk_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_reset_export : out std_logic; -- export reg_dp_offload_tx_hdr_dat_reset_export : out std_logic; -- export
reg_dp_offload_tx_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dp_offload_tx_1gbe_read_export : out std_logic; -- export
reg_dp_offload_tx_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_tx_1gbe_write_export : out std_logic; -- export
reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
reg_dp_offload_tx_1gbe_clk_export : out std_logic; -- export
reg_dp_offload_tx_1gbe_reset_export : out std_logic; -- export
reg_dp_offload_tx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dp_offload_tx_1gbe_hdr_dat_read_export : out std_logic; -- export
reg_dp_offload_tx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_tx_1gbe_hdr_dat_write_export : out std_logic; -- export
reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
reg_dp_offload_tx_1gbe_hdr_dat_clk_export : out std_logic; -- export
reg_dp_offload_tx_1gbe_hdr_dat_reset_export : out std_logic; -- export
reg_dp_offload_rx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export reg_dp_offload_rx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dp_offload_rx_hdr_dat_read_export : out std_logic; -- export reg_dp_offload_rx_hdr_dat_read_export : out std_logic; -- export
reg_dp_offload_rx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export reg_dp_offload_rx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
...@@ -174,13 +191,6 @@ PACKAGE qsys_unb1_test_pkg IS ...@@ -174,13 +191,6 @@ PACKAGE qsys_unb1_test_pkg IS
reg_dp_offload_rx_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export reg_dp_offload_rx_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
reg_dp_offload_rx_hdr_dat_clk_export : out std_logic; -- export reg_dp_offload_rx_hdr_dat_clk_export : out std_logic; -- export
reg_dp_offload_rx_hdr_dat_reset_export : out std_logic; -- export reg_dp_offload_rx_hdr_dat_reset_export : out std_logic; -- export
reg_dp_offload_tx_hdr_ovr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dp_offload_tx_hdr_ovr_read_export : out std_logic; -- export
reg_dp_offload_tx_hdr_ovr_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_tx_hdr_ovr_write_export : out std_logic; -- export
reg_dp_offload_tx_hdr_ovr_address_export : out std_logic_vector(6 downto 0); -- export
reg_dp_offload_tx_hdr_ovr_clk_export : out std_logic; -- export
reg_dp_offload_tx_hdr_ovr_reset_export : out std_logic; -- export
reg_diag_data_buffer_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export reg_diag_data_buffer_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_data_buffer_read_export : out std_logic; -- export reg_diag_data_buffer_read_export : out std_logic; -- export
reg_diag_data_buffer_writedata_export : out std_logic_vector(31 downto 0); -- export reg_diag_data_buffer_writedata_export : out std_logic_vector(31 downto 0); -- export
...@@ -206,7 +216,7 @@ PACKAGE qsys_unb1_test_pkg IS ...@@ -206,7 +216,7 @@ PACKAGE qsys_unb1_test_pkg IS
ram_diag_bg_read_export : out std_logic; -- export ram_diag_bg_read_export : out std_logic; -- export
ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_bg_write_export : out std_logic; -- export ram_diag_bg_write_export : out std_logic; -- export
ram_diag_bg_address_export : out std_logic_vector(11 downto 0); -- export ram_diag_bg_address_export : out std_logic_vector(12 downto 0); -- export
ram_diag_bg_clk_export : out std_logic; -- export ram_diag_bg_clk_export : out std_logic; -- export
ram_diag_bg_reset_export : out std_logic; -- export ram_diag_bg_reset_export : out std_logic; -- export
ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
......
boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+ 155
− 179
View file @ 86455877
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