diff --git a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
index 102a636744d821e25dbda308ec28773efaf811dd..7fed96c210203d094a569bf33673020a1b5998e6 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
+++ b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
@@ -65,59 +65,59 @@
          type = "String";
       }
    }
-   element reg_tr_10GbE.mem
+   element reg_dpmm_ctrl.mem
    {
       datum baseAddress
       {
-         value = "524288";
+         value = "12432";
          type = "long";
       }
    }
-   element reg_unb_sens.mem
+   element reg_dpmm_data.mem
    {
       datum baseAddress
       {
-         value = "12416";
+         value = "12440";
          type = "long";
       }
    }
-   element reg_diag_data_buffer.mem
+   element reg_mmdp_data.mem
    {
       datum baseAddress
       {
-         value = "128";
+         value = "12456";
          type = "long";
       }
    }
-   element reg_diag_bg.mem
+   element reg_dp_offload_rx_hdr_dat.mem
    {
       datum baseAddress
       {
-         value = "12544";
+         value = "1024";
          type = "long";
       }
    }
-   element pio_pps.mem
+   element reg_remu.mem
    {
       datum baseAddress
       {
-         value = "12624";
+         value = "12320";
          type = "long";
       }
    }
-   element reg_dp_offload_tx_hdr_dat.mem
+   element reg_unb_sens.mem
    {
       datum baseAddress
       {
-         value = "13312";
+         value = "480";
          type = "long";
       }
    }
-   element reg_epcs.mem
+   element reg_diag_bg.mem
    {
       datum baseAddress
       {
-         value = "12480";
+         value = "12384";
          type = "long";
       }
    }
@@ -129,113 +129,113 @@
          type = "long";
       }
    }
-   element reg_dpmm_data.mem
+   element pio_pps.mem
    {
       datum baseAddress
       {
-         value = "12600";
+         value = "12464";
          type = "long";
       }
    }
-   element reg_io_ddr.mem
+   element reg_dp_offload_tx.mem
    {
       datum baseAddress
       {
-         value = "12576";
+         value = "320";
          type = "long";
       }
    }
-   element rom_system_info.mem
+   element reg_diag_data_buffer.mem
    {
-      datum _lockedAddress
-      {
-         value = "1";
-         type = "boolean";
-      }
       datum baseAddress
       {
-         value = "4096";
+         value = "128";
          type = "long";
       }
    }
-   element reg_dp_offload_rx_hdr_dat.mem
+   element reg_dp_offload_tx_1gbe_hdr_dat.mem
    {
       datum baseAddress
       {
-         value = "1024";
+         value = "28672";
          type = "long";
       }
    }
-   element reg_dpmm_ctrl.mem
+   element reg_tr_10GbE.mem
    {
       datum baseAddress
       {
-         value = "12592";
+         value = "262144";
          type = "long";
       }
    }
-   element reg_mmdp_data.mem
+   element ram_diag_bg.mem
    {
       datum baseAddress
       {
-         value = "12616";
+         value = "32768";
          type = "long";
       }
    }
-   element reg_dp_offload_tx_hdr_ovr.mem
+   element ram_ss_ss_wide.mem
    {
       datum baseAddress
       {
-         value = "512";
+         value = "393216";
          type = "long";
       }
    }
-   element ram_diag_bg.mem
+   element pio_system_info.mem
    {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
       datum baseAddress
       {
-         value = "262144";
+         value = "0";
          type = "long";
       }
    }
-   element ram_diag_data_buffer.mem
+   element rom_system_info.mem
    {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
       datum baseAddress
       {
-         value = "65536";
+         value = "4096";
          type = "long";
       }
    }
-   element ram_ss_ss_wide.mem
+   element reg_io_ddr.mem
    {
       datum baseAddress
       {
-         value = "655360";
+         value = "12416";
          type = "long";
       }
    }
-   element reg_wdi.mem
+   element reg_dp_offload_tx_hdr_dat.mem
    {
-      datum _lockedAddress
-      {
-         value = "1";
-         type = "boolean";
-      }
       datum baseAddress
       {
-         value = "12288";
+         value = "13312";
          type = "long";
       }
    }
-   element reg_bsn_monitor.mem
+   element reg_epcs.mem
    {
       datum baseAddress
       {
-         value = "256";
+         value = "12352";
          type = "long";
       }
    }
-   element pio_system_info.mem
+   element reg_wdi.mem
    {
       datum _lockedAddress
       {
@@ -244,7 +244,15 @@
       }
       datum baseAddress
       {
-         value = "0";
+         value = "12288";
+         type = "long";
+      }
+   }
+   element reg_bsn_monitor.mem
+   {
+      datum baseAddress
+      {
+         value = "512";
          type = "long";
       }
    }
@@ -252,23 +260,23 @@
    {
       datum baseAddress
       {
-         value = "12608";
+         value = "12448";
          type = "long";
       }
    }
-   element reg_dp_offload_tx.mem
+   element ram_diag_data_buffer.mem
    {
       datum baseAddress
       {
-         value = "12512";
+         value = "65536";
          type = "long";
       }
    }
-   element reg_remu.mem
+   element reg_dp_offload_tx_1gbe.mem
    {
       datum baseAddress
       {
-         value = "12448";
+         value = "384";
          type = "long";
       }
    }
@@ -284,7 +292,7 @@
    {
       datum baseAddress
       {
-         value = "12352";
+         value = "256";
          type = "long";
       }
    }
@@ -342,7 +350,7 @@
    {
       datum _sortIndex
       {
-         value = "28";
+         value = "27";
          type = "int";
       }
    }
@@ -350,7 +358,7 @@
    {
       datum _sortIndex
       {
-         value = "26";
+         value = "25";
          type = "int";
       }
    }
@@ -358,7 +366,7 @@
    {
       datum _sortIndex
       {
-         value = "29";
+         value = "28";
          type = "int";
       }
    }
@@ -374,7 +382,7 @@
    {
       datum _sortIndex
       {
-         value = "27";
+         value = "26";
          type = "int";
       }
    }
@@ -382,7 +390,7 @@
    {
       datum _sortIndex
       {
-         value = "25";
+         value = "24";
          type = "int";
       }
    }
@@ -402,19 +410,27 @@
          type = "int";
       }
    }
-   element reg_dp_offload_tx_hdr_dat
+   element reg_dp_offload_tx_1gbe
    {
       datum _sortIndex
       {
-         value = "22";
+         value = "30";
          type = "int";
       }
    }
-   element reg_dp_offload_tx_hdr_ovr
+   element reg_dp_offload_tx_1gbe_hdr_dat
    {
       datum _sortIndex
       {
-         value = "24";
+         value = "31";
+         type = "int";
+      }
+   }
+   element reg_dp_offload_tx_hdr_dat
+   {
+      datum _sortIndex
+      {
+         value = "22";
          type = "int";
       }
    }
@@ -446,7 +462,7 @@
    {
       datum _sortIndex
       {
-         value = "30";
+         value = "29";
          type = "int";
       }
    }
@@ -514,6 +530,14 @@
          type = "int";
       }
    }
+   element pio_wdi.s1
+   {
+      datum baseAddress
+      {
+         value = "12304";
+         type = "long";
+      }
+   }
    element onchip_memory2_0.s1
    {
       datum _lockedAddress
@@ -527,19 +551,11 @@
          type = "long";
       }
    }
-   element pio_wdi.s1
-   {
-      datum baseAddress
-      {
-         value = "12304";
-         type = "long";
-      }
-   }
    element timer_0.s1
    {
       datum baseAddress
       {
-         value = "12320";
+         value = "448";
          type = "long";
       }
    }
@@ -566,7 +582,7 @@
  <parameter name="projectName" value="" />
  <parameter name="sopcBorderPoints" value="false" />
  <parameter name="systemHash" value="1" />
- <parameter name="timeStamp" value="1427787271744" />
+ <parameter name="timeStamp" value="1429017518755" />
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
  <interface
@@ -1664,41 +1680,6 @@
    internal="reg_dp_offload_rx_hdr_dat.reset"
    type="conduit"
    dir="end" />
- <interface
-   name="reg_dp_offload_tx_hdr_ovr_readdata"
-   internal="reg_dp_offload_tx_hdr_ovr.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_dp_offload_tx_hdr_ovr_read"
-   internal="reg_dp_offload_tx_hdr_ovr.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_dp_offload_tx_hdr_ovr_writedata"
-   internal="reg_dp_offload_tx_hdr_ovr.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_dp_offload_tx_hdr_ovr_write"
-   internal="reg_dp_offload_tx_hdr_ovr.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_dp_offload_tx_hdr_ovr_address"
-   internal="reg_dp_offload_tx_hdr_ovr.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_dp_offload_tx_hdr_ovr_clk"
-   internal="reg_dp_offload_tx_hdr_ovr.clk"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_dp_offload_tx_hdr_ovr_reset"
-   internal="reg_dp_offload_tx_hdr_ovr.reset"
-   type="conduit"
-   dir="end" />
  <interface
    name="reg_diag_data_buffer_readdata"
    internal="reg_diag_data_buffer.readdata"
@@ -1909,6 +1890,76 @@
    internal="reg_io_ddr.reset"
    type="conduit"
    dir="end" />
+ <interface
+   name="reg_dp_offload_tx_1gbe_readdata"
+   internal="reg_dp_offload_tx_1gbe.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_tx_1gbe_read"
+   internal="reg_dp_offload_tx_1gbe.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_tx_1gbe_writedata"
+   internal="reg_dp_offload_tx_1gbe.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_tx_1gbe_write"
+   internal="reg_dp_offload_tx_1gbe.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_tx_1gbe_address"
+   internal="reg_dp_offload_tx_1gbe.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_tx_1gbe_clk"
+   internal="reg_dp_offload_tx_1gbe.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_tx_1gbe_reset"
+   internal="reg_dp_offload_tx_1gbe.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_tx_1gbe_hdr_dat_readdata"
+   internal="reg_dp_offload_tx_1gbe_hdr_dat.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_tx_1gbe_hdr_dat_read"
+   internal="reg_dp_offload_tx_1gbe_hdr_dat.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_tx_1gbe_hdr_dat_writedata"
+   internal="reg_dp_offload_tx_1gbe_hdr_dat.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_tx_1gbe_hdr_dat_write"
+   internal="reg_dp_offload_tx_1gbe_hdr_dat.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_tx_1gbe_hdr_dat_address"
+   internal="reg_dp_offload_tx_1gbe_hdr_dat.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_tx_1gbe_hdr_dat_clk"
+   internal="reg_dp_offload_tx_1gbe_hdr_dat.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_tx_1gbe_hdr_dat_reset"
+   internal="reg_dp_offload_tx_1gbe_hdr_dat.reset"
+   type="conduit"
+   dir="end" />
  <module kind="clock_source" version="11.1" enabled="1" name="clk_0">
   <parameter name="clockFrequency" value="125000000" />
   <parameter name="clockFrequencyKnown" value="true" />
@@ -2139,7 +2190,7 @@ q]]></parameter>
   <parameter name="dcache_numTCDM" value="0" />
   <parameter name="dcache_lineSize" value="32" />
   <parameter name="instAddrWidth" value="18" />
-  <parameter name="dataAddrWidth" value="20" />
+  <parameter name="dataAddrWidth" value="19" />
   <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
   <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
   <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
@@ -2149,7 +2200,7 @@ q]]></parameter>
   <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
   <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
   <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='reg_bsn_monitor.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_unb_sens.mem' start='0x3080' end='0x30A0' /><slave name='reg_remu.mem' start='0x30A0' end='0x30C0' /><slave name='reg_epcs.mem' start='0x30C0' end='0x30E0' /><slave name='reg_dp_offload_tx.mem' start='0x30E0' end='0x3100' /><slave name='reg_diag_bg.mem' start='0x3100' end='0x3120' /><slave name='reg_io_ddr.mem' start='0x3120' end='0x3130' /><slave name='reg_dpmm_ctrl.mem' start='0x3130' end='0x3138' /><slave name='reg_dpmm_data.mem' start='0x3138' end='0x3140' /><slave name='reg_mmdp_ctrl.mem' start='0x3140' end='0x3148' /><slave name='reg_mmdp_data.mem' start='0x3148' end='0x3150' /><slave name='pio_pps.mem' start='0x3150' end='0x3158' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_bg.mem' start='0x40000' end='0x80000' /><slave name='reg_tr_10GbE.mem' start='0x80000' end='0xA0000' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' /></address-map>]]></parameter>
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='avs_eth_0.mms_reg' start='0x100' end='0x140' /><slave name='reg_dp_offload_tx.mem' start='0x140' end='0x180' /><slave name='reg_dp_offload_tx_1gbe.mem' start='0x180' end='0x1C0' /><slave name='timer_0.s1' start='0x1C0' end='0x1E0' /><slave name='reg_unb_sens.mem' start='0x1E0' end='0x200' /><slave name='reg_bsn_monitor.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='reg_remu.mem' start='0x3020' end='0x3040' /><slave name='reg_epcs.mem' start='0x3040' end='0x3060' /><slave name='reg_diag_bg.mem' start='0x3060' end='0x3080' /><slave name='reg_io_ddr.mem' start='0x3080' end='0x3090' /><slave name='reg_dpmm_ctrl.mem' start='0x3090' end='0x3098' /><slave name='reg_dpmm_data.mem' start='0x3098' end='0x30A0' /><slave name='reg_mmdp_ctrl.mem' start='0x30A0' end='0x30A8' /><slave name='reg_mmdp_data.mem' start='0x30A8' end='0x30B0' /><slave name='pio_pps.mem' start='0x30B0' end='0x30B8' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='reg_dp_offload_tx_1gbe_hdr_dat.mem' start='0x7000' end='0x7400' /><slave name='ram_diag_bg.mem' start='0x8000' end='0x10000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' /></address-map>]]></parameter>
   <parameter name="clockFrequency" value="125000000" />
   <parameter name="deviceFamilyName" value="Stratix IV" />
   <parameter name="internalIrqMaskSystemInfo" value="7" />
@@ -2165,7 +2216,7 @@ q]]></parameter>
   <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
  </module>
  <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_bsn_monitor">
-  <parameter name="g_adr_w" value="6" />
+  <parameter name="g_adr_w" value="7" />
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
@@ -2174,7 +2225,7 @@ q]]></parameter>
    version="1.0"
    enabled="1"
    name="reg_dp_offload_tx">
-  <parameter name="g_adr_w" value="3" />
+  <parameter name="g_adr_w" value="4" />
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
@@ -2196,15 +2247,6 @@ q]]></parameter>
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
- <module
-   kind="avs_common_mm"
-   version="1.0"
-   enabled="1"
-   name="reg_dp_offload_tx_hdr_ovr">
-  <parameter name="g_adr_w" value="7" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- </module>
  <module
    kind="avs_common_mm"
    version="1.0"
@@ -2229,7 +2271,7 @@ q]]></parameter>
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
  <module kind="avs_common_mm" version="1.0" enabled="1" name="ram_diag_bg">
-  <parameter name="g_adr_w" value="16" />
+  <parameter name="g_adr_w" value="13" />
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
@@ -2243,6 +2285,24 @@ q]]></parameter>
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
  </module>
+ <module
+   kind="avs_common_mm"
+   version="1.0"
+   enabled="1"
+   name="reg_dp_offload_tx_1gbe">
+  <parameter name="g_adr_w" value="4" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+   kind="avs_common_mm"
+   version="1.0"
+   enabled="1"
+   name="reg_dp_offload_tx_1gbe_hdr_dat">
+  <parameter name="g_adr_w" value="8" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
  <connection
    kind="avalon"
    version="11.1"
@@ -2304,7 +2364,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="timer_0.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3020" />
+  <parameter name="baseAddress" value="0x01c0" />
  </connection>
  <connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq">
   <parameter name="irqNumber" value="1" />
@@ -2315,7 +2375,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_unb_sens.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3080" />
+  <parameter name="baseAddress" value="0x01e0" />
  </connection>
  <connection
    kind="avalon"
@@ -2347,7 +2407,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_remu.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30a0" />
+  <parameter name="baseAddress" value="0x3020" />
  </connection>
  <connection
    kind="avalon"
@@ -2355,7 +2415,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_dpmm_ctrl.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3130" />
+  <parameter name="baseAddress" value="0x3090" />
  </connection>
  <connection
    kind="avalon"
@@ -2363,7 +2423,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_dpmm_data.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3138" />
+  <parameter name="baseAddress" value="0x3098" />
  </connection>
  <connection
    kind="avalon"
@@ -2371,7 +2431,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_mmdp_ctrl.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3140" />
+  <parameter name="baseAddress" value="0x30a0" />
  </connection>
  <connection
    kind="avalon"
@@ -2379,7 +2439,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_mmdp_data.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3148" />
+  <parameter name="baseAddress" value="0x30a8" />
  </connection>
  <connection
    kind="avalon"
@@ -2387,7 +2447,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_epcs.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30c0" />
+  <parameter name="baseAddress" value="0x3040" />
  </connection>
  <connection
    kind="avalon"
@@ -2395,7 +2455,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="pio_pps.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3150" />
+  <parameter name="baseAddress" value="0x30b0" />
  </connection>
  <connection
    kind="avalon"
@@ -2403,7 +2463,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_tr_10GbE.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00080000" />
+  <parameter name="baseAddress" value="0x00040000" />
  </connection>
  <connection
    kind="avalon"
@@ -2419,7 +2479,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="avs_eth_0.mms_reg">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3040" />
+  <parameter name="baseAddress" value="0x0100" />
  </connection>
  <connection
    kind="avalon"
@@ -2645,7 +2705,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_bsn_monitor.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0100" />
+  <parameter name="baseAddress" value="0x0200" />
  </connection>
  <connection
    kind="reset"
@@ -2696,7 +2756,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_dp_offload_tx.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30e0" />
+  <parameter name="baseAddress" value="0x0140" />
  </connection>
  <connection
    kind="avalon"
@@ -2706,14 +2766,6 @@ q]]></parameter>
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x3400" />
  </connection>
- <connection
-   kind="avalon"
-   version="11.1"
-   start="cpu_0.data_master"
-   end="reg_dp_offload_tx_hdr_ovr.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0200" />
- </connection>
  <connection
    kind="avalon"
    version="11.1"
@@ -2730,11 +2782,6 @@ q]]></parameter>
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x00010000" />
  </connection>
- <connection
-   kind="reset"
-   version="11.1"
-   start="cpu_0.jtag_debug_module_reset"
-   end="reg_dp_offload_tx_hdr_ovr.system_reset" />
  <connection
    kind="reset"
    version="11.1"
@@ -2745,11 +2792,6 @@ q]]></parameter>
    version="11.1"
    start="cpu_0.jtag_debug_module_reset"
    end="ram_diag_data_buffer.system_reset" />
- <connection
-   kind="reset"
-   version="11.1"
-   start="clk_0.clk_reset"
-   end="reg_dp_offload_tx_hdr_ovr.system_reset" />
  <connection
    kind="reset"
    version="11.1"
@@ -2766,7 +2808,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_diag_bg.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3100" />
+  <parameter name="baseAddress" value="0x3060" />
  </connection>
  <connection
    kind="avalon"
@@ -2774,7 +2816,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="ram_diag_bg.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00040000" />
+  <parameter name="baseAddress" value="0x8000" />
  </connection>
  <connection
    kind="reset"
@@ -2812,7 +2854,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="ram_ss_ss_wide.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x000a0000" />
+  <parameter name="baseAddress" value="0x00060000" />
  </connection>
  <connection kind="clock" version="11.1" start="clk_0.clk" end="cpu_0.clk" />
  <connection
@@ -2893,11 +2935,6 @@ q]]></parameter>
    version="11.1"
    start="clk_0.clk"
    end="reg_dp_offload_rx_hdr_dat.system" />
- <connection
-   kind="clock"
-   version="11.1"
-   start="clk_0.clk"
-   end="reg_dp_offload_tx_hdr_ovr.system" />
  <connection
    kind="clock"
    version="11.1"
@@ -2940,6 +2977,52 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_io_ddr.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3120" />
+  <parameter name="baseAddress" value="0x3080" />
+ </connection>
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_0.clk_reset"
+   end="reg_dp_offload_tx_1gbe.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="reg_dp_offload_tx_1gbe.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_0.clk_reset"
+   end="reg_dp_offload_tx_1gbe_hdr_dat.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="reg_dp_offload_tx_1gbe_hdr_dat.system_reset" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="clk_0.clk"
+   end="reg_dp_offload_tx_1gbe.system" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="clk_0.clk"
+   end="reg_dp_offload_tx_1gbe_hdr_dat.system" />
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="reg_dp_offload_tx_1gbe.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0180" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="reg_dp_offload_tx_1gbe_hdr_dat.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x7000" />
  </connection>
 </system>
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 02bed12f68e34436940ff1d88bde9a26f0559a68..72b41764928565691643720850902642d6bbf974 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -46,10 +46,12 @@ ENTITY mmm_unb1_test IS
     g_sim               : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O
     g_sim_unb_nr        : NATURAL := 0;
     g_sim_node_nr       : NATURAL := 0;
+    g_nof_streams_1GbE  : NATURAL;
     g_nof_streams_10GbE : NATURAL;
     g_nof_streams_ddr   : NATURAL;
     g_bg_block_size     : NATURAL;
-    g_hdr_field_arr     : t_common_field_arr
+    g_hdr_field_arr     : t_common_field_arr;
+    g_nof_dp_offload_tx : NATURAL
   );
   PORT (
     mm_rst                         : IN  STD_LOGIC;
@@ -110,14 +112,11 @@ ENTITY mmm_unb1_test IS
     reg_diag_bg_mosi               : OUT t_mem_mosi;
     reg_diag_bg_miso               : IN  t_mem_miso;
 
-    reg_dp_offload_tx_mosi         : OUT t_mem_mosi;
-    reg_dp_offload_tx_miso         : IN  t_mem_miso;
+    reg_dp_offload_tx_mosi_arr         : OUT t_mem_mosi_arr(g_nof_dp_offload_tx-1 DOWNTO 0);
+    reg_dp_offload_tx_miso_arr         : IN  t_mem_miso_arr(g_nof_dp_offload_tx-1 DOWNTO 0);
 
-    reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
-    reg_dp_offload_tx_hdr_dat_miso : IN  t_mem_miso;
-
-    reg_dp_offload_tx_hdr_ovr_mosi : OUT t_mem_mosi;
-    reg_dp_offload_tx_hdr_ovr_miso : IN  t_mem_miso;
+    reg_dp_offload_tx_hdr_dat_mosi_arr : OUT t_mem_mosi_arr(g_nof_dp_offload_tx-1 DOWNTO 0);
+    reg_dp_offload_tx_hdr_dat_miso_arr : IN  t_mem_miso_arr(g_nof_dp_offload_tx-1 DOWNTO 0);
 
     reg_dp_offload_rx_hdr_dat_mosi : OUT t_mem_mosi;
     reg_dp_offload_rx_hdr_dat_miso : IN  t_mem_miso;
@@ -145,27 +144,23 @@ END mmm_unb1_test;
 
 ARCHITECTURE str OF mmm_unb1_test IS
 
---FIXME
-  --CONSTANT g_nof_streams                           : NATURAL := g_nof_streams_10GbE + g_nof_streams_ddr;
-  CONSTANT g_nof_streams                           : NATURAL := g_nof_streams_10GbE + 1;
+  CONSTANT g_nof_streams                           : NATURAL := g_nof_streams_1GbE + g_nof_streams_10GbE + g_nof_streams_ddr;
+  CONSTANT g_nof_streams_eth                       : NATURAL := g_nof_streams_1GbE + g_nof_streams_10GbE;
+
   -- Block generator
-  CONSTANT c_ram_diag_bg_addr_w                    : NATURAL := ceil_log2(g_nof_streams* pow2(ceil_log2(g_bg_block_size)));
+  CONSTANT c_ram_diag_bg_addr_w                    : NATURAL := ceil_log2(g_nof_streams* pow2(ceil_log2(g_bg_block_size))); -- 5*10 --> 13
 
   -- dp_offload
   CONSTANT c_reg_dp_offload_tx_adr_w               : NATURAL := 1; -- Dev note: add to c_unb1_board_peripherals_mm_reg_default
-  CONSTANT c_reg_dp_offload_tx_multi_adr_w         : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_dp_offload_tx_adr_w));
+  CONSTANT c_reg_dp_offload_tx_multi_adr_w         : NATURAL := ceil_log2(g_nof_streams_eth * pow2(c_reg_dp_offload_tx_adr_w)); -- 4*1
 
   CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words   : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
   CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w       : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words);
-  CONSTANT c_reg_dp_offload_tx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_dp_offload_tx_hdr_dat_adr_w));
-
-  CONSTANT c_reg_dp_offload_tx_hdr_ovr_nof_words   : NATURAL := g_hdr_field_arr'LENGTH;
-  CONSTANT c_reg_dp_offload_tx_hdr_ovr_adr_w       : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_ovr_nof_words);
-  CONSTANT c_reg_dp_offload_tx_hdr_ovr_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_dp_offload_tx_hdr_ovr_adr_w));
+  CONSTANT c_reg_dp_offload_tx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_eth * pow2(c_reg_dp_offload_tx_hdr_dat_adr_w));
 
   CONSTANT c_reg_dp_offload_rx_hdr_dat_nof_words   : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
   CONSTANT c_reg_dp_offload_rx_hdr_dat_adr_w       : NATURAL := ceil_log2(c_reg_dp_offload_rx_hdr_dat_nof_words);
-  CONSTANT c_reg_dp_offload_rx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_dp_offload_rx_hdr_dat_adr_w));
+  CONSTANT c_reg_dp_offload_rx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_eth * pow2(c_reg_dp_offload_rx_hdr_dat_adr_w));
 
   -- reorder
   --                                                                       v--- FIXME: g_frame_size_in
@@ -180,7 +175,7 @@ ARCHITECTURE str OF mmm_unb1_test IS
   CONSTANT c_reg_tr_xaui_multi_adr_w               : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_tr_xaui_adr_w));
 
   -- BSN monitors
-  CONSTANT c_reg_rsp_bsn_monitor_adr_w             : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
+  CONSTANT c_reg_rsp_bsn_monitor_adr_w             : NATURAL := ceil_log2(g_nof_streams * pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
 
 
   CONSTANT c_dp_reg_mm_nof_words       : NATURAL := 1;
@@ -255,14 +250,20 @@ BEGIN
     u_mm_file_ram_diag_bg               : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
                                                      PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
 
-    u_mm_file_reg_dp_offload_tx         : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX")
-                                                     PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_mosi, reg_dp_offload_tx_miso );
 
-    u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
-                                                     PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
+    u_mm_file_reg_dp_offload_tx_1       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX")
+                                                     PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_mosi_arr(1), reg_dp_offload_tx_miso_arr(1) );
+
+    u_mm_file_reg_dp_offload_tx_0       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
+                                                     PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_mosi_arr(0), reg_dp_offload_tx_miso_arr(0) );
+
+
+    u_mm_file_reg_dp_offload_tx_1_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
+                                                     PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi_arr(1), reg_dp_offload_tx_hdr_dat_miso_arr(1) );
+
+    u_mm_file_reg_dp_offload_tx_0_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT_1GBE")
+                                                     PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi_arr(0), reg_dp_offload_tx_hdr_dat_miso_arr(0) );
 
-    u_mm_file_reg_dp_offload_tx_hdr_ovr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_OVR")
-                                                     PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_ovr_mosi, reg_dp_offload_tx_hdr_ovr_miso );
 
     u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
                                                      PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
@@ -505,32 +506,44 @@ BEGIN
       ram_diag_bg_write_export                      => ram_diag_bg_mosi.wr,
       ram_diag_bg_writedata_export                  => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
 
+
       -- the_reg_dp_offload_tx
-      reg_dp_offload_tx_address_export              => reg_dp_offload_tx_mosi.address(c_reg_dp_offload_tx_multi_adr_w-1 DOWNTO 0),
+      reg_dp_offload_tx_address_export              => reg_dp_offload_tx_mosi_arr(1).address(c_reg_dp_offload_tx_multi_adr_w-1 DOWNTO 0),
       reg_dp_offload_tx_clk_export                  => OPEN,
-      reg_dp_offload_tx_read_export                 => reg_dp_offload_tx_mosi.rd,
-      reg_dp_offload_tx_readdata_export             => reg_dp_offload_tx_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_dp_offload_tx_read_export                 => reg_dp_offload_tx_mosi_arr(1).rd,
+      reg_dp_offload_tx_readdata_export             => reg_dp_offload_tx_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
       reg_dp_offload_tx_reset_export                => OPEN,
-      reg_dp_offload_tx_write_export                => reg_dp_offload_tx_mosi.wr,
-      reg_dp_offload_tx_writedata_export            => reg_dp_offload_tx_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_dp_offload_tx_write_export                => reg_dp_offload_tx_mosi_arr(1).wr,
+      reg_dp_offload_tx_writedata_export            => reg_dp_offload_tx_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
 
       -- the_reg_dp_offload_tx_hdr_dat
-      reg_dp_offload_tx_hdr_dat_address_export      => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w-1 DOWNTO 0),
+      reg_dp_offload_tx_hdr_dat_address_export      => reg_dp_offload_tx_hdr_dat_mosi_arr(1).address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w-1 DOWNTO 0),
       reg_dp_offload_tx_hdr_dat_clk_export          => OPEN,
-      reg_dp_offload_tx_hdr_dat_read_export         => reg_dp_offload_tx_hdr_dat_mosi.rd,
-      reg_dp_offload_tx_hdr_dat_readdata_export     => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_dp_offload_tx_hdr_dat_read_export         => reg_dp_offload_tx_hdr_dat_mosi_arr(1).rd,
+      reg_dp_offload_tx_hdr_dat_readdata_export     => reg_dp_offload_tx_hdr_dat_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
       reg_dp_offload_tx_hdr_dat_reset_export        => OPEN,
-      reg_dp_offload_tx_hdr_dat_write_export        => reg_dp_offload_tx_hdr_dat_mosi.wr,
-      reg_dp_offload_tx_hdr_dat_writedata_export    => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-      -- the_reg_dp_offload_tx_hdr_ovr
-      reg_dp_offload_tx_hdr_ovr_address_export      => reg_dp_offload_tx_hdr_ovr_mosi.address(c_reg_dp_offload_tx_hdr_ovr_multi_adr_w-1 DOWNTO 0),
-      reg_dp_offload_tx_hdr_ovr_clk_export          => OPEN,
-      reg_dp_offload_tx_hdr_ovr_read_export         => reg_dp_offload_tx_hdr_ovr_mosi.rd,
-      reg_dp_offload_tx_hdr_ovr_readdata_export     => reg_dp_offload_tx_hdr_ovr_miso.rddata(c_word_w-1 DOWNTO 0),
-      reg_dp_offload_tx_hdr_ovr_reset_export        => OPEN,
-      reg_dp_offload_tx_hdr_ovr_write_export        => reg_dp_offload_tx_hdr_ovr_mosi.wr,
-      reg_dp_offload_tx_hdr_ovr_writedata_export    => reg_dp_offload_tx_hdr_ovr_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_dp_offload_tx_hdr_dat_write_export        => reg_dp_offload_tx_hdr_dat_mosi_arr(1).wr,
+      reg_dp_offload_tx_hdr_dat_writedata_export    => reg_dp_offload_tx_hdr_dat_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
+
+
+      -- the_reg_dp_offload_tx_1gbe
+      reg_dp_offload_tx_1gbe_address_export              => reg_dp_offload_tx_mosi_arr(0).address(c_reg_dp_offload_tx_multi_adr_w-1 DOWNTO 0),
+      reg_dp_offload_tx_1gbe_clk_export                  => OPEN,
+      reg_dp_offload_tx_1gbe_read_export                 => reg_dp_offload_tx_mosi_arr(0).rd,
+      reg_dp_offload_tx_1gbe_readdata_export             => reg_dp_offload_tx_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
+      reg_dp_offload_tx_1gbe_reset_export                => OPEN,
+      reg_dp_offload_tx_1gbe_write_export                => reg_dp_offload_tx_mosi_arr(0).wr,
+      reg_dp_offload_tx_1gbe_writedata_export            => reg_dp_offload_tx_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
+
+      -- the_reg_dp_offload_tx_1gbe_hdr_dat
+      reg_dp_offload_tx_1gbe_hdr_dat_address_export      => reg_dp_offload_tx_hdr_dat_mosi_arr(0).address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w-1 DOWNTO 0),
+      reg_dp_offload_tx_1gbe_hdr_dat_clk_export          => OPEN,
+      reg_dp_offload_tx_1gbe_hdr_dat_read_export         => reg_dp_offload_tx_hdr_dat_mosi_arr(0).rd,
+      reg_dp_offload_tx_1gbe_hdr_dat_readdata_export     => reg_dp_offload_tx_hdr_dat_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
+      reg_dp_offload_tx_1gbe_hdr_dat_reset_export        => OPEN,
+      reg_dp_offload_tx_1gbe_hdr_dat_write_export        => reg_dp_offload_tx_hdr_dat_mosi_arr(0).wr,
+      reg_dp_offload_tx_1gbe_hdr_dat_writedata_export    => reg_dp_offload_tx_hdr_dat_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
+
 
       -- the_reg_dp_offload_rx_hdr_dat
       reg_dp_offload_rx_hdr_dat_address_export      => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0),
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
index bc766fbea91214b65068579100339730f4782347..99f3a4ba822744f480fb8ca39054b05c4253030a 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
@@ -150,9 +150,10 @@ PACKAGE qsys_unb1_test_pkg IS
             reg_bsn_monitor_read_export                   : out std_logic;                                        -- export
             reg_bsn_monitor_writedata_export              : out std_logic_vector(31 downto 0);                    -- export
             reg_bsn_monitor_write_export                  : out std_logic;                                        -- export
-            reg_bsn_monitor_address_export                : out std_logic_vector(5 downto 0);                     -- export
+            reg_bsn_monitor_address_export                : out std_logic_vector(6 downto 0);                     -- export
             reg_bsn_monitor_clk_export                    : out std_logic;                                        -- export
             reg_bsn_monitor_reset_export                  : out std_logic;                                        -- export
+
             reg_dp_offload_tx_readdata_export             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
             reg_dp_offload_tx_read_export                 : out std_logic;                                        -- export
             reg_dp_offload_tx_writedata_export            : out std_logic_vector(31 downto 0);                    -- export
@@ -167,6 +168,22 @@ PACKAGE qsys_unb1_test_pkg IS
             reg_dp_offload_tx_hdr_dat_address_export      : out std_logic_vector(7 downto 0);                     -- export
             reg_dp_offload_tx_hdr_dat_clk_export          : out std_logic;                                        -- export
             reg_dp_offload_tx_hdr_dat_reset_export        : out std_logic;                                        -- export
+
+            reg_dp_offload_tx_1gbe_readdata_export             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dp_offload_tx_1gbe_read_export                 : out std_logic;                                        -- export
+            reg_dp_offload_tx_1gbe_writedata_export            : out std_logic_vector(31 downto 0);                    -- export
+            reg_dp_offload_tx_1gbe_write_export                : out std_logic;                                        -- export
+            reg_dp_offload_tx_1gbe_address_export              : out std_logic_vector(2 downto 0);                     -- export
+            reg_dp_offload_tx_1gbe_clk_export                  : out std_logic;                                        -- export
+            reg_dp_offload_tx_1gbe_reset_export                : out std_logic;                                        -- export
+            reg_dp_offload_tx_1gbe_hdr_dat_readdata_export     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dp_offload_tx_1gbe_hdr_dat_read_export         : out std_logic;                                        -- export
+            reg_dp_offload_tx_1gbe_hdr_dat_writedata_export    : out std_logic_vector(31 downto 0);                    -- export
+            reg_dp_offload_tx_1gbe_hdr_dat_write_export        : out std_logic;                                        -- export
+            reg_dp_offload_tx_1gbe_hdr_dat_address_export      : out std_logic_vector(7 downto 0);                     -- export
+            reg_dp_offload_tx_1gbe_hdr_dat_clk_export          : out std_logic;                                        -- export
+            reg_dp_offload_tx_1gbe_hdr_dat_reset_export        : out std_logic;                                        -- export
+
             reg_dp_offload_rx_hdr_dat_readdata_export     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
             reg_dp_offload_rx_hdr_dat_read_export         : out std_logic;                                        -- export
             reg_dp_offload_rx_hdr_dat_writedata_export    : out std_logic_vector(31 downto 0);                    -- export
@@ -174,13 +191,6 @@ PACKAGE qsys_unb1_test_pkg IS
             reg_dp_offload_rx_hdr_dat_address_export      : out std_logic_vector(7 downto 0);                     -- export
             reg_dp_offload_rx_hdr_dat_clk_export          : out std_logic;                                        -- export
             reg_dp_offload_rx_hdr_dat_reset_export        : out std_logic;                                        -- export
-            reg_dp_offload_tx_hdr_ovr_readdata_export     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_dp_offload_tx_hdr_ovr_read_export         : out std_logic;                                        -- export
-            reg_dp_offload_tx_hdr_ovr_writedata_export    : out std_logic_vector(31 downto 0);                    -- export
-            reg_dp_offload_tx_hdr_ovr_write_export        : out std_logic;                                        -- export
-            reg_dp_offload_tx_hdr_ovr_address_export      : out std_logic_vector(6 downto 0);                     -- export
-            reg_dp_offload_tx_hdr_ovr_clk_export          : out std_logic;                                        -- export
-            reg_dp_offload_tx_hdr_ovr_reset_export        : out std_logic;                                        -- export
             reg_diag_data_buffer_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
             reg_diag_data_buffer_read_export              : out std_logic;                                        -- export
             reg_diag_data_buffer_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
@@ -206,7 +216,7 @@ PACKAGE qsys_unb1_test_pkg IS
             ram_diag_bg_read_export                       : out std_logic;                                        -- export
             ram_diag_bg_writedata_export                  : out std_logic_vector(31 downto 0);                    -- export
             ram_diag_bg_write_export                      : out std_logic;                                        -- export
-            ram_diag_bg_address_export                    : out std_logic_vector(11 downto 0);                     -- export
+            ram_diag_bg_address_export                    : out std_logic_vector(12 downto 0);                     -- export
             ram_diag_bg_clk_export                        : out std_logic;                                        -- export
             ram_diag_bg_reset_export                      : out std_logic;                                        -- export
             ram_ss_ss_wide_address_export                 : out std_logic_vector(13 downto 0);                     -- export
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index bf0714f790e55e2bfff88831a8cd8bc1f53ac0f2..383e8572780282a610744f42bb41c621a7d522d9 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -1,6 +1,6 @@
 -------------------------------------------------------------------------------
 --
--- Copyright (C) 2012
+-- Copyright (C) 2014-2015
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -119,12 +119,10 @@ END unb1_test;
 ARCHITECTURE str OF unb1_test IS
 
   -- Firmware version x.y
-  CONSTANT c_fw_version             : t_unb1_board_fw_version := (1, 1);
-
-  CONSTANT c_use_front              : BOOLEAN := TRUE; --c_design_name(1 TO 2)="fn"; -- FIXME
-  CONSTANT c_use_back               : BOOLEAN := FALSE; --c_design_name(1 TO 2)="bn"; -- FIXME
-  CONSTANT c_use_pc_target          : BOOLEAN := TRUE;
+  CONSTANT c_fw_version             : t_unb1_board_fw_version := (1, 2);
 
+  CONSTANT c_use_front              : BOOLEAN := TRUE;  -- connect SI_FN_[0..2]
+  CONSTANT c_use_back               : BOOLEAN := FALSE; -- however SI_FN_[0..2] do connect to copper connectors of single board unb
 
   -- In simulation we don't need the 1GbE core for MM control, deselect it in c_use_phy based on g_sim
   CONSTANT c_use_phy                : t_c_unb1_board_use_phy  := (sel_a_b(g_sim, 0, 1), 
@@ -138,15 +136,17 @@ ARCHITECTURE str OF unb1_test IS
   CONSTANT c_lpbk_data_w                : NATURAL := 32; -- 128 c_eth_data_w, c_xgmii_data_w
 
   -- Revision controlled constants
-  CONSTANT c_use_lpbk                   : BOOLEAN := g_design_name = "unb1_test_lpbk";
-  CONSTANT c_use_1GbE                   : BOOLEAN := g_design_name = "unb1_test_1GbE";
-  CONSTANT c_use_10GbE                  : BOOLEAN := g_design_name = "unb1_test_10GbE";
+  CONSTANT c_use_lpbk                   : BOOLEAN := FALSE;--g_design_name = "unb1_test_lpbk";
+  CONSTANT c_use_1GbE                   : BOOLEAN := TRUE;--g_design_name = "unb1_test_1GbE";
+  CONSTANT c_use_10GbE                  : BOOLEAN := TRUE;--g_design_name = "unb1_test_10GbE";
   CONSTANT c_nof_streams_10GbE          : NATURAL := 3;
+  CONSTANT c_nof_streams_1GbE           : NATURAL := 1;
   CONSTANT c_nof_streams_ddr            : NATURAL := 1; --2
-  CONSTANT c_nof_streams                : NATURAL := c_nof_streams_10GbE + c_nof_streams_ddr;
-  CONSTANT c_data_w                     : NATURAL := sel_a_b(c_use_lpbk,  c_lpbk_data_w, -- Select correct c_data_w when one interface is used
-                                                     sel_a_b(c_use_1GbE,  c_eth_data_w,
-                                                     sel_a_b(c_use_10GbE, c_xgmii_data_w, 0)));
+  CONSTANT c_nof_streams                : NATURAL := c_nof_streams_1GbE + c_nof_streams_10GbE + c_nof_streams_ddr;
+  CONSTANT c_nof_streams_eth            : NATURAL := c_nof_streams_1GbE + c_nof_streams_10GbE;
+  CONSTANT c_data_w                     : NATURAL := c_xgmii_data_w;--sel_a_b(c_use_lpbk,  c_lpbk_data_w, -- Select correct c_data_w when one interface is used
+                                                     --sel_a_b(c_use_1GbE,  c_eth_data_w,
+                                                     --sel_a_b(c_use_10GbE, c_xgmii_data_w, 0)));
 
 
   -- ddr
@@ -215,14 +215,13 @@ ARCHITECTURE str OF unb1_test IS
   CONSTANT c_max_udp_payload_nof_words  : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w;
   CONSTANT c_max_nof_words_per_block    : NATURAL := c_bg_block_size;
   CONSTANT c_min_nof_words_per_block    : NATURAL := 1;
-  CONSTANT c_def_nof_words_per_block    : NATURAL := sel_a_b(c_use_1GbE,  c_def_1GbE_block_size,
-                                                     sel_a_b(c_use_10GbE, c_def_10GbE_block_size,
-                                                     c_bg_block_size));
   CONSTANT c_max_nof_blocks_per_packet  : NATURAL := c_max_udp_payload_nof_words/c_min_nof_words_per_block;
   CONSTANT c_def_nof_blocks_per_packet  : NATURAL := 1;
 
-  SIGNAL hdr_fields_in_arr              : t_slv_1024_arr(c_nof_streams_10GbE-1 DOWNTO 0);
-  SIGNAL hdr_fields_out_arr             : t_slv_1024_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+  CONSTANT c_nof_dp_offload_tx          : NATURAL := 2; -- 1 set 1GbE + 1 set 10GbE
+
+  SIGNAL hdr_fields_in_arr              : t_slv_1024_arr(c_nof_streams_eth-1 DOWNTO 0);
+  SIGNAL hdr_fields_out_arr             : t_slv_1024_arr(c_nof_streams_eth-1 DOWNTO 0);
 
 
 
@@ -323,10 +322,10 @@ ARCHITECTURE str OF unb1_test IS
   SIGNAL ram_diag_bg_mosi               : t_mem_mosi;
   SIGNAL ram_diag_bg_miso               : t_mem_miso;
 
-  SIGNAL reg_dp_offload_tx_mosi         : t_mem_mosi;
-  SIGNAL reg_dp_offload_tx_miso         : t_mem_miso;
-  SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
-  SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
+  SIGNAL reg_dp_offload_tx_mosi_arr         : t_mem_mosi_arr(c_nof_dp_offload_tx-1 DOWNTO 0);
+  SIGNAL reg_dp_offload_tx_miso_arr         : t_mem_miso_arr(c_nof_dp_offload_tx-1 DOWNTO 0);
+  SIGNAL reg_dp_offload_tx_hdr_dat_mosi_arr : t_mem_mosi_arr(c_nof_dp_offload_tx-1 DOWNTO 0);
+  SIGNAL reg_dp_offload_tx_hdr_dat_miso_arr : t_mem_miso_arr(c_nof_dp_offload_tx-1 DOWNTO 0);
 
   SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
   SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
@@ -341,23 +340,26 @@ ARCHITECTURE str OF unb1_test IS
   SIGNAL block_gen_src_out_arr          : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
   SIGNAL block_gen_src_in_arr           : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
 
-  SIGNAL dp_offload_tx_src_out_arr      : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
-  SIGNAL dp_offload_tx_src_in_arr       : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+  SIGNAL fifo_block_gen_src_out_arr     : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+  SIGNAL fifo_block_gen_src_in_arr      : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
 
-  SIGNAL dp_offload_rx_snk_in_arr       : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
-  SIGNAL dp_offload_rx_snk_out_arr      : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+  SIGNAL dp_offload_tx_src_out_arr      : t_dp_sosi_arr(c_nof_streams_eth-1 DOWNTO 0);
+  SIGNAL dp_offload_tx_src_in_arr       : t_dp_siso_arr(c_nof_streams_eth-1 DOWNTO 0);
 
-  SIGNAL dp_offload_rx_src_out_arr      : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
-  SIGNAL dp_offload_rx_src_in_arr       : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+  SIGNAL dp_offload_rx_snk_in_arr       : t_dp_sosi_arr(c_nof_streams_eth-1 DOWNTO 0);
+  SIGNAL dp_offload_rx_snk_out_arr      : t_dp_siso_arr(c_nof_streams_eth-1 DOWNTO 0);
+
+  SIGNAL dp_offload_rx_src_out_arr      : t_dp_sosi_arr(c_nof_streams_eth-1 DOWNTO 0);
+  SIGNAL dp_offload_rx_src_in_arr       : t_dp_siso_arr(c_nof_streams_eth-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
 
   SIGNAL diag_data_buf_snk_in_arr       : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
   SIGNAL diag_data_buf_snk_out_arr      : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
 
    -- Interface: 1GbE UDP streaming ports
-  SIGNAL eth1g_udp_tx_sosi_arr          : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
-  SIGNAL eth1g_udp_tx_siso_arr          : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
-  SIGNAL eth1g_udp_rx_sosi_arr          : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
-  SIGNAL eth1g_udp_rx_siso_arr          : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+  SIGNAL eth1g_udp_tx_sosi_arr          : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+  SIGNAL eth1g_udp_tx_siso_arr          : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+  SIGNAL eth1g_udp_rx_sosi_arr          : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+  SIGNAL eth1g_udp_rx_siso_arr          : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
 
   -- DDR
   SIGNAL ddr_ctlr_mosi_arr              : t_mem_ctlr_mosi_arr(0 TO g_nof_MB-1);
@@ -368,23 +370,21 @@ ARCHITECTURE str OF unb1_test IS
 
   SIGNAL ram_ss_ss_transp_mosi          : t_mem_mosi;
   SIGNAL ram_ss_ss_transp_miso          : t_mem_miso;
-  SIGNAL ram_ss_ss_transp_mosi2          : t_mem_mosi;
-  SIGNAL ram_ss_ss_transp_miso2          : t_mem_miso := c_mem_miso_rst;
+  SIGNAL ram_ss_ss_transp_mosi2         : t_mem_mosi;
+  SIGNAL ram_ss_ss_transp_miso2         : t_mem_miso := c_mem_miso_rst;
 
   SIGNAL to_mem_siso                    : t_dp_siso := c_dp_siso_rdy;
   SIGNAL to_mem_sosi                    : t_dp_sosi;
   SIGNAL from_mem_siso                  : t_dp_siso := c_dp_siso_rdy;
   SIGNAL from_mem_sosi                  : t_dp_sosi;
 
-  SIGNAL to_mem_siso2                    : t_dp_siso := c_dp_siso_rdy;
-  SIGNAL to_mem_sosi2                    : t_dp_sosi;
-  SIGNAL from_mem_siso2                  : t_dp_siso := c_dp_siso_rdy;
-  SIGNAL from_mem_sosi2                  : t_dp_sosi;
+  SIGNAL to_mem_siso2                   : t_dp_siso := c_dp_siso_rdy;
+  SIGNAL to_mem_sosi2                   : t_dp_sosi;
+  SIGNAL from_mem_siso2                 : t_dp_siso := c_dp_siso_rdy;
+  SIGNAL from_mem_sosi2                 : t_dp_sosi;
 
   SIGNAL reg_io_ddr_mosi                : t_mem_mosi;
   SIGNAL reg_io_ddr_miso                : t_mem_miso;
---  SIGNAL seriesterminationcontrol   : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0); 
---  SIGNAL parallelterminationcontrol   : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0); 
 BEGIN
 
   -----------------------------------------------------------------------------
@@ -403,7 +403,7 @@ BEGIN
     g_use_phy                 => c_use_phy,
     g_aux                     => c_unb1_board_aux,
     g_udp_offload             => c_use_1GbE,
-    g_udp_offload_nof_streams => c_nof_streams_10GbE,
+    g_udp_offload_nof_streams => c_nof_streams_1GbE,
     g_dp_clk_use_pll          => TRUE,
     g_mm_clk_use_pll          => TRUE
   )
@@ -514,10 +514,12 @@ BEGIN
     g_sim               => g_sim,
     g_sim_unb_nr        => g_sim_unb_nr,
     g_sim_node_nr       => g_sim_node_nr,
+    g_nof_streams_1GbE  => c_nof_streams_1GbE,
     g_nof_streams_10GbE => c_nof_streams_10GbE,
     g_nof_streams_ddr   => c_nof_streams_ddr,
     g_bg_block_size     => c_bg_block_size,
-    g_hdr_field_arr     => c_hdr_field_arr
+    g_hdr_field_arr     => c_hdr_field_arr,
+    g_nof_dp_offload_tx => c_nof_dp_offload_tx
    )
   PORT MAP(  
     mm_rst                         => mm_rst,
@@ -577,14 +579,10 @@ BEGIN
     reg_diag_bg_mosi               => reg_diag_bg_mosi,
     reg_diag_bg_miso               => reg_diag_bg_miso,
 
-    reg_dp_offload_tx_mosi         => reg_dp_offload_tx_mosi,
-    reg_dp_offload_tx_miso         => reg_dp_offload_tx_miso,
-
-    reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
-    reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
-    reg_dp_offload_tx_hdr_ovr_mosi => OPEN, -- FIXME DS: This MM bus can be removed.
-    reg_dp_offload_tx_hdr_ovr_miso => c_mem_miso_rst, -- FIXME
+    reg_dp_offload_tx_mosi_arr         => reg_dp_offload_tx_mosi_arr,
+    reg_dp_offload_tx_miso_arr         => reg_dp_offload_tx_miso_arr,
+    reg_dp_offload_tx_hdr_dat_mosi_arr => reg_dp_offload_tx_hdr_dat_mosi_arr,
+    reg_dp_offload_tx_hdr_dat_miso_arr => reg_dp_offload_tx_hdr_dat_miso_arr,
 
     reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
     reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
@@ -637,16 +635,68 @@ BEGIN
     ram_bg_data_miso => ram_diag_bg_miso
   );
 
+  gen_dp_fifo_sc : FOR i IN 0 TO c_nof_streams_eth-1 GENERATE
+    u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
+    GENERIC MAP (
+      g_data_w    => c_data_w,
+      g_fifo_size => 50 
+    )
+    PORT MAP (
+      rst         => dp_rst,
+      clk         => dp_clk,
+      -- ST sink (BG)
+      snk_out     => block_gen_src_in_arr(i),
+      snk_in      => block_gen_src_out_arr(i),
+      -- ST source (tx_offload)
+      src_in      => fifo_block_gen_src_in_arr(i),
+      src_out     => fifo_block_gen_src_out_arr(i)
+    );
+  END GENERATE;
+
   -----------------------------------------------------------------------------
   -- TX: dp_offload_tx
   -----------------------------------------------------------------------------
-  u_dp_offload_tx : ENTITY dp_lib.dp_offload_tx
+  u_dp_offload_tx_1GbE : ENTITY dp_lib.dp_offload_tx
+  GENERIC MAP (
+    g_nof_streams               => c_nof_streams_1GbE,
+    g_data_w                    => c_eth_data_w,
+    g_use_complex               => FALSE,
+    g_max_nof_words_per_block   => c_max_nof_words_per_block,
+    g_def_nof_words_per_block   => c_def_1GbE_block_size,
+    g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet,
+    g_def_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+    g_hdr_field_arr             => c_hdr_field_arr,
+    g_hdr_field_sel             => c_hdr_field_ovr_init
+   )
+  PORT MAP (
+    mm_rst                => mm_rst,
+    mm_clk                => mm_clk,
+
+    dp_rst                => dp_rst,
+    dp_clk                => dp_clk,
+
+    reg_mosi              => reg_dp_offload_tx_mosi_arr(0),
+    reg_miso              => reg_dp_offload_tx_miso_arr(0),
+
+    reg_hdr_dat_mosi      => reg_dp_offload_tx_hdr_dat_mosi_arr(0),
+    reg_hdr_dat_miso      => reg_dp_offload_tx_hdr_dat_miso_arr(0),
+
+    snk_in_arr            => fifo_block_gen_src_out_arr(c_nof_streams_1GbE-1 DOWNTO 0),
+    snk_out_arr           => fifo_block_gen_src_in_arr(c_nof_streams_1GbE-1 DOWNTO 0),
+
+    src_out_arr           => dp_offload_tx_src_out_arr(c_nof_streams_1GbE-1 DOWNTO 0),
+    src_in_arr            => dp_offload_tx_src_in_arr(c_nof_streams_1GbE-1 DOWNTO 0),
+
+    hdr_fields_in_arr     => hdr_fields_in_arr(c_nof_streams_1GbE-1 DOWNTO 0)
+  );
+
+  u_dp_offload_tx_10GbE : ENTITY dp_lib.dp_offload_tx
   GENERIC MAP (
     g_nof_streams               => c_nof_streams_10GbE,
     g_data_w                    => c_data_w,
     g_use_complex               => FALSE,
     g_max_nof_words_per_block   => c_max_nof_words_per_block,
-    g_def_nof_words_per_block   => c_def_nof_words_per_block,
+    g_def_nof_words_per_block   => c_def_10GbE_block_size,
     g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet,
     g_def_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
     g_hdr_field_arr             => c_hdr_field_arr,
@@ -659,43 +709,63 @@ BEGIN
     dp_rst                => dp_rst,
     dp_clk                => dp_clk,
 
-    reg_mosi              => reg_dp_offload_tx_mosi,
-    reg_miso              => reg_dp_offload_tx_miso,
+    reg_mosi              => reg_dp_offload_tx_mosi_arr(1),
+    reg_miso              => reg_dp_offload_tx_miso_arr(1),
 
-    reg_hdr_dat_mosi      => reg_dp_offload_tx_hdr_dat_mosi,
-    reg_hdr_dat_miso      => reg_dp_offload_tx_hdr_dat_miso,
+    reg_hdr_dat_mosi      => reg_dp_offload_tx_hdr_dat_mosi_arr(1),
+    reg_hdr_dat_miso      => reg_dp_offload_tx_hdr_dat_miso_arr(1),
 
-    snk_in_arr            => block_gen_src_out_arr(c_nof_streams_10GbE-1 DOWNTO 0),
-    snk_out_arr           => block_gen_src_in_arr(c_nof_streams_10GbE-1 DOWNTO 0),
+    snk_in_arr            => fifo_block_gen_src_out_arr(c_nof_streams_eth-1 DOWNTO c_nof_streams_1GbE),
+    snk_out_arr           => fifo_block_gen_src_in_arr(c_nof_streams_eth-1 DOWNTO c_nof_streams_1GbE),
 
-    src_out_arr           => dp_offload_tx_src_out_arr,
-    src_in_arr            => dp_offload_tx_src_in_arr,
+    src_out_arr           => dp_offload_tx_src_out_arr(c_nof_streams_eth-1 DOWNTO c_nof_streams_1GbE),
+    src_in_arr            => dp_offload_tx_src_in_arr(c_nof_streams_eth-1 DOWNTO c_nof_streams_1GbE),
 
-    hdr_fields_in_arr     => hdr_fields_in_arr
+    hdr_fields_in_arr     => hdr_fields_in_arr(c_nof_streams_eth-1 DOWNTO c_nof_streams_1GbE)
   );
 
-  gen_hdr_in_fields : FOR i IN 0 TO c_nof_streams_10GbE-1 GENERATE
-    -- dst = src
+
+
+  -- c_nof_streams_1GbE:
+  -- dst = src
+  gen_hdr_in_fields_1GbE : FOR i IN 0 TO c_nof_streams_1GbE-1 GENERATE
     hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
     hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_dst_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_dst_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
 
     hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr")) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
     hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_dst_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_dst_addr")) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
 
-    -- dst port goes through 4000,4001,4002
-    hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_src_port") DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= TO_UVEC(4000+i, 16);
-    hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port") DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= TO_UVEC(4000+i, 16);
+    -- dst port goes through 4000
+    hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_src_port") DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= TO_UVEC(4000, 16);
+    hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port") DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= TO_UVEC(4000, 16);
 
     hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_sync"    ) DOWNTO field_lo(c_hdr_field_arr, "usr_sync"   )) <= slv(block_gen_src_out_arr(i).sync);
     hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn"     ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn"    )) <= block_gen_src_out_arr(i).bsn(59 DOWNTO 0);
   END GENERATE;
 
+  -- c_nof_streams_10GbE:
+  gen_hdr_in_fields_10GbE : FOR i IN 0 TO c_nof_streams_10GbE-1 GENERATE
+    -- dst = src
+    hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
+    hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "eth_dst_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_dst_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
+
+    hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr")) <= x"0A0A" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
+    hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "ip_dst_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_dst_addr")) <= x"0A0A" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
+
+    -- dst port goes through 4000,4001,4002
+    hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "udp_src_port") DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= TO_UVEC(4000+i, 16);
+    hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "udp_dst_port") DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= TO_UVEC(4000+i, 16);
+
+    hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "usr_sync"    ) DOWNTO field_lo(c_hdr_field_arr, "usr_sync"   )) <= slv(block_gen_src_out_arr(i+c_nof_streams_1GbE).sync);
+    hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "usr_bsn"     ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn"    )) <= block_gen_src_out_arr(i+c_nof_streams_1GbE).bsn(59 DOWNTO 0);
+  END GENERATE;
+
 -----------------------------------------------------------------------------
   -- RX: dp_offload_rx
   -----------------------------------------------------------------------------
   u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
   GENERIC MAP (
-    g_nof_streams         => c_nof_streams_10GbE,
+    g_nof_streams         => c_nof_streams_eth,
     g_data_w              => c_data_w,
     g_hdr_field_arr       => c_hdr_field_arr,
     g_remove_crc          => NOT(c_use_lpbk),
@@ -720,7 +790,7 @@ BEGIN
     hdr_fields_out_arr    => hdr_fields_out_arr
     );
 
-  gen_hdr_out_fields : FOR i IN 0 TO c_nof_streams_10GbE-1 GENERATE
+  gen_hdr_out_fields : FOR i IN 0 TO c_nof_streams_eth-1 GENERATE
     diag_data_buf_snk_in_arr(i).sync <=          sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )));
     diag_data_buf_snk_in_arr(i).bsn  <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn"  )), c_dp_stream_bsn_w);
   END GENERATE;
@@ -728,9 +798,9 @@ BEGIN
   -----------------------------------------------------------------------------
   -- RX: Data buffers and BSN monitors
   -----------------------------------------------------------------------------
-  dp_offload_rx_src_in_arr <= diag_data_buf_snk_out_arr(c_nof_streams_10GbE-1 downto 0);
+  dp_offload_rx_src_in_arr <= diag_data_buf_snk_out_arr(c_nof_streams_eth-1 downto 0);
 
-  gen_bsn_mon_in : FOR i IN 0 TO c_nof_streams_10GbE-1 GENERATE
+  gen_bsn_mon_in : FOR i IN 0 TO c_nof_streams_eth-1 GENERATE
     diag_data_buf_snk_in_arr(i).data  <= dp_offload_rx_src_out_arr(i).data;
     diag_data_buf_snk_in_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
     diag_data_buf_snk_in_arr(i).sop   <= dp_offload_rx_src_out_arr(i).sop;
@@ -740,7 +810,7 @@ BEGIN
 
   u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
   GENERIC MAP (
-    g_nof_streams        => c_nof_streams_10GbE,
+    g_nof_streams        => c_nof_streams_eth,
     g_cross_clock_domain => TRUE,
     g_sync_timeout       => c_bg_blocks_per_sync*(c_bg_block_size+c_bg_gapsize),
     g_cnt_sop_w          => ceil_log2(c_bg_blocks_per_sync+1),
@@ -755,8 +825,8 @@ BEGIN
 
     dp_rst      => dp_rst,
     dp_clk      => dp_clk,
-    in_siso_arr => diag_data_buf_snk_out_arr(c_nof_streams_10GbE-1 downto 0),
-    in_sosi_arr => diag_data_buf_snk_in_arr(c_nof_streams_10GbE-1 downto 0)
+    in_siso_arr => diag_data_buf_snk_out_arr(c_nof_streams_eth-1 downto 0),
+    in_sosi_arr => diag_data_buf_snk_in_arr(c_nof_streams_eth-1 downto 0)
   );
 
   diag_data_buf_snk_out_arr <= (OTHERS=>c_dp_siso_rdy);
@@ -797,11 +867,11 @@ BEGIN
   -- Interface : 1GbE
   -----------------------------------------------------------------------------
   gen_wires_1GbE : IF c_use_1GbE=TRUE GENERATE
-    eth1g_udp_tx_sosi_arr    <= dp_offload_tx_src_out_arr;
-    dp_offload_tx_src_in_arr <= eth1g_udp_tx_siso_arr;
+    eth1g_udp_tx_sosi_arr(0)    <= dp_offload_tx_src_out_arr(0);
+    dp_offload_tx_src_in_arr(0) <= eth1g_udp_tx_siso_arr(0);
 
-    dp_offload_rx_snk_in_arr <= eth1g_udp_rx_sosi_arr;
-    eth1g_udp_rx_siso_arr    <= dp_offload_rx_snk_out_arr;
+    dp_offload_rx_snk_in_arr(0) <= eth1g_udp_rx_sosi_arr(0);
+    eth1g_udp_rx_siso_arr(0)    <= dp_offload_rx_snk_out_arr(0);
   END GENERATE;
 
   -----------------------------------------------------------------------------
@@ -849,11 +919,11 @@ BEGIN
       dp_rst              => dp_rst,
       dp_clk              => dp_clk,
 
-      src_out_arr         => dp_offload_rx_snk_in_arr,
-      src_in_arr          => dp_offload_rx_snk_out_arr,
+      src_out_arr         => dp_offload_rx_snk_in_arr(c_nof_streams_eth-1 downto c_nof_streams_1GbE),
+      src_in_arr          => dp_offload_rx_snk_out_arr(c_nof_streams_eth-1 downto c_nof_streams_1GbE),
   
-      snk_out_arr         => dp_offload_tx_src_in_arr,
-      snk_in_arr          => dp_offload_tx_src_out_arr,
+      snk_out_arr         => dp_offload_tx_src_in_arr(c_nof_streams_eth-1 downto c_nof_streams_1GbE),
+      snk_in_arr          => dp_offload_tx_src_out_arr(c_nof_streams_eth-1 downto c_nof_streams_1GbE),
 
       -- Serial XAUI IO
       xaui_tx_arr         => i_xaui_tx_arr,
@@ -904,8 +974,7 @@ BEGIN
 
   u_reorder: ENTITY reorder_lib.reorder_transpose 
   GENERIC MAP (
-    g_sim            => g_sim,
-    g_nof_streams    => 1,--c_nof_streams_ddr,
+    g_nof_streams    => c_nof_streams_ddr,
     g_in_dat_w       => c_data_w,
     g_ena_pre_transp => FALSE,
     g_use_complex    => FALSE,
@@ -917,11 +986,11 @@ BEGIN
     dp_clk                => dp_clk,
     dp_rst                => dp_rst,
     -- ST sinks from BG
-    snk_out_arr           => block_gen_src_in_arr(c_nof_streams-1 downto c_nof_streams_10GbE), -- -2
-    snk_in_arr            => block_gen_src_out_arr(c_nof_streams-1 downto c_nof_streams_10GbE), -- -2
+    snk_out_arr           => block_gen_src_in_arr(c_nof_streams-1 downto c_nof_streams_eth), -- -2
+    snk_in_arr            => block_gen_src_out_arr(c_nof_streams-1 downto c_nof_streams_eth), -- -2
     -- ST source to DB
     src_in_arr            => (OTHERS=> c_dp_siso_rdy),
-    src_out_arr           => diag_data_buf_snk_in_arr(c_nof_streams-1 downto c_nof_streams_10GbE), -- -2
+    src_out_arr           => diag_data_buf_snk_in_arr(c_nof_streams-1 downto c_nof_streams_eth), -- -2
     -- Memory Mapped 
     ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
     ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
@@ -934,43 +1003,6 @@ BEGIN
     from_mem_snk_in       => from_mem_sosi,
     from_mem_snk_out      => from_mem_siso
   );
-  --u_reorder2: ENTITY reorder_lib.reorder_transpose 
-  --GENERIC MAP (
-  --  g_sim            => g_sim,
-  --  g_nof_streams    => 1,--,
-  --  g_ena_pre_transp => FALSE,
-  --  g_reorder_seq    => c_reorder_seq_same
-  --)
-  --PORT MAP (
-  --  mm_rst                => mm_rst,
-  --  mm_clk                => mm_clk,
-  --  dp_clk                => dp_clk,
-  --  dp_rst                => dp_rst,
-  --  -- ST sinks from BG
-  --  snk_out_arr           => block_gen_src_in_arr(c_nof_streams-1 downto c_nof_streams-1),
-  --  snk_in_arr            => block_gen_src_out_arr(c_nof_streams-1 downto c_nof_streams-1),
-  --  -- ST source to DB
-  --  src_in_arr            => (OTHERS=> c_dp_siso_rdy),
-  --  src_out_arr           => diag_data_buf_snk_in_arr(c_nof_streams-1 downto c_nof_streams-1),
-  --  -- Memory Mapped 
-  --  ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi2,
-  --  ram_ss_ss_transp_miso => ram_ss_ss_transp_miso2,
-  --  -- Control interface to the external memory
-  --  dvr_mosi              => ddr_ctlr_mosi_arr(1),
-  --  dvr_miso              => ddr_ctlr_miso_arr(1),
-  --  -- Data interface to the external memory
-  --  to_mem_src_out        => to_mem_sosi2,
-  --  to_mem_src_in         => to_mem_siso2,
-  --  from_mem_snk_in       => from_mem_sosi2,
-  --  from_mem_snk_out      => from_mem_siso2
-  --);
-
-  --seriesterminationcontrol <= (OTHERS=>'0');
-  --parallelterminationcontrol <= (OTHERS=>'0');
-  --MB_I_IN(0).seriesterminationcontrol <= seriesterminationcontrol;
-  --MB_I_IN(0).parallelterminationcontrol <= parallelterminationcontrol;
-  --MB_I_OU(0).seriesterminationcontrol <= MB_I_IN(0).seriesterminationcontrol;
-  --MB_I_OU(0).parallelterminationcontrol <= MB_I_IN(0).parallelterminationcontrol;
 
   ------------------------------------------------------------------------------
   -- DDR3 MODULE 0,1
@@ -1031,62 +1063,6 @@ BEGIN
     );
   END GENERATE;
 
---  no_MB_II : IF g_use_MB_II = 0 GENERATE
---    --reg_ddr3_miso_arr(0)        <= c_mem_miso_rst;
---    --reg_diagnostics_miso_arr(0) <= c_mem_miso_rst;
---  END GENERATE;
---
---  gen_MB_II : IF g_use_MB_II = 1 GENERATE
---    u_mms_ddr3_ii: ENTITY io_ddr_lib.io_ddr
---    GENERIC MAP (
---      g_technology       => g_technology,
---      g_tech_ddr         => c_ddr_master,
---      g_wr_data_w        => c_st_dat_w,
---      g_rd_data_w        => c_st_dat_w
---    )
---    PORT MAP (
---      mm_clk             => mm_clk,
---      mm_rst             => mm_rst,
---
---      reg_io_ddr_mosi    => reg_io_ddr_mosi2,
---      reg_io_ddr_miso    => reg_io_ddr_miso2,
---
---      ctlr_ref_clk       => dp_clk,
---      ctlr_ref_rst       => dp_rst,
---
---      ctlr_clk_out       => ddr_ctlr_clk(1),
---      ctlr_clk_in        => ddr_ctlr_clk(1),
---
---      ctlr_rst_out       => ddr_ctlr_rst(1),
---      ctlr_rst_in        => ddr_ctlr_rst(1),
---
---      dvr_clk            => dp_clk,
---      dvr_rst            => dp_rst,
---
---      dvr_mosi           => ddr_ctlr_mosi_arr(1),
---      dvr_miso           => ddr_ctlr_miso_arr(1),
---
---      wr_clk             => dp_clk,
---      wr_rst             => dp_rst,
---
---      wr_sosi            => to_mem_sosi2,
---      wr_siso            => to_mem_siso2,
---
---      rd_clk             => dp_clk,
---      rd_rst             => dp_rst,
---
---      rd_sosi            => from_mem_sosi2,
---      rd_siso            => from_mem_siso2,
---
---      term_ctrl_out      => OPEN,
---      term_ctrl_in       => OPEN,
---
---      phy3_in            => MB_I_IN,
---      phy3_io            => MB_I_IO,
---      phy3_ou            => MB_I_OU
---    );
---  END GENERATE;
-
   -----------------------------------------------------------------------------
   -- Node function
   -----------------------------------------------------------------------------