diff --git a/tools/oneclick/prestudy/ASTRON_SP_056_One_Click_Design_Flow_Specification.doc b/tools/oneclick/prestudy/ASTRON_SP_056_One_Click_Design_Flow_Specification.doc index a01563c8fcd84a400096b037dc099d930c31287c..c5d4d7ca8e9e6b0df217a01dac678b3e51619da2 100644 Binary files a/tools/oneclick/prestudy/ASTRON_SP_056_One_Click_Design_Flow_Specification.doc and b/tools/oneclick/prestudy/ASTRON_SP_056_One_Click_Design_Flow_Specification.doc differ diff --git a/tools/oneclick/prestudy/ASTRON_SP_056_One_Click_Design_Flow_Specification.pdf b/tools/oneclick/prestudy/ASTRON_SP_056_One_Click_Design_Flow_Specification.pdf index fd7b263599718ddfa5ad7512d1f18f87c990bc64..17433ad0668d310c2baa32e2c8dfe6fed37c6081 100644 Binary files a/tools/oneclick/prestudy/ASTRON_SP_056_One_Click_Design_Flow_Specification.pdf and b/tools/oneclick/prestudy/ASTRON_SP_056_One_Click_Design_Flow_Specification.pdf differ diff --git a/tools/oneclick/prestudy/ASTRON_SP_056_One_Click_Design_Flow_Specification.vsd b/tools/oneclick/prestudy/ASTRON_SP_056_One_Click_Design_Flow_Specification.vsd index 060f08c2a0d0335f8381ad52cda76e42ee236286..5d3060396c6a54c372976c100f1d197dc01e85e7 100644 Binary files a/tools/oneclick/prestudy/ASTRON_SP_056_One_Click_Design_Flow_Specification.vsd and b/tools/oneclick/prestudy/ASTRON_SP_056_One_Click_Design_Flow_Specification.vsd differ diff --git a/tools/oneclick/prestudy/oneclick_prestudy_readme.txt b/tools/oneclick/prestudy/oneclick_prestudy_readme.txt index d4a7308e1d72f924e88f7bb91970cc4e2dc38bfd..0f885fd75a5ee890f0b80b4d1dcf4d0ac3eaed1c 100644 --- a/tools/oneclick/prestudy/oneclick_prestudy_readme.txt +++ b/tools/oneclick/prestudy/oneclick_prestudy_readme.txt @@ -10,34 +10,8 @@ This file keeps some historical notes on the OneClick prestudy results. and connect it between 'b' and 'c'. The printed output changes accordingly. It's minimal, but hopefully illustrates the concept. -2) Data driven or RTL accurate, telecon with SA, 15 may 2014 -a)SA are doing trials with MyHDL. They want designers to have access to the RTL - without having to know VHDL, because this makes the development feasible - for a broad community of engineers like they have now with Matlab/Simulink, - and not only to digital engineers. RTL access in Python is what MyHDL - provides. MyHDL simulates HDL at the RTL level, i.e. event driven with clocks. - The parallel simulation is achieved using sensitivity lists, similar as in - VHDL. - -b) Astron wants to model the DSP at the data level, so without the clock. The - parallel simulation is not achieved by a sensitivity list and functions that - are processed each time an input changes, but instead a function is only - processed when it has sufficient data to calculate its next new output. Hence - input data is only processed once. The functions may be mapped on software - processes, threads or in a sequential loop. The next investigations focus on - using software processes or threads, and on using pipes or queues. - -c) MyHDL could be supported in the Astron scheme by treating the MyHDL - components as just another source for creating RTL components. Default at - Astron we develop our RTL components in VHDL, but one may also start coding - in MyHDL and then use the toVHDL() function to convert it to an VHDL - component. The advantage of a MyHDL component is that the RTL description - in Python can also serve as behavioral model in Python by simply adding - an local clock source (assuming that the RTL description uses the standard - MM and ST interfaces). For the VHDL components we manually need to create - a model in Python. However this model is typically quite simple. -3) Explorations, 3 june 2014 +2) Explorations, 3 june 2014 - 7_stream_simplex_2_comp_parallel.py Show using software processes and pipes to model components. With 20 processes on the 12 core CPU of dop233 this runs much faster then on a quad core CPU.