L2SDP-200, backup only.

applications/lofar2/libraries/sdp/hdllib.cfg

@@ -13,12 +13,14 @@ synth_files =
     src/vhdl/sdp_info_reg.vhd 
     src/vhdl/sdp_info.vhd 
     src/vhdl/sdp_beamformer_output.vhd 
+    src/vhdl/sdp_statistics_offload.vhd 
     src/vhdl/node_sdp_adc_input_and_timing.vhd
     src/vhdl/node_sdp_filterbank.vhd
     src/vhdl/node_sdp_beamformer.vhd
 
 test_bench_files =
     tb/vhdl/tb_sdp_info.vhd 
+    tb/vhdl/tb_sdp_statistics_offload.vhd 
 
 regression_test_vhdl = 
     tb/vhdl/tb_sdp_info.vhd

applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: P. Donker
+
+-- Purpose:
+-- . test bench for sdp_info.vhd (and sdp_info_reg.vhd)
+-- Description:
+--
+-- https://plm.astron.nl/polarion/#/project/LOFAR2System/workitem?id=LOFAR2-9258
+-- https://plm.astron.nl/polarion/#/project/LOFAR2System/workitem?id=LOFAR2-8855
+--
+-- Remark:
+-- .
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL; 
+USE common_lib.tb_common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.sdp_pkg.ALL;
+
+
+ENTITY tb_sdp_statistics_offload IS
+  GENERIC (
+    g_statistics_type : STRING := "SST";
+    g_nof_signal_inputs_per_pn : NATURAL := 4
+  );
+END tb_sdp_statistics_offload;
+
+ARCHITECTURE tb OF tb_sdp_statistics_offload IS
+  CONSTANT c_dp_clk_period        : TIME := 5 ns;     -- 200 MHz
+  CONSTANT c_mm_clk_period        : TIME := 20 ns;    -- 50 MHz
+
+  CONSTANT c_cross_clock_domain_latency : NATURAL := 40;
+  
+  CONSTANT c_eth_src_mac  : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0) := x"123456789ABC";
+  CONSTANT c_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0) := x"D001";
+  CONSTANT c_ip_src_addr  : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0) := x"0A090807";
+
+  -- used mm_adresses on mm bus
+  CONSTANT c_mm_addr_enable   : NATURAL := 0;
+  
+  -- used test ram size: c_block_size = c_nof_data * c_data_size * (c_step_size / c_data_size) => 512 * 2 * (4 / 2) = 2048 words per pair of signal inputs;
+  -- with 12 signal input, 6 pairs (blocks) we will fill 2 blocks for testing 2 * 2048 = 4096 = 
+  CONSTANT c_nof_data  : NATURAL := 512;
+  CONSTANT c_data_size : NATURAL := 2;
+  CONSTANT c_step_size : NATURAL := 4;
+  CONSTANT c_ram_size  : NATURAL := c_nof_data * c_data_size * g_nof_signal_inputs_per_pn;
+  CONSTANT c_ram_w     : NATURAL := ceil_log2(c_ram_size);
+  CONSTANT c_ram_buf   : t_c_mem := (c_mem_ram_rd_latency, c_ram_w,  32, 2**c_ram_w, 'X');
+
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL tb_mm_reg_end       : STD_LOGIC := '0';
+
+  SIGNAL dp_clk              : STD_LOGIC := '1';   -- digital data path clock = 200 MHz (deser factor 4);
+  SIGNAL dp_rst              : STD_LOGIC;
+
+  SIGNAL mm_clk              : STD_LOGIC := '1';   -- MM control clock = 50 MHz
+  SIGNAL mm_rst              : STD_LOGIC;
+  
+  SIGNAL master_mosi         : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL master_miso         : t_mem_miso;
+
+  SIGNAL enable_mosi : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL enable_miso : t_mem_miso;
+
+  SIGNAL hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL hdr_dat_miso : t_mem_miso;
+
+  SIGNAL in_sosi             : t_dp_sosi := c_dp_sosi_rst;
+  SIGNAL out_sosi            : t_dp_sosi;
+
+  -- signals used to change settings of sdp_info 
+  SIGNAL gn_index  : NATURAL   := 15; 
+  SIGNAL f_adc     : STD_LOGIC := '0'; 
+  SIGNAL fsub_type : STD_LOGIC := '0';
+
+  SIGNAL sdp_info  : t_sdp_info; 
+
+  -- signals used for response of mm bus
+  SIGNAL mm_natural_response : NATURAL;
+
+  -- signals used for starting processes
+  SIGNAL wr_data      : STD_LOGIC_VECTOR(c_ram_buf.dat_w-1 DOWNTO 0);
+  SIGNAL wr_addr      : STD_LOGIC_VECTOR(c_ram_buf.adr_w-1 DOWNTO 0);
+  SIGNAL wr_en        : STD_LOGIC;
+  SIGNAL init_ram_done: STD_LOGIC := '0';
+
+BEGIN
+  dp_rst <= '1', '0' AFTER c_dp_clk_period*7;
+  dp_clk <= (NOT dp_clk) OR tb_end AFTER c_dp_clk_period/2;
+  
+  mm_rst <= '1', '0' AFTER c_mm_clk_period*7;
+  mm_clk <= (NOT mm_clk) OR tb_end AFTER c_mm_clk_period/2;
+
+  
+  -- fill ram with data, data is same as address number.
+  p_mm_statistics_ram : PROCESS
+    VARIABLE addr_cnt : NATURAL := 0;
+  BEGIN
+    wr_en <= '0';
+    -- initialyze
+    proc_common_wait_until_low(mm_clk, mm_rst);
+    proc_common_wait_some_cycles(mm_clk, 10);
+
+    FOR i IN 0 TO c_ram_buf.nof_dat-1 LOOP
+      wr_addr <= TO_UVEC(addr_cnt, c_ram_buf.adr_w);
+      wr_data <= TO_UVEC(addr_cnt, c_ram_buf.dat_w);
+      wr_en   <= '1';
+      proc_common_wait_some_cycles(dp_clk, 1);
+      addr_cnt := addr_cnt + 1;
+    END LOOP; 
+    wr_en <= '0';
+    
+    init_ram_done <= '1'; 
+    WAIT;
+  END PROCESS;
+
+  p_in_sosi : PROCESS
+  BEGIN
+    proc_common_wait_until_high(dp_clk, init_ram_done);
+    -- enable common variabel delay
+    proc_mem_mm_bus_wr(c_mm_addr_enable, 1, mm_clk, enable_miso, enable_mosi);
+    proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency);
+    FOR i IN 0 TO g_nof_signal_inputs_per_pn LOOP
+      in_sosi.sync  <= '1';
+      in_sosi.valid <= '1';
+      in_sosi.sop   <= '1';                 
+      proc_common_wait_some_cycles(dp_clk, 1);
+      in_sosi.sync  <= '0';
+      in_sosi.sop   <= '0';
+      proc_common_wait_some_cycles(dp_clk, c_nof_data*c_data_size);                 
+      in_sosi.eop   <= '1';                 
+      proc_common_wait_some_cycles(dp_clk, 1);
+      in_sosi.eop   <= '0';
+      in_sosi.valid <= '0';
+      proc_common_wait_some_cycles(dp_clk, 1);
+    END LOOP;
+    WAIT;
+  END PROCESS;
+
+  p_mm_reg_stimuli : PROCESS
+  BEGIN
+    --enable_mosi  <= c_mem_mosi_rst;
+    --hdr_dat_mosi <= c_mem_mosi_rst;
+
+    proc_common_wait_until_high(dp_clk, init_ram_done);
+    proc_common_wait_some_cycles(mm_clk, 100);
+
+    -- station_id, antenna_band_index, observation_id, nyquist_zone_index, f_adc, fsub_type, beam_repositioning_flag, subband_calibrated_flag, O_si, N_si, O_rn, N_rn, block_period, beamlet_scale
+    sdp_info <= ( x"0001", '0', x"00000003", b"01", '0', '0', '0', '0', x"00", x"00", x"00", x"00", x"0000", x"0000");
+    proc_common_wait_some_cycles(mm_clk, 1);
+    out_sosi.sync <= '1';
+
+    proc_common_wait_some_cycles(mm_clk, 100);
+    tb_end <= '1';
+    WAIT;
+  END PROCESS;
+
+  
+  u_ram: ENTITY common_lib.common_ram_crw_crw_ratio
+  GENERIC MAP (
+    g_ram_a => c_ram_buf,  -- settings for port a
+    g_ram_b => c_ram_buf  -- settings for port b
+  )
+  PORT MAP (
+    -- MM read/write port clock domain
+    rst_a    => mm_rst,
+    clk_a    => mm_clk,
+    wr_en_a  => master_mosi.wr,
+    wr_dat_a => master_mosi.wrdata(c_ram_buf.dat_w-1 DOWNTO 0),
+    adr_a    => master_mosi.address(c_ram_buf.adr_w-1 DOWNTO 0),
+    rd_en_a  => master_mosi.rd,
+    rd_dat_a => master_miso.rddata(c_ram_buf.dat_w-1 DOWNTO 0),
+    rd_val_a => master_miso.rdval,
+
+    -- ST write only port clock domain
+    rst_b     => dp_rst,
+    clk_b     => dp_clk,
+    wr_en_b   => wr_en,
+    wr_dat_b  => wr_data,
+    adr_b     => wr_addr,
+    rd_en_b   => '0',
+    rd_dat_b  => OPEN,
+    rd_val_b  => OPEN
+  ); 
+
+  -- SDP info
+  u_dut: ENTITY work.sdp_statistics_offload
+  GENERIC MAP (
+    g_statistics_type => "SST",
+    g_offload_time    => 0,
+    g_beamset_id      => 0
+  )
+  PORT MAP (
+    mm_clk    => mm_clk,
+    mm_rst    => mm_rst,
+
+    dp_clk    => dp_clk,
+    dp_rst    => dp_rst,
+
+    master_mosi => master_mosi,
+    master_miso => master_miso,
+
+    reg_enable_mosi  => enable_mosi,
+    reg_enable_miso  => enable_miso,
+
+    reg_hdr_dat_mosi  => hdr_dat_mosi,
+    reg_hdr_dat_miso  => hdr_dat_miso,
+
+    sdp_info  => sdp_info,
+    gn_index  => gn_index,
+
+    in_sosi   => in_sosi,
+    out_sosi  => out_sosi,
+
+    eth_src_mac  => c_eth_src_mac,
+    udp_src_port => c_udp_src_port,
+    ip_src_addr  => c_ip_src_addr
+  );
+
+END tb;
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