Merge branch 'L2SDP-184' into 'master'

Resolve L2SDP-184

Closes L2SDP-184

See merge request desp/hdl!62

libraries/base/dp/hdllib.cfg

@@ -73,6 +73,8 @@ synth_files =
     src/vhdl/dp_bsn_restore_global.vhd
     src/vhdl/dp_block_gen.vhd
     src/vhdl/dp_block_gen_valid_arr.vhd
+    src/vhdl/dp_block_from_mm.vhd
+    src/vhdl/dp_block_to_mm.vhd
     src/vhdl/dp_bsn_source.vhd
     src/vhdl/dp_bsn_source_v2.vhd
     src/vhdl/dp_bsn_source_reg.vhd
@@ -166,6 +168,9 @@ synth_files =
     src/vhdl/dp_selector_arr.vhd
     src/vhdl/dp_selector.vhd
     src/vhdl/mms_dp_scale.vhd
+    
+    
+    
     tb/vhdl/dp_stream_player.vhd
     tb/vhdl/dp_sosi_recorder.vhd
     tb/vhdl/dp_stream_rec_play.vhd
@@ -184,6 +189,7 @@ test_bench_files =
     tb/vhdl/tb_dp_block_reshape_sync.vhd
     tb/vhdl/tb_dp_block_gen.vhd
     tb/vhdl/tb_dp_block_gen_valid_arr.vhd
+    tb/vhdl/tb_dp_block_from_mm.vhd
     tb/vhdl/tb_dp_bsn_align.vhd
     tb/vhdl/tb_mms_dp_bsn_align.vhd
     tb/vhdl/tb_dp_bsn_monitor.vhd
@@ -251,12 +257,14 @@ test_bench_files =
     tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd
     tb/vhdl/tb_mms_dp_gain_arr.vhd
     tb/vhdl/tb_mms_dp_gain_serial_arr.vhd
+    
 
     tb/vhdl/tb_tb_dp_block_select.vhd
     tb/vhdl/tb_tb_dp_block_reshape.vhd
     tb/vhdl/tb_tb_dp_block_reshape_sync.vhd
     tb/vhdl/tb_tb_dp_block_gen.vhd
     tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd
+    tb/vhdl/tb_tb_dp_block_from_mm.vhd
     tb/vhdl/tb_tb_dp_bsn_align.vhd
     tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
     tb/vhdl/tb_tb_dp_concat.vhd
@@ -318,6 +326,7 @@ regression_test_vhdl =
     tb/vhdl/tb_tb_dp_block_reshape_sync.vhd
     tb/vhdl/tb_tb_dp_block_gen.vhd
     tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd
+    tb/vhdl/tb_tb_dp_block_from_mm.vhd
     tb/vhdl/tb_tb_dp_bsn_align.vhd
     tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
     tb/vhdl/tb_tb_dp_concat.vhd

libraries/base/dp/src/vhdl/dp_block_from_mm.vhd

+-- --------------------------------------------------------------------------
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+
+-- --------------------------------------------------------------------------
+-- Author: 
+-- . Pieter Donker
+-- Purpose:
+-- . Read a block of data from memory mapped (MM) location and stream it as a block of data.
+-- Description:
+-- . https://support.astron.nl/confluence/display/L2M/L5+SDPFW+Design+Document%3A+Subband+filterbank
+-- --------------------------------------------------------------------------
+
+LIBRARY IEEE,common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+ENTITY dp_block_from_mm IS
+  GENERIC (
+    g_data_size  : NATURAL;
+    g_step_size  : NATURAL;
+    g_nof_data   : NATURAL
+  ); 
+  PORT (
+    rst           : IN  STD_LOGIC;
+    clk           : IN  STD_LOGIC;
+    start_pulse   : IN  STD_LOGIC;
+    start_address : IN  NATURAL RANGE 0 TO g_step_size * g_nof_data;
+    mm_done       : OUT STD_LOGIC;
+    mm_mosi       : OUT t_mem_mosi;
+    mm_miso       : IN  t_mem_miso;
+    out_sosi      : OUT t_dp_sosi;
+    out_siso      : IN  t_dp_siso
+  );
+END dp_block_from_mm;
+
+
+ARCHITECTURE rtl OF dp_block_from_mm IS 
+
+  CONSTANT c_mem_size : NATURAL := g_step_size * g_nof_data;
+
+  TYPE t_reg IS RECORD
+    busy       : STD_LOGIC;
+    sop        : STD_LOGIC;
+    eop        : STD_LOGIC;
+    word_index : NATURAL;
+    step_index : NATURAL;
+  END RECORD;
+
+  CONSTANT c_reg_rst : t_reg := ('0', '0', '0', 0, 0);
+
+  SIGNAL r : t_reg;
+  SIGNAL d : t_reg;
+  SIGNAL mm_address      : NATURAL := 0;
+  SIGNAL last_mm_address : NATURAL := 0;
+BEGIN
+
+  last_mm_address <= g_step_size * (g_nof_data - 1) + g_data_size + start_address;
+  mm_address      <= start_address + r.word_index + r.step_index;
+  
+  mm_mosi.address <= TO_MEM_ADDRESS(mm_address);
+
+  out_sosi.data  <= RESIZE_DP_DATA(mm_miso.rddata(c_word_w-1 DOWNTO 0));
+  out_sosi.valid <= mm_miso.rdval;  -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
+  out_sosi.sop   <= r.sop;          -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop
+  out_sosi.eop   <= r.eop;          -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop
+  
+  mm_done <= d.eop;
+
+  p_reg : PROCESS(rst, clk)
+  BEGIN
+    IF rst='1' THEN
+      r <= c_reg_rst;
+    ELSIF rising_edge(clk) THEN
+      r <= d;
+    END IF;
+  END PROCESS;
+
+  p_comb : PROCESS(r, start_pulse, out_siso, mm_address, last_mm_address)
+  BEGIN
+    d <= r;
+    d.sop <= '0';
+    d.eop <= '0';
+    mm_mosi.rd <= '0';
+    IF r.busy = '0' AND start_pulse = '1' THEN
+      -- initiate next block
+      d.busy <= '1';
+    ELSIF r.busy = '1' THEN
+      IF out_siso.ready = '1' THEN
+        -- continue with block
+        mm_mosi.rd <= '1';
+        IF r.word_index < g_data_size - 1 THEN
+          d.word_index <= r.word_index + 1;
+        ELSE
+          d.word_index <= 0;
+          d.step_index <= r.step_index + g_step_size;
+        END IF;
+        
+        -- check start of block
+        IF r.word_index = 0 AND r.step_index = 0 THEN
+          d.sop <= '1';
+        END IF;
+        
+        -- check end of block
+        IF mm_address >= last_mm_address THEN
+          d.eop <= '1';
+          -- prepare for next block
+          d.busy <= '0';
+          d.word_index <= 0;
+          d.step_index <= 0;
+        END IF;
+      END IF;
+    END IF;
+  END PROCESS;
+    
+END rtl;
\ No newline at end of file

libraries/base/dp/src/vhdl/dp_block_to_mm.vhd

+-- --------------------------------------------------------------------------
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+
+-- --------------------------------------------------------------------------
+-- Author: 
+-- . Pieter Donker
+-- Purpose:
+-- . get a block of data from a stream and write it to a memory mapped (MM) location.
+-- Description:
+-- . https://support.astron.nl/confluence/display/L2M/L5+SDPFW+Design+Document%3A+Subband+filterbank
+-- --------------------------------------------------------------------------
+
+LIBRARY IEEE,common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+ENTITY dp_block_to_mm IS
+  GENERIC (
+    g_data_size  : NATURAL;
+    g_step_size  : NATURAL;
+    g_nof_data   : NATURAL
+  ); 
+  PORT (
+    rst           : IN  STD_LOGIC;
+    clk           : IN  STD_LOGIC;
+    start_address : IN  NATURAL RANGE 0 TO g_step_size * g_nof_data;
+    mm_mosi       : OUT t_mem_mosi;
+    in_sosi       : IN  t_dp_sosi
+  );
+END dp_block_to_mm;
+
+
+ARCHITECTURE rtl OF dp_block_to_mm IS 
+
+  CONSTANT c_mem_size : NATURAL := g_step_size * g_nof_data;
+
+  TYPE t_reg IS RECORD
+    wr         : STD_LOGIC;
+    word_index : NATURAL;
+    step_index : NATURAL;
+  END RECORD;
+
+  CONSTANT c_reg_rst : t_reg := ('0', 0, 0);
+
+  SIGNAL r : t_reg;
+  SIGNAL d : t_reg;
+  SIGNAL address : NATURAL := 0;
+
+BEGIN
+  address         <= start_address + r.word_index + r.step_index;
+  mm_mosi.address <= TO_MEM_ADDRESS(address);
+  mm_mosi.wrdata  <= RESIZE_MEM_DATA(in_sosi.data);
+  mm_mosi.wr      <= r.wr;
+  
+  p_reg : PROCESS(rst, clk)
+  BEGIN
+    IF rst='1' THEN
+      r <= c_reg_rst;
+    ELSIF rising_edge(clk) THEN
+      r <= d;
+    END IF;
+  END PROCESS;
+
+  p_comb : PROCESS(r, in_sosi)
+  BEGIN
+    d <= r;
+    d.wr <= '0';
+    -- while receiving block
+    IF in_sosi.valid = '1' THEN
+      -- continue with block
+      IF r.step_index <= c_mem_size THEN
+        d.wr <= '1';
+        IF r.word_index < g_data_size - 1 THEN
+          d.word_index <= r.word_index + 1;
+        ELSE
+          d.word_index <= 0;
+          d.step_index <= r.step_index + g_step_size;
+        END IF;
+      END IF;
+    END IF;
+    -- if end of block
+    IF in_sosi.eop = '1' THEN
+      -- prepare for next block
+      d.word_index <= 0;
+      d.step_index <= 0;
+    END IF;
+  END PROCESS;
+    
+END rtl;
\ No newline at end of file

libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd

+-- --------------------------------------------------------------------------
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+
+-- --------------------------------------------------------------------------
+-- Author: 
+-- . Pieter Donker
+-- Purpose:
+-- . Test bench for dp_block_from_mm.vhd and dp_block_to_mm.vhd 
+--
+-- Description:
+-- . data flow:
+--   p_init_ram --> u_ram_rd --> u_dp_block_from_mm --> dp_block_to_mm --> u_ram_wr --> p_verify_read
+-- . process flow:
+--   p_init_ram --> p_transfer --> p_verify_read / p_verify_check. 
+--   . p_init_ram, initializes u_ram_rd with ascending values.
+--   . p_transfer, u_dp_block_from_mm reads data (using g_data_size and g_step size)
+--     from u_ram_rd and stream it to u_dp_block_to_mm which write it to u_ram_wr.
+--   . p_verify_read, set ram address (using g_data_size and g_step_size) to check and
+--     read value from ram, also set expected ram value.
+--   . p_verify_check, check if ram_value is equal to expected value. 
+-- --------------------------------------------------------------------------
+
+-- > as 10
+-- > run -all  -- signal tb_end will stop the simulation by stopping the clk
+  
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE dp_lib.tb_dp_pkg.ALL;
+
+
+ENTITY tb_dp_block_from_mm IS
+  GENERIC (
+    g_data_size : NATURAL := 2;
+    g_step_size : NATURAL := 4;
+    g_nof_data  : NATURAL := 512
+  );
+END tb_dp_block_from_mm;
+
+ARCHITECTURE tb OF tb_dp_block_from_mm IS
+
+  CONSTANT c_nof_blocks    : NATURAL := g_step_size / g_data_size;
+  CONSTANT c_ram_data_size : NATURAL := g_nof_data * g_data_size * c_nof_blocks;
+  CONSTANT c_ram_adr_w     : NATURAL := ceil_log2(c_ram_data_size);
+
+  CONSTANT c_ram : t_c_mem := (1, c_ram_adr_w, c_word_w, 2**c_ram_adr_w, '0');
+
+  SIGNAL tb_end            : STD_LOGIC := '0';
+  SIGNAL clk               : STD_LOGIC := '1';
+  SIGNAL rst               : STD_LOGIC := '1';
+
+  SIGNAL start_pulse       : STD_LOGIC := '0';
+  SIGNAL start_address     : NATURAL := 0;
+  SIGNAL start_address_dly : NATURAL := 0;
+  SIGNAL block_done        : STD_LOGIC;
+
+  SIGNAL rd_mosi           : t_mem_mosi;
+  SIGNAL rd_miso           : t_mem_miso;
+  
+  SIGNAL blk_sosi          : t_dp_sosi;
+  SIGNAL blk_siso          : t_dp_siso := c_dp_siso_rdy;
+
+  SIGNAL wr_mosi           : t_mem_mosi;
+  SIGNAL wr_miso           : t_mem_miso;
+
+  -- needed for init and verify
+  SIGNAL ram_wr_en  : STD_LOGIC := '0';
+  SIGNAL ram_wr_adr : STD_LOGIC_VECTOR(c_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+  SIGNAL ram_wr_dat : STD_LOGIC_VECTOR(c_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+  SIGNAL ram_rd_en  : STD_LOGIC := '0';
+  SIGNAL ram_rd_adr : STD_LOGIC_VECTOR(c_ram.adr_w-1 DOWNTO 0);
+  SIGNAL ram_rd_dat : STD_LOGIC_VECTOR(c_ram.dat_w-1 DOWNTO 0);
+  SIGNAL ram_rd_val : STD_LOGIC;
+
+  SIGNAL init_done     : STD_LOGIC := '0';
+  SIGNAL transfer_done : STD_LOGIC := '0';
+  
+BEGIN
+
+  clk <= (NOT clk) OR tb_end AFTER clk_period/2;
+  rst <= '1', '0' AFTER clk_period*7;
+  
+  ------------------------------------------------------------------------------
+  -- STIMULI
+  ------------------------------------------------------------------------------
+  
+  start_address_dly <= start_address WHEN rising_edge(clk);  -- dp_block_to_mm is 1 clock behind so set address also 1 clock later. 
+  
+  p_init_ram : PROCESS
+  BEGIN
+    ram_wr_en <= '0';
+    proc_common_wait_until_low(clk, rst);
+    proc_common_wait_some_cycles(clk, 10);
+    FOR i IN 0 TO c_ram_data_size-1 LOOP
+      ram_wr_adr <= TO_UVEC(i, c_ram.adr_w);
+      ram_wr_dat <= TO_UVEC(i, c_ram.dat_w);
+      ram_wr_en  <= '1'; 
+      proc_common_wait_some_cycles(clk, 1);
+    END LOOP;
+    ram_wr_en <= '0'; 
+
+    init_done <= '1';
+    WAIT;
+  END PROCESS;
+
+  p_transfer : PROCESS
+  BEGIN
+    start_pulse   <= '0';
+    start_address <= 0;
+    proc_common_wait_until_high(clk, init_done);
+    FOR i IN 0 TO c_nof_blocks-1 LOOP
+      start_address <= i * g_data_size; 
+      start_pulse <= '1';
+      proc_common_wait_some_cycles(clk, 1);
+      
+      start_pulse <= '0';
+      proc_common_wait_until_high(clk, block_done);
+    END LOOP;
+    proc_common_wait_some_cycles(clk, 1);  -- needed for dp_block_to_mm to proccess last word.
+    transfer_done <= '1';
+    WAIT;
+  END PROCESS;
+
+  p_verify_read : PROCESS
+  BEGIN
+    ram_rd_en  <= '0';
+    ram_rd_adr <= TO_UVEC(0 , c_ram.adr_w);
+    proc_common_wait_until_high(clk, transfer_done);
+    ram_rd_en  <= '1';
+    FOR i IN 0 TO c_ram_data_size-1 LOOP  
+      ram_rd_adr <= TO_UVEC(i, c_ram.adr_w);
+      proc_common_wait_some_cycles(clk, 1);
+    END LOOP;
+    ram_rd_en <= '0'; 
+
+    proc_common_wait_some_cycles(clk, 10);
+    tb_end <= '1';
+    WAIT;
+  END PROCESS;
+
+  p_verify_check: PROCESS
+    VARIABLE v_cnt: NATURAL := 0; 
+  BEGIN
+    proc_common_wait_until_high(clk, transfer_done);
+    WHILE tb_end = '0' LOOP
+      WAIT UNTIL rising_edge(clk);
+      IF ram_rd_val = '1' THEN
+        ASSERT v_cnt = TO_UINT(ram_rd_dat) REPORT "RAM values not equal" SEVERITY ERROR;
+        v_cnt := v_cnt + 1;
+      END IF;
+    END LOOP;
+    WAIT;
+  END PROCESS;
+  
+  ------------------------------------------------------------------------------
+  -- DUT, dp_block_from_mm and dp_block_to_mm
+  ------------------------------------------------------------------------------
+  -- RAM with test data
+  u_ram_rd: ENTITY common_lib.common_ram_r_w
+  GENERIC MAP (
+    g_ram => c_ram
+  )
+  PORT MAP (
+    rst    => rst,
+    clk    => clk,
+    wr_en  => ram_wr_en,
+    wr_adr => ram_wr_adr,
+    wr_dat => ram_wr_dat,
+    rd_en  => rd_mosi.rd,
+    rd_adr => rd_mosi.address(c_ram.adr_w-1 DOWNTO 0),
+    rd_dat => rd_miso.rddata(c_ram.dat_w-1 DOWNTO 0),
+    rd_val => rd_miso.rdval
+  );
+  
+  -- DUT, dp_block_from_mm
+  u_dp_block_from_mm: ENTITY work.dp_block_from_mm
+  GENERIC MAP (
+    g_data_size => g_data_size,
+    g_step_size => g_step_size,
+    g_nof_data  => g_nof_data
+  )
+  PORT MAP (
+    rst           => rst,
+    clk           => clk,
+    start_pulse   => start_pulse,
+    start_address => start_address,
+    mm_done       => block_done,
+    mm_mosi       => rd_mosi,
+    mm_miso       => rd_miso,
+    out_sosi      => blk_sosi,
+    out_siso      => blk_siso
+  );
+    
+  -- DUT, dp_block_to_mm
+  u_dp_block_to_mm: ENTITY work.dp_block_to_mm
+  GENERIC MAP (
+    g_data_size => g_data_size,
+    g_step_size => g_step_size,
+    g_nof_data  => g_nof_data
+  )
+  PORT MAP (
+    rst           => rst,
+    clk           => clk,
+    start_address => start_address_dly,
+    mm_mosi       => wr_mosi,
+    in_sosi       => blk_sosi
+  );
+
+  -- RAM with transferred data
+  u_ram_wr: ENTITY common_lib.common_ram_r_w
+  GENERIC MAP (
+    g_ram => c_ram
+  )
+  PORT MAP (
+    rst    => rst,
+    clk    => clk,
+    wr_en  => wr_mosi.wr,
+    wr_adr => wr_mosi.address(c_ram.adr_w-1 DOWNTO 0),
+    wr_dat => wr_mosi.wrdata(c_ram.dat_w-1 DOWNTO 0),
+    rd_en  => ram_rd_en,
+    rd_adr => ram_rd_adr,
+    rd_dat => ram_rd_dat,
+    rd_val => ram_rd_val
+  );
+
+END tb;

libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd

+-- --------------------------------------------------------------------------
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+
+-- --------------------------------------------------------------------------
+-- Author: 
+-- . Pieter Donker
+-- Purpose:
+-- . Test bench running multiple tb_dp_block_from_mm.vhd with different settings 
+--
+-- Description:
+--   
+-- --------------------------------------------------------------------------
+
+-- > as 10
+-- > run -all  -- signal tb_end will stop the simulation by stopping the clk
+ 
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE work.tb_dp_pkg.ALL;
+
+
+ENTITY tb_tb_dp_block_from_mm IS
+END tb_tb_dp_block_from_mm;
+
+
+ARCHITECTURE tb OF tb_tb_dp_block_from_mm IS
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+BEGIN
+  -- used generics for tb_dp_block_from_mm (g_data_size, g_step_size, g_nof_data)
+  u0_tst_1_1_1   : ENTITY work.tb_dp_block_from_mm GENERIC MAP (1, 1, 1);
+  u1_tst_2_2_17  : ENTITY work.tb_dp_block_from_mm GENERIC MAP (2, 2, 17);
+  u2_tst_2_2_256 : ENTITY work.tb_dp_block_from_mm GENERIC MAP (2, 2, 256);
+  u3_tst_2_4_256 : ENTITY work.tb_dp_block_from_mm GENERIC MAP (2, 4, 256);
+  u4_tst_2_6_256 : ENTITY work.tb_dp_block_from_mm GENERIC MAP (2, 6, 256);
+  u5_tst_2_8_256 : ENTITY work.tb_dp_block_from_mm GENERIC MAP (2, 8, 256);
+  u6_tst_3_6_17  : ENTITY work.tb_dp_block_from_mm GENERIC MAP (3, 6, 17);
+  
+END tb;
+  
\ No newline at end of file