Pass valid signal to the output

libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd

@@ -420,6 +420,7 @@ BEGIN
             rx_src_out_arr(i).data(15 downto 0)  <= (OTHERS => '0');
             f2_div1_cnt_arr(i) <= '0';
           ELSE
+            rx_src_out_arr(i).valid <= jesd204b_rx_link_valid_arr(i);
             IF jesd204b_rx_link_valid_arr(i) = '0' THEN
               rx_src_out_arr(i).data(15 downto 0)  <= (OTHERS => '0');
             ELSE