From 82adcff43b944a4faa173c24d8c69ac12d18ef9a Mon Sep 17 00:00:00 2001
From: Jonathan Hargreaves <hargreaves@jive.eu>
Date: Mon, 20 Jan 2020 09:55:39 +0100
Subject: [PATCH] Pass valid signal to the output
---
.../ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd | 1 +
1 file changed, 1 insertion(+)
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index f569101a19..75f4327b52 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -420,6 +420,7 @@ BEGIN
rx_src_out_arr(i).data(15 downto 0) <= (OTHERS => '0');
f2_div1_cnt_arr(i) <= '0';
ELSE
+ rx_src_out_arr(i).valid <= jesd204b_rx_link_valid_arr(i);
IF jesd204b_rx_link_valid_arr(i) = '0' THEN
rx_src_out_arr(i).data(15 downto 0) <= (OTHERS => '0');
ELSE
--
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