Updated data buffer and block gen ram size

applications/unb1_reorder/src/vhdl/mmm_unb1_reorder.vhd

@@ -133,10 +133,13 @@ ARCHITECTURE str OF mmm_unb1_reorder IS
   CONSTANT c_reg_diag_bg_adr_w         : NATURAL  := 3;
   CONSTANT c_ram_diag_bg_adr_w         : POSITIVE := ceil_log2(g_nof_streams * c_stimuli_length);
   CONSTANT c_reg_diag_data_buf_im_adr_w : NATURAL  := 5;
-  CONSTANT c_ram_diag_data_buf_im_adr_w : NATURAL  := ceil_log2(g_nof_streams * c_stimuli_length);
+--  CONSTANT c_ram_diag_data_buf_im_adr_w : NATURAL  := ceil_log2(g_nof_streams * c_stimuli_length);
+  CONSTANT c_ram_diag_data_buf_im_adr_w : NATURAL  := 13;
   CONSTANT c_reg_diag_data_buf_re_adr_w : NATURAL  := 5;
-  CONSTANT c_ram_diag_data_buf_re_adr_w : NATURAL  := ceil_log2(g_nof_streams * c_stimuli_length);
-  CONSTANT c_ram_ss_ss_transp_adr_w     : NATURAL  := ceil_log2(g_frame_size_in * c_ddr3_seq.rd_chunksize);
+--  CONSTANT c_ram_diag_data_buf_re_adr_w : NATURAL  := ceil_log2(g_nof_streams * c_stimuli_length);
+  CONSTANT c_ram_diag_data_buf_re_adr_w : NATURAL  := 13;
+--  CONSTANT c_ram_ss_ss_transp_adr_w     : NATURAL  := ceil_log2(g_frame_size_in * c_ddr3_seq.rd_chunksize);
+  CONSTANT c_ram_ss_ss_transp_adr_w     : NATURAL  := 13;
 
   -- Actual MM address widths, the MM data width is fixed at the default c_word_w=32
   CONSTANT c_mm_reg_ddr3_addr_w        : NATURAL := ceil_log2(7);