From 81e59c5cfcbba910d6d6b272eaf78a24407470bf Mon Sep 17 00:00:00 2001 From: Zanting <zanting> Date: Fri, 20 Mar 2015 14:56:40 +0000 Subject: [PATCH] Updated data buffer and block gen ram size --- applications/unb1_reorder/src/vhdl/mmm_unb1_reorder.vhd | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/applications/unb1_reorder/src/vhdl/mmm_unb1_reorder.vhd b/applications/unb1_reorder/src/vhdl/mmm_unb1_reorder.vhd index fa7afeb1b7..28adc5d3a8 100644 --- a/applications/unb1_reorder/src/vhdl/mmm_unb1_reorder.vhd +++ b/applications/unb1_reorder/src/vhdl/mmm_unb1_reorder.vhd @@ -133,10 +133,13 @@ ARCHITECTURE str OF mmm_unb1_reorder IS CONSTANT c_reg_diag_bg_adr_w : NATURAL := 3; CONSTANT c_ram_diag_bg_adr_w : POSITIVE := ceil_log2(g_nof_streams * c_stimuli_length); CONSTANT c_reg_diag_data_buf_im_adr_w : NATURAL := 5; - CONSTANT c_ram_diag_data_buf_im_adr_w : NATURAL := ceil_log2(g_nof_streams * c_stimuli_length); +-- CONSTANT c_ram_diag_data_buf_im_adr_w : NATURAL := ceil_log2(g_nof_streams * c_stimuli_length); + CONSTANT c_ram_diag_data_buf_im_adr_w : NATURAL := 13; CONSTANT c_reg_diag_data_buf_re_adr_w : NATURAL := 5; - CONSTANT c_ram_diag_data_buf_re_adr_w : NATURAL := ceil_log2(g_nof_streams * c_stimuli_length); - CONSTANT c_ram_ss_ss_transp_adr_w : NATURAL := ceil_log2(g_frame_size_in * c_ddr3_seq.rd_chunksize); +-- CONSTANT c_ram_diag_data_buf_re_adr_w : NATURAL := ceil_log2(g_nof_streams * c_stimuli_length); + CONSTANT c_ram_diag_data_buf_re_adr_w : NATURAL := 13; +-- CONSTANT c_ram_ss_ss_transp_adr_w : NATURAL := ceil_log2(g_frame_size_in * c_ddr3_seq.rd_chunksize); + CONSTANT c_ram_ss_ss_transp_adr_w : NATURAL := 13; -- Actual MM address widths, the MM data width is fixed at the default c_word_w=32 CONSTANT c_mm_reg_ddr3_addr_w : NATURAL := ceil_log2(7); -- GitLab