Rename ip_altera_mf into ip_stratixiv.

libraries/technology/iobuf/tech_iobuf_component_pkg.vhd

@@ -27,10 +27,10 @@ USE IEEE.STD_LOGIC_1164.ALL;
 PACKAGE tech_iobuf_component_pkg IS
 
   -----------------------------------------------------------------------------
-  -- altera_mf
+  -- ip_stratixiv
   -----------------------------------------------------------------------------
   
-  COMPONENT altera_mf_ddio_in IS
+  COMPONENT ip_stratixiv_ddio_in IS
   GENERIC(
     g_device_family : STRING := "Stratix IV";
     g_width         : NATURAL := 1
@@ -45,7 +45,7 @@ PACKAGE tech_iobuf_component_pkg IS
   );
   END COMPONENT;
   
-  COMPONENT altera_mf_ddio_out IS
+  COMPONENT ip_stratixiv_ddio_out IS
   GENERIC(
     g_device_family : STRING  := "Stratix IV";
     g_width         : NATURAL := 1

libraries/technology/iobuf/tech_iobuf_ddio_in.vhd

@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_altera_mf_lib;
+LIBRARY ip_stratixiv_lib;
 
 ENTITY tech_iobuf_ddio_in IS
   GENERIC (
@@ -48,8 +48,8 @@ ARCHITECTURE str OF tech_iobuf_ddio_in IS
 
 BEGIN
 
-  gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
-    u0 : altera_mf_ddio_in
+  gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+    u0 : ip_stratixiv_ddio_in
     GENERIC MAP ("Stratix IV", g_width)
     PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
   END GENERATE;

libraries/technology/iobuf/tech_iobuf_ddio_out.vhd

@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_altera_mf_lib;
+LIBRARY ip_stratixiv_lib;
 
 ENTITY tech_iobuf_ddio_out IS
   GENERIC (
@@ -48,8 +48,8 @@ ARCHITECTURE str OF tech_iobuf_ddio_out IS
 
 BEGIN
 
-  gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
-    u0 : altera_mf_ddio_out
+  gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+    u0 : ip_stratixiv_ddio_out
     GENERIC MAP ("Stratix IV", g_width)
     PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
   END GENERATE;