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Commit 7f96d943 authored by Reinier van der Walle's avatar Reinier van der Walle
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Merge branch 'master' into 'L2SDP-131'

Master

See merge request desp/hdl!43
parents 802e66ab 38cf9c3d
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3 merge requests!100Removed text for XSub that is now written in Confluence Subband correlator...,!44Resolve L2SDP-131,!43Master
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with 6216 additions and 909 deletions
......@@ -13,13 +13,16 @@ synth_files =
test_bench_files =
tb/vhdl/tb_lofar2_unb2b_adc.vhd
tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
regression_test_vhdl =
tb/vhdl/tb_lofar2_unb2b_adc.vhd
tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
[modelsim_project_file]
modelsim_copy_files =
src/data data
tb/wave/wave_multichannel.do .
tb/wave/readregs.do .
......
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......@@ -187,6 +187,41 @@ BEGIN
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_jesd204b : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
PORT MAP(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
u_mm_file_reg_dp_shiftram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
PORT MAP(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
u_mm_file_reg_bsn_source : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
PORT MAP(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
u_mm_file_reg_bsn_scheduler : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
u_mm_file_reg_bsn_monitor_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
u_mm_file_reg_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
PORT MAP(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
u_mm_file_ram_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
PORT MAP(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
u_mm_file_ram_diag_data_buf_jesd : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
u_mm_file_reg_diag_data_buf_jesd : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
u_mm_file_ram_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
u_mm_file_reg_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
u_mm_file_ram_aduh_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
PORT MAP(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
u_mm_file_reg_aduh_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
PORT MAP(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
......
......@@ -125,8 +125,8 @@ ARCHITECTURE str OF node_adc_input_and_timing IS
-- Waveform Generator
CONSTANT c_wg_buf_directory : STRING := "data/";
CONSTANT c_wg_buf_dat_w : NATURAL := c_unb2b_board_peripherals_mm_reg_default.ram_diag_wg_dat_w;
CONSTANT c_wg_buf_addr_w : NATURAL := c_unb2b_board_peripherals_mm_reg_default.ram_diag_wg_adr_w;
CONSTANT c_wg_buf_dat_w : NATURAL := 18; --default value of WG that fits 14 bits of ADC data
CONSTANT c_wg_buf_addr_w : NATURAL := 10; --default value of WG for 1024 samples;
SIGNAL wg_out_ovr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL wg_out_val : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL wg_out_data : STD_LOGIC_VECTOR(g_nof_streams*c_wg_buf_dat_w-1 DOWNTO 0);
......
-------------------------------------------------------------------------------
--
-- Copyright 2020
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Author: R. van der Walle
-- Purpose: Self-checking testbench for simulating lofar2_unb2b_adc using WG data.
--
-- Description:
-- MM control actions:
--
-- 1) Enable calc mode for WG via reg_diag_wg with:
-- freq = 20MHz
-- ampl = 0.5 * 2**13
--
-- 2) Read current BSN from reg_bsn_scheduler_wg and write reg_bsn_scheduler_wg
-- to trigger start of WG at BSN.
--
-- 3) Read WG data via ram_aduh_mon into sp_sample and replay sp_sample for
-- analogue view in Wave window:
--
-- 4) Read ADUH monitor power sum for via reg_aduh_mon and verify with
-- c_exp_wg_power_sp.
-- View sp_power_sum in Wave window
--
-- Usage:
-- > as 7 # default
-- > as 12 # for detailed debugging
-- > run -a
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE common_lib.common_str_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
ENTITY tb_lofar2_unb2b_adc_wg IS
END tb_lofar2_unb2b_adc_wg;
ARCHITECTURE tb OF tb_lofar2_unb2b_adc_wg IS
CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
CONSTANT c_node_nr : NATURAL := 0;
CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_ext_clk_period : TIME := 5 ns;
CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
CONSTANT c_pps_period : NATURAL := 1000;
CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
CONSTANT c_cable_delay : TIME := 12 ns
;
CONSTANT c_sample_freq : NATURAL := c_unb2b_board_ext_clk_freq_200M/10**6; -- 200 MSps
CONSTANT c_sample_period : TIME := (10**6 / c_sample_freq) * 1 ps;
CONSTANT c_nof_sync : NATURAL := 5;
CONSTANT c_nof_block_per_sync : NATURAL := 16;
CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
CONSTANT c_nof_points : NATURAL := 1024;
CONSTANT c_nof_taps : NATURAL := 16;
CONSTANT c_subband_period : TIME := c_nof_points * c_sample_period;
-- WG
CONSTANT c_full_scale_ampl : REAL := REAL(2**(18-1)-1); -- = full scale of WG
CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
CONSTANT c_ampl_sp : NATURAL := 2**(14-1)/2; -- in number of lsb
CONSTANT c_subband_sp : REAL := 51.2; -- Select subband at index 512/10 = 51.2 = 20 MHz
CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/512.0; -- subband freq = Fs/512 = 200 MSps/512 = 390625 Hz sinus
CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
CONSTANT c_exp_wg_power_sp : REAL := REAL(c_ampl_sp**2)/2.0 * REAL(c_nof_points*c_nof_block_per_sync);
-- ADUH
CONSTANT c_mon_buffer_nof_samples : NATURAL := 1024; --samples per stream
CONSTANT c_mon_buffer_nof_words : NATURAL := c_mon_buffer_nof_samples;
-- MM
CONSTANT c_mm_file_reg_ppsh : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
CONSTANT c_mm_file_reg_bsn_source : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE";
CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
CONSTANT c_mm_file_reg_aduh_mon : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_ADUH_MONITOR";
CONSTANT c_mm_file_ram_aduh_mon : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ADUH_MONITOR";
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL tb_clk : STD_LOGIC := '0';
SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
-- WG
SIGNAL dbg_c_exp_wg_power_sp : REAL := c_exp_wg_power_sp;
SIGNAL sp_samples : t_integer_arr(0 TO c_mon_buffer_nof_samples-1) := (OTHERS=>0);
SIGNAL sp_sample : INTEGER := 0;
SIGNAL sp_power_sum : UNSIGNED(63 DOWNTO 0);
SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
-- DUT
SIGNAL ext_clk : STD_LOGIC := '0';
SIGNAL pps : STD_LOGIC := '0';
SIGNAL ext_pps : STD_LOGIC := '0';
SIGNAL pps_rst : STD_LOGIC := '0';
SIGNAL WDI : STD_LOGIC;
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
SIGNAL eth_clk : STD_LOGIC := '0';
SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
SIGNAL pmbus_scl : STD_LOGIC;
SIGNAL pmbus_sda : STD_LOGIC;
-- back transceivers
SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
-- jesd204b syncronization signals
SIGNAL jesd204b_sysref : STD_LOGIC;
SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
sens_scl <= 'H'; -- pull up
sens_sda <= 'H'; -- pull up
pmbus_scl <= 'H'; -- pull up
pmbus_sda <= 'H'; -- pull up
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
jesd204b_sysref <= pps;
ext_pps <= pps;
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc : ENTITY work.lofar2_unb2b_adc
GENERIC MAP (
g_design_name => "lofar2_unb2b_adc_one_node",
g_design_note => "Lofar2 adc with one node",
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
g_sim_node_nr => c_node_nr
)
PORT MAP (
-- GENERAL
CLK => ext_clk,
PPS => pps,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
VERSION => c_version,
ID => c_id,
TESTIO => open,
-- I2C Interface to Sensors
SENS_SC => sens_scl,
SENS_SD => sens_sda,
PMBUS_SC => pmbus_scl,
PMBUS_SD => pmbus_sda,
PMBUS_ALERT => open,
-- 1GbE Control Interface
ETH_CLK => eth_clk,
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp,
-- LEDs
QSFP_LED => open,
-- back transceivers
JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
JESD204B_REFCLK => JESD204B_REFCLK,
-- jesd204b syncronization signals
JESD204B_SYSREF => jesd204b_sysref,
JESD204B_SYNC_N => jesd204b_sync_n
);
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
p_mm_stimuli : PROCESS
VARIABLE v_bsn : NATURAL;
VARIABLE v_sp_power_sum : REAL;
BEGIN
-- Wait for DUT power up after reset
WAIT FOR 1 us;
proc_common_wait_until_hi_lo(ext_clk, ext_pps);
----------------------------------------------------------------------------
-- Enable BS
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3, 0, tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 0, tb_clk); -- Init BSN = 0
mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk); -- nof_block_per_sync
mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
----------------------------------------------------------------------------
-- Enable WG
----------------------------------------------------------------------------
-- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3)
-- nof_samples[31:16] --> <= c_ram_wg_size=1024
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, INTEGER( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER(c_subband_sp * c_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, INTEGER(REAL(c_ampl_sp) * c_wg_ampl_lsb), tb_clk); -- ampl
-- Read current BSN
mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk);
mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
proc_common_wait_some_cycles(tb_clk, 1);
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
v_bsn := c_bsn_start_wg;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
-- Wait for ADUH monitor to have filled with WG data
WAIT FOR c_subband_period*c_nof_taps;
WAIT FOR c_subband_period*2;
----------------------------------------------------------------------------
-- WG data : read ADUH monitor buffer
----------------------------------------------------------------------------
-- Wait for start of sync interval
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
"UNSIGNED", rd_data, ">=", c_nof_block_per_sync*2, -- this is the wait until condition
c_subband_period, tb_clk);
WAIT FOR c_subband_period; -- ensure that one block of samples has filled the ADUH monitor buffer after the sync
-- Read via MM
FOR I IN 0 TO c_mon_buffer_nof_words-1 LOOP
mmf_mm_bus_rd(c_mm_file_ram_aduh_mon, I, rd_data, tb_clk);
sp_samples(I) <= TO_SINT(rd_data(15 DOWNTO 0));
END LOOP;
-- Play to have waveform in time to allow viewing as analogue in the Wave Window
FOR I IN 0 TO c_mon_buffer_nof_words-1 LOOP
proc_common_wait_some_cycles(ext_clk, 1);
sp_sample <= sp_samples(I);
END LOOP;
WAIT FOR c_subband_period*3;
---------------------------------------------------------------------------
-- Read ADUH monitor power sum
---------------------------------------------------------------------------
-- Wait for start of sync interval
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
"UNSIGNED", rd_data, ">=", c_nof_block_per_sync*3, -- this is the wait until condition
c_subband_period, tb_clk);
-- Read ADUH monitor power sum
mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk); -- read low part
sp_power_sum(31 DOWNTO 0) <= UNSIGNED(rd_data);
mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk); -- read high part
sp_power_sum(63 DOWNTO 32) <= UNSIGNED(rd_data);
proc_common_wait_some_cycles(tb_clk, 1);
---------------------------------------------------------------------------
-- Verification
---------------------------------------------------------------------------
-- Convert UNSIGNED sp_power_sum to REAL
v_sp_power_sum := REAL(REAL(TO_INTEGER(sp_power_sum(61 DOWNTO 30)))*REAL(2**30) + REAL(TO_INTEGER(sp_power_sum(29 DOWNTO 0))));
ASSERT v_sp_power_sum > c_lo_factor * c_exp_wg_power_sp REPORT "Wrong SP power for SP 0" SEVERITY ERROR;
ASSERT v_sp_power_sum < c_hi_factor * c_exp_wg_power_sp REPORT "Wrong SP power for SP 0" SEVERITY ERROR;
---------------------------------------------------------------------------
-- End Simulation
---------------------------------------------------------------------------
sim_done <= '1';
proc_common_wait_some_cycles(ext_clk, 100);
proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
WAIT;
END PROCESS;
END tb;
......@@ -498,6 +498,266 @@ Do not support more than one block per packet, because for SST and BST the paylo
Statistics packet fields format: See ICD SC-SDP in Polarion
The ToD in SC and the ToD in SDPTR shall be within +-10 ms. This value is a compromise between using a measurable value, a feasible value with NTP and not adding too much timing margin between SC and SDP.
Direct:
Per memory mapped (MM) point in the register map of a PN on a UniBoard2:
/unb[0:7]/pn[0:3]/mm/peripheral/field
Composite:
Per functional point per antenna band, where antenna band is Low Band (= SDP - LBAS) or High Band (= SDP - HBAS)
Monitor and control of SDP
The monitoring and control of the SDP Translator and of the SDP Firmware is done via the OPC-UA interface of the SDP Translator. The SDP Translator is central to entire SDP.
The SDP Firmware is distirubuted
List of products with M&C in SDP
Path Product name
/sdptr SDP Translator
/band[0:1]/bsp SDPFW Board Support Package
/band[0:1]/general SDPFW
/band[0:1]/ait SDPFW ADC Input and Timing
/band[0:1]/fsub SDPFW Subband Filterbank
/band[0:1]/bf SDPFW Beamformer
/band[0:1]/ri SDPFW Ring
/band[0:1]/xc SDPFW Subband Correlator
/band[0:1]/tbuf SDPFW Transient Buffer
/band[0:1]/tdet SDPFW Transient Detector
List of control points per antenna band and per product in SDP
Path Point
/sdptr /sdp_info
/band[0:1]/bsp /pn_image
/band[0:1]/general /sdp_info
/data_flags
/signal_input_range
/band[0:1]/ait /processing_enable
/si_sample_delay
/si_waveform_generator
/band[0:1]/fsub /pfir_coefficients
/subband_weights
/sst_select
/sst_offload_destination
/sst_offload_enable
/band[0:1]/bf /subband_select
/weights_xx
/weights_yy
/bst_offload_destination
/bst_offload_enable
/beamlet_offload_destination
/beamlet_offload_enable
/band[0:1]/ri/
/band[0:1]/xc/
/band[0:1]/tbuf/
/band[0:1]/tdet/
List of monitor points per antenna band and per product in SDP
Path Point
/sdptr /tr_info
/tr_timing
/tr_network
/band[0:1]/bsp /pn_info
/pps_timing
/mc_network
/band[0:1]/general /sdp_info
/band[0:1]/ait /sdp_status
/si_timing
/si_mean
/si_sigma
/si_data_buffer
/si_histogram
/band[0:1]/fsub - If sst_offload_enable = off, then the SST can be read via direct monitoring.
/band[0:1]/bf - If bst_offload_enable = off, then the BST can be read via direct monitoring.
/band[0:1]/ri/
/band[0:1]/xc/
/band[0:1]/tbuf/
/band[0:1]/tdet/
For the SDP Firmware the
/sdptr/
Control:
- sdp_info:
. station_id
Monitor:
- tr_info:
. software name and version
. temperature ? (or via EC2 ?)
- tr_timing:
. NTP status
. PPS status : Locked, not locked, unknown
- Not locked = NTP time at SDPTR does not coincide within +- 1 ms with PPS top of second at SDPFW
- Locked = NTP time at SDPTR is aligned within +- 1 ms with the PPS top of second at SDPFW → based on the offset_cnt information from the PPSH in one of the PN in the SDPHW / SDPFW
- Unknown when the PPS information in SDPFW is not stable or not available
- tr_network:
. SC-SDPTR link status at SDPTR : nof tx pkts, nof rx pkts, nof crc errors, nof retransmissions, nof timeouts
. SDPTR-SDPFW link status at SDPTR : nof tx pkts, nof rx pkts, nof crc errors, nof retransmissions, nof timeouts
/band[0:1]/bsp/
Control for all allocated PN
- pn_image : design name
Monitor per allocated PN
- pn_info : unb_hw_version, gn_id, rn_id, fw_image (design_name with date, time and revision stamp, design note), f_adc, fsub_type
- pn_regmap : mmap
- pps_timing :
. STF-SDPFW PPS status at SDPFW:
'not active' = measured PPS count >> f_adc = 200M and clipped at 2**28 - 1
'asynchronous' = measured PPS count != expected count -1, +0, or +1
'active' = measured PPS count = expected count -1, +0, or +1
'active and stable' → measured PPS count has been equal to expected count -1, +0, or +1 since last time it was monitored.
- eth1g :
. SDPTR-SDPFW link status at SDPFW : nof tx pkts, nof rx pkts, nof crc errors, nof retransmissions, nof timeouts
band[0:1]/general
Control
- sdp_info: observation_id, nyquist_zone_index
- data_flags : beam repositioning flag, calibrated subbands flag
- signal_input_range : R_ant = (O_si, N_si) → this will allocate N_pn = N_si / S_pn PN starting with PN with rn_id = O_si / S_pn
Both the offset and the amount are a multiple of S_pn = 12 signals inputs, because there are S_pn = 12 signal inputs per FPGA processing node (PN) in the SDP Hardware and because the PN are interconnected in a fixed sequence.
Monitor per allocated PN
- sdp_info : f_adc, fsub_type
- eth10g
/band[0:1]/ait/ (AIT = adc input and timing)
Control:
- processing_enable : Start, stop
- si_sample_delay, Sample delay buffer : (unit16)ait_sample_delay[R_ant]
- si_waveform_generator (WG) : start at BSN, stop, freq[R_ant], ampl[R_ant], phs[R_ant]
Monitor:
- sdp_status : 'stopped', 'running' or running and stable' → based on read BSN from BSN source being equal and incrementing correctly at all PN
- si_timing : (enum)ait_timing[R_ant]
'not active' = no data
'active' = there is data
'active and stable and not aligned' = there is a stable flow of data since last time it was monitored, but the recovered LMFC is not aligned with the local FPGA_SYSREF
'aligned' = there is a stable flow of data and it is aligned
'aligned and stable' = there is a stable flow of data and it is aligned since the last time it was monitored
Monitor on request:
- si_mean : (float)ait_mean[R_ant]
- si_sigma : (float)ait_sigma[R_ant]
- si_data_buffer : (sint16)ait_data_buffer[R_ant][N] (N = 1k samples)
- si_histogram : (uint32)ait_histogram[R_ant][N] (N = 1k bins)
/band[0:1]/fsub/ (Fsub = subband filterbank)
Control:
- pfir_coefficients: FIR filter coefficients: (sint16)pfir_coefficients[N_taps*N_fft]
- subband_weights : (cint16)subband_weights[R_ant][N_sub]
- sst_input_select : (bool)sst_input_select, select calibrated or not calibrated for SST
- sst_offload_destination : SST UDP offload header
. Destination : (tuple)sst_offload_destination = (MAC address, IPv4 address, UDP port)
- sst_offload_enable : SST UDP offload : (bool)sst_offload_enable = on, off
Monitor: None, if sst_offload = off, then the SST can be read via direct monitoring.
/band[0:1]/bf/ (BF = beamformer)
Control:
- Subband select per beam: (uint16)beamlet_subband_select[N_beamlets]
- Beamformer weights for X polarization beams: (cint16)beamlet_weights_xx[N_ant][N_beamlets]
- Beamformer weights for Y polarization beams: (cint16)beamlet_weights_yy[N_ant][N_beamlets]
- BST UDP offload header
. Destination : (tuple)bst_offload_destination[N_beamsets] = (MAC address, IPv4 address, UDP port)
- BST UDP offload : (bool)bst_offload[N_beamsets] = on, off
Monitor: None, if bst_offload = off, then the BST can be read via direct monitoring.
/band[0:1]/ri/ (RI = ring)
/band[0:1]/xc/ (XC = subband correlator)
/band[0:1]/tbuf/ (Tbuf = Transient Buffer)
/band[0:1]/tdet/ (Tdet = Transient Detector)
De SDP Translator is valt ook onder beheer EC2.
###################################################################################################
# L3 ICD 11423 SDPTR - SDPFW
ToD
The SDP maintains timing using the PPS and the sample clock. Hence SDP knows about seconds, but it does not know the time of day (ToD) since 1970 at the PPS. After power up SDP needs to get the ToD information from SC to be able to timestamp SDP output data. Both SC and SDP know the PPS grid. The SC has to provide the ToD information at PPS in one PPS interval and then SDP will apply that ToD in the next PPS interval. The ToD at the PPS is defined at the block sequence number (BSN) grid, using initial BSN and a BSN offset [Does SC care about BSN. IMHO that's SDP internal.] [AD-4]. The SC only has to provide the ToD once, because after that SDP can maintain the ToD by counting PPS pulses and sample clock periods. The SDP provides a monitoring point that reports the time since last PPS. [Do you really mean time since last PPS? What's the purpose? Assuming time distribution is done properly within the station, then all subsystem will receive the PPS at the same time. AFAIK, SC doesn't need to align with the PPS. Maybe you're referring to the ToD when the last PPS occurred? That could indeed be useful to discover inconsistencies between SC and SDP.] The SC can read this monitoring point to check whether is own PPS is aligned to the PPS in SDP.
PPS monitoring
The monitoring of the status of the PPS in the SDP Firmware reveals:
whether the PPS period is correct and stable. This allows SC to monitor whether processing by SDP is possible. If the period is wrong or not stable, then this indicates an issue between the STF and SDP. The stable interval is defined by the time since between monitoring requests by SC of the PPS period. [We have to be careful here, not to make the same mistakes as in APERTIF, where the misalignment detection generated a lot of false positives. What problem are we trying to solve here? Only when we've answered that question, it's time to ask ourselves what is the best solution?]
the number of sample clock cycles since last PPS, upon reception of the monitoring message. This allows SC to monitor the synchronisation between SC and SD
BSN timing grid
The ToD information defines the BSN timing grid and shall consist of [AD-3]: [Again, isn't this all SDP internals? AFAIC, SC provides the ToD, only. Whatever SDP does internally with BSN is none of SC's business.]
an initial BSN that counts subband periods T_sub,
a BSN offset in ADC sample periods T_adc relative to the initial PPS
SDPTR requirements:
SC-SDP synchronisation. The Time of Day (ToD) in SC and the PPS in SDP shall be synchronous within a margin of ±100 ms, to ensure that real-time [There is no real-time communication.] M&C communication that starts in a certain PPS interval can also complete in that PPS interval.
PPS monitoring. SC shall monitor the status of the PPS in the SDP Firmware, [Like I said before, this is IMHO the wrong (APERTIF) approach. Do we really want to go that route again?] as listed in LOFAR2-8852 - PPS monitoring.
Time of Day (ToD) information at PPS. SC shall provide the initial ToD information to SDP within the pulse per second (PPS) interval that precedes the PPS that corresponds to that initial ToD. For subsequent PPS intervals the SDP maintains the ToD information by itself.
Block Sequence Number (BSN) timing grid. SC shall provide the ToD information as defined in LOFAR2-8853 - BSN timing grid.
Block Sequence Number (BSN) monitoring. The SC shall monitor the BSN monitoring points in the SDP Firmware to monitor whether the processing in SDP is synchronous.
SDP processing start and restart.The SC shall start the SDP processing by providing the ToD information to SDP. The SDP processing can be started or restarted at any PPS (i.e. no need to wait for an even second like in LOFAR1).
SDPFW requirements:
SC-SDP synchronisation. The Timeof Day (ToD) in SC and the PPS in SDP shall be synchronous within a margin of ±100 ms, to ensure that real-time M&C communication that starts in a certain PPS interval can also complete in that PPS interval.
PPS monitor. The SDP Firmware shall report the status of the PPS upon request, as listed in LOFAR2-8852 - PPS monitoring.
Time of Day (ToD) information at PPS. SDP Firmware shall apply the received ToD information at the next pulse per second (PPS). For subsequent PPS intervals the SDP Firmware shall maintain the ToD information by counting sample clock cycles.
Block Sequence Number (BSN) timing grid. [I'm not sure why this should be in the ICD. Like I said, BSN is IMHO SDP internal.] SDP shall apply the ToD information as defined in LOFAR2-8853 - BSN timing grid.
Block Sequence Number (BSN) monitor. The SDP Firmware shall provide monitoring points that show the status of the timing within a processing node (PN) and the status of the timing alignment between PN within SDP.
SDP processing start and restart.The SDP shall start the SDP processing at the next PPS, when it has received the ToD information from SC. The SDP processing can be started or restarted at any PPS.
I.011211.SDPTR.SDPFW d.7, Data - Synchronous control using time activated control
In LOFAR1LOFAR1: RSP driver moet 2 x een setting sturen naar het RSP board, vanwege het per seconde swappen. Dit moeten we voorkomen in LOFAR2.
Time activated control is control that takes effect in the SDP Firmware at a scheduled instant. The scheduled instant uses the block sequence number (BSN) grid [AD-4], so it is not restricted to the seconds grid. Time activated control implies that the SDP Firmware uses a dual page register to store the control data. One page can accept new control data, while the control data in the other page is being used. At a trigger the pages swap or shift, dependent on whether the register consist of RAM or logic. In LOFAR1 the dual page registers swap at the PPS, independent of whether the RSP driver had updated the setting. This causes that the RSP driver has to set the same setting twice in two successive PPS intervals, to avoid that the page swap of a RAM register results in using old page values. For LOFAR2.0 this is avoided by letting the SC control when the register in SDP should swap, instead of at any PPS. Therefore the time activated control in LOFAR2.0 uses a trigger that is scheduled by SC [I don't think I agree with that approach. Unless I completely misunderstand the issue here, but why should SC have to ensure SDP's internal consistency?!?! This definitely needs to be discussed.] instead of by the PPS. The scheduled instant for the trigger is typically in the future. If the scheduled instant is in the past, then SDP will not do the page swap. If the scheduled instant is at BSN = 0 then SDP will do the page swap immediately. The trigger can be rescheduled by SC as long as its time instant has not yet past. SC has to provide a trigger instant per page swap, otherwise the pages do not swap. Hence SC has full control over when and how often time activated control is applied.
Linked Work Items has parent: LOFAR2-8812 - Station Control (L3-SC) - SDP Translator (L4-SDPTR)
[Create Link] List of time-activated control pointsThe time activated control is used for controlling:
starting of the subband correlator,
starting the waveform generators
SC requirements:
Time activated control. For time activated control the SC shall provide the control data and a timestamp. The timestamp schedules an instant at the BSN grid. The SDP Firmware shall activate the control at that timestamp. The SC shall use time-activated control for the control points listed in LOFAR2-8854 - List of time-activated control points.
SDP requirements:
Time activated control. For time activated control the SC shall provide the control data and a timestamp. The timestamp schedules an instant at the BSN grid. The SDP Firmware shall activate the control at that timestamp. The SDP shall use time-activated control for the control points listed in LOFAR2-8854 - List of time-activated control points.
###################################################################################################
# L2 ICD 11207 RCU2S-SDP
......
......@@ -19,7 +19,7 @@ set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to PPS
# IO Standard Assignments from Gijs (excluding memory)
set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_CLK
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ETH_CLK
#set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ETH_CLK
set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[0]
set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[0](n)"
set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[1]
......
......@@ -55,10 +55,10 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
#set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
#set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
#set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
#set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 1.8V
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
......
......@@ -21,6 +21,7 @@ test_bench_files =
tb/vhdl/tb_mmf_st_sst.vhd
tb/vhdl/tb_st_histogram.vhd
tb/vhdl/tb_mms_st_histogram.vhd
tb/vhdl/tb_tb_st_histogram.vhd
regression_test_vhdl =
tb/vhdl/tb_st_acc.vhd
......
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-------------------------------------------------------------------------------
--
-- Copyright 2020
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Author: J.W.E. Oudman
-- Purpose:
-- Description:
-- .
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY tb_tb_st_histogram IS
END tb_tb_st_histogram;
ARCHITECTURE tb OF tb_tb_st_histogram IS
SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
BEGIN
-- Usage
-- > as 8
-- > run -all
-- > Testbenches are self-checking
--
-- g_sync_length : NATURAL := 200;
-- g_nof_sync : NATURAL := 3;
-- g_data_w : NATURAL := 4;
-- g_nof_bins : NATURAL := 8;
-- g_nof_data : NATURAL := 200;
-- --g_str : STRING := "freq.density";
-- g_valid_gap : STRING := "custom"; -- "false" or "true" or "custom"
-- g_snk_in_data_sim_type : STRING := "same rw" -- "counter" or "toggle" or "same rw" or "mix"
--
-- do test for different number of bins
u_tb_st_histogram_counter_nof_2 : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 1, 2, 200, "true" , "counter" );
u_tb_st_histogram_counter_nof_4 : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 2, 4, 200, "true" , "counter" );
u_tb_st_histogram_counter : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 4, 8, 200, "true" , "counter" );
-- do tests for RAM delay issues
u_tb_st_histogram_toggle : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 4, 8, 200, "true" , "toggle" );
u_tb_st_histogram_same_rw : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 4, 8, 200, "custom", "same rw" );
END tb;
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
vmap altera_jesd204_180 ./work/
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx/sim"
vcom "$IP_DIR/../altera_jesd204_180/sim/ip_arria10_e1sg_jesd204b_rx_altera_jesd204_180_3rumeui.vhd" -work altera_jesd204_180
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
vcom "$IP_DIR/../altera_jesd204_180/sim/ip_arria10_e1sg_jesd204b_tx_altera_jesd204_180_too2kia.vhd" -work altera_jesd204_180
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