diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
index 6df0316fe12cef1d40a9b83ef1204b0a48990d67..c854fbb25961c387d6ba0ccfda5a233dab1bd38c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
@@ -13,13 +13,16 @@ synth_files =
     
 test_bench_files = 
     tb/vhdl/tb_lofar2_unb2b_adc.vhd
+    tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
     tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
 
 regression_test_vhdl =
     tb/vhdl/tb_lofar2_unb2b_adc.vhd
+    tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
 
 [modelsim_project_file]
 modelsim_copy_files = 
+    src/data data
     tb/wave/wave_multichannel.do .
     tb/wave/readregs.do .
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/data/diag_sin_1024x18.hex b/applications/lofar2/designs/lofar2_unb2b_adc/src/data/diag_sin_1024x18.hex
new file mode 100644
index 0000000000000000000000000000000000000000..8e1a9a6faab8c1ab9daa1fbedea2d1a2a6f16fdf
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/data/diag_sin_1024x18.hex
@@ -0,0 +1,1025 @@
+:03000000000000FD
+:03000100000324D5
+:03000200000648AD
+:0300030000096D84
+:03000400000C915C
+:03000500000FB534
+:030006000012D80D
+:030007000015FCE5
+:0300080000191FBD
+:03000900001C4296
+:03000A00001F656F
+:03000B0000228848
+:03000C000025AA22
+:03000D000028CCFC
+:03000E00002BEED6
+:03000F00002F0FB0
+:0300100000322F8C
+:0300110000354F68
+:0300120000386F44
+:03001300003B8E21
+:03001400003EACFF
+:030015000041CADD
+:030016000044E8BB
+:030017000048049A
+:03001800004B207A
+:03001900004E3B5B
+:03001A000051563C
+:03001B0000546F1F
+:03001C0000578802
+:03001D00005AA0E6
+:03001E00005DB7CB
+:03001F000060CDB1
+:030020000063E397
+:030021000066F77F
+:03002200006A0A67
+:03002300006D1D50
+:0300240000702E3B
+:0300250000733E27
+:0300260000764D14
+:0300270000795B02
+:03002800007C68F1
+:03002900007F73E2
+:03002A0000827DD4
+:03002B00008587C6
+:03002C0000888EBB
+:03002D00008B95B0
+:03002E00008E9AA7
+:03002F0000919E9F
+:030030000094A099
+:030031000097A194
+:03003200009AA091
+:03003300009D9E8F
+:0300340000A09B8E
+:0300350000A39590
+:0300360000A68F92
+:0300370000A98697
+:0300380000AC7C9D
+:0300390000AF71A4
+:03003A0000B264AD
+:03003B0000B555B8
+:03003C0000B844C5
+:03003D0000BB31D4
+:03003E0000BE1DE4
+:03003F0000C107F6
+:0300400000C3EF0B
+:0300410000C6D521
+:0300420000C9B939
+:0300430000CC9B53
+:0300440000CF7B6F
+:0300450000D25A8C
+:0300460000D536AC
+:0300470000D810CE
+:0300480000DAE8F3
+:0300490000DDBE19
+:03004A0000E09241
+:03004B0000E3646B
+:03004C0000E63398
+:03004D0000E900C7
+:03004E0000EBCBF9
+:03004F0000EE942C
+:0300500000F15A62
+:0300510000F41F99
+:0300520000F6E0D5
+:0300530000F9A011
+:0300540000FC5D50
+:0300550000FF1792
+:030056000101CFD6
+:030057000104851C
+:0300580001073865
+:030059000109E9B1
+:03005A00010C9600
+:03005B00010F4250
+:03005C000111EBA4
+:03005D00011491FA
+:03005E0001173453
+:03005F000119D5AF
+:03006000011C730D
+:03006100011F0E6E
+:030062000121A7D2
+:0300630001243D38
+:030064000126D0A2
+:030065000129600E
+:03006600012BED7E
+:03006700012E77F0
+:030068000130FF65
+:03006900013383DD
+:03006A0001360557
+:03006B00013883D6
+:03006C00013AFF57
+:03006D00013D78DA
+:03006E00013FED62
+:03006F0001425FEC
+:030070000144CF79
+:0300710001473B09
+:030072000149A49D
+:03007300014C0934
+:03007400014E6CCE
+:030075000150CB6C
+:030076000153270C
+:03007700015580B0
+:030078000157D657
+:03007900015A2801
+:03007A00015C77AF
+:03007B00015EC360
+:03007C0001610B14
+:03007D00016350CC
+:03007E0001659188
+:03007F000167CF47
+:03008000016A0909
+:03008100016C40CF
+:03008200016E7498
+:030083000170A366
+:030084000172D036
+:030085000174F90A
+:0300860001771EE1
+:0300870001793FBD
+:03008800017B5D9C
+:03008900017D777F
+:03008A00017F8E65
+:03008B000181A14F
+:03008C000183B03D
+:03008D000185BC2E
+:03008E000187C324
+:03008F000189C71D
+:03009000018BC71A
+:03009100018DC41A
+:03009200018FBC1F
+:030093000191B127
+:030094000193A134
+:0300950001958E44
+:0300960001977758
+:0300970001995C70
+:03009800019B3D8C
+:03009900019D1AAC
+:03009A00019EF3D1
+:03009B0001A0C9F8
+:03009C0001A29A24
+:03009D0001A46754
+:03009E0001A63088
+:03009F0001A7F5C1
+:0300A00001A9B6FD
+:0300A10001AB723E
+:0300A20001AD2B82
+:0300A30001AEDFCC
+:0300A40001B09018
+:0300A50001B23C69
+:0300A60001B3E4BF
+:0300A70001B58818
+:0300A80001B72776
+:0300A90001B8C3D8
+:0300AA0001BA5A3E
+:0300AB0001BBEDA9
+:0300AC0001BD7B18
+:0300AD0001BF058B
+:0300AE0001C08B03
+:0300AF0001C20D7E
+:0300B00001C38AFF
+:0300B10001C50383
+:0300B20001C6780C
+:0300B30001C7E89A
+:0300B40001C9542B
+:0300B50001CABBC2
+:0300B60001CC1E5C
+:0300B70001CD7DFB
+:0300B80001CED79F
+:0300B90001D02C47
+:0300BA0001D17EF3
+:0300BB0001D2CAA5
+:0300BC0001D4125A
+:0300BD0001D55614
+:0300BE0001D695D3
+:0300BF0001D7D096
+:0300C00001D9065D
+:0300C10001DA372A
+:0300C20001DB64FB
+:0300C30001DC8DD0
+:0300C40001DDB0AB
+:0300C50001DECF8A
+:0300C60001DFEA6D
+:0300C70001E10054
+:0300C80001E21141
+:0300C90001E31E32
+:0300CA0001E42628
+:0300CB0001E52923
+:0300CC0001E62822
+:0300CD0001E72226
+:0300CE0001E8172F
+:0300CF0001E9073D
+:0300D00001E9F350
+:0300D10001EADA67
+:0300D20001EBBD82
+:0300D30001EC9AA3
+:0300D40001ED73C8
+:0300D50001EE47F2
+:0300D60001EF1720
+:0300D70001EFE155
+:0300D80001F0A78D
+:0300D90001F168CA
+:0300DA0001F2240C
+:0300DB0001F2DC53
+:0300DC0001F38E9F
+:0300DD0001F43CEF
+:0300DE0001F4E545
+:0300DF0001F5899F
+:0300E00001F629FD
+:0300E10001F6C362
+:0300E20001F759CA
+:0300E30001F7E939
+:0300E40001F875AB
+:0300E50001F8FC23
+:0300E60001F97F9E
+:0300E70001F9FC20
+:0300E80001FA74A6
+:0300E90001FAE831
+:0300EA0001FB57C0
+:0300EB0001FBC056
+:0300EC0001FC25EF
+:0300ED0001FC858E
+:0300EE0001FCE032
+:0300EF0001FD37D9
+:0300F00001FD8887
+:0300F10001FDD43A
+:0300F20001FE1CF0
+:0300F30001FE5EAD
+:0300F40001FE9C6E
+:0300F50001FED534
+:0300F60001FF08FF
+:0300F70001FF37CF
+:0300F80001FF61A4
+:0300F90001FF867E
+:0300FA0001FFA65D
+:0300FB0001FFC141
+:0300FC0001FFD829
+:0300FD0001FFE917
+:0300FE0001FFF50A
+:0300FF0001FFFD01
+:0301000001FFFFFD
+:0301010001FFFDFE
+:0301020001FFF505
+:0301030001FFE910
+:0301040001FFD820
+:0301050001FFC136
+:0301060001FFA650
+:0301070001FF866F
+:0301080001FF6193
+:0301090001FF37BC
+:03010A0001FF08EA
+:03010B0001FED51D
+:03010C0001FE9C55
+:03010D0001FE5E92
+:03010E0001FE1CD3
+:03010F0001FDD41B
+:0301100001FD8866
+:0301110001FD37B6
+:0301120001FCE00D
+:0301130001FC8567
+:0301140001FC25C6
+:0301150001FBC02B
+:0301160001FB5793
+:0301170001FAE802
+:0301180001FA7475
+:0301190001F9FCED
+:03011A0001F97F69
+:03011B0001F8FCEC
+:03011C0001F87572
+:03011D0001F7E9FE
+:03011E0001F7598D
+:03011F0001F6C323
+:0301200001F629BC
+:0301210001F5895C
+:0301220001F4E500
+:0301230001F43CA8
+:0301240001F38E56
+:0301250001F2DC08
+:0301260001F224BF
+:0301270001F1687B
+:0301280001F0A73C
+:0301290001EFE102
+:03012A0001EF17CB
+:03012B0001EE479B
+:03012C0001ED736F
+:03012D0001EC9A48
+:03012E0001EBBD25
+:03012F0001EADA08
+:0301300001E9F3EF
+:0301310001E907DA
+:0301320001E817CA
+:0301330001E722BF
+:0301340001E628B9
+:0301350001E529B8
+:0301360001E426BB
+:0301370001E31EC3
+:0301380001E211D0
+:0301390001E100E1
+:03013A0001DFEAF8
+:03013B0001DECF13
+:03013C0001DDB032
+:03013D0001DC8D55
+:03013E0001DB647E
+:03013F0001DA37AB
+:0301400001D906DC
+:0301410001D7D013
+:0301420001D6954E
+:0301430001D5568D
+:0301440001D412D1
+:0301450001D2CA1A
+:0301460001D17E66
+:0301470001D02CB8
+:0301480001CED70E
+:0301490001CD7D68
+:03014A0001CC1EC7
+:03014B0001CABB2B
+:03014C0001C95492
+:03014D0001C7E8FF
+:03014E0001C6786F
+:03014F0001C503E4
+:0301500001C38A5E
+:0301510001C20DDB
+:0301520001C08B5E
+:0301530001BF05E4
+:0301540001BD7B6F
+:0301550001BBEDFE
+:0301560001BA5A91
+:0301570001B8C329
+:0301580001B727C5
+:0301590001B58865
+:03015A0001B3E40A
+:03015B0001B23CB2
+:03015C0001B0905F
+:03015D0001AEDF11
+:03015E0001AD2BC5
+:03015F0001AB727F
+:0301600001A9B63C
+:0301610001A7F5FE
+:0301620001A630C3
+:0301630001A4678D
+:0301640001A29A5B
+:0301650001A0C92D
+:03016600019EF304
+:03016700019D1ADD
+:03016800019B3DBB
+:0301690001995C9D
+:03016A0001977783
+:03016B0001958E6D
+:03016C000193A15B
+:03016D000191B14C
+:03016E00018FBC42
+:03016F00018DC43B
+:03017000018BC739
+:030171000189C73A
+:030172000187C33F
+:030173000185BC47
+:030174000183B054
+:030175000181A164
+:03017600017F8E78
+:03017700017D7790
+:03017800017B5DAB
+:0301790001793FCA
+:03017A0001771EEC
+:03017B000174F913
+:03017C000172D03D
+:03017D000170A36B
+:03017E00016E749B
+:03017F00016C40D0
+:03018000016A0908
+:030181000167CF44
+:0301820001659183
+:03018300016350C5
+:0301840001610B0B
+:03018500015EC355
+:03018600015C77A2
+:03018700015A28F2
+:030188000157D646
+:030189000155809D
+:03018A00015327F7
+:03018B000150CB55
+:03018C00014E6CB5
+:03018D00014C0919
+:03018E000149A480
+:03018F0001473BEA
+:030190000144CF58
+:0301910001425FC9
+:03019200013FED3D
+:03019300013D78B3
+:03019400013AFF2E
+:03019500013883AB
+:030196000136052A
+:03019700013383AE
+:030198000130FF34
+:03019900012E77BD
+:03019A00012BED49
+:03019B00012960D7
+:03019C000126D069
+:03019D0001243DFD
+:03019E000121A795
+:03019F00011F0E2F
+:0301A000011C73CC
+:0301A1000119D56C
+:0301A2000117340E
+:0301A300011491B3
+:0301A4000111EB5B
+:0301A500010F4205
+:0301A600010C96B3
+:0301A7000109E962
+:0301A80001073814
+:0301A900010485C9
+:0301AA000101CF81
+:0301AB0000FF173B
+:0301AC0000FC5DF7
+:0301AD0000F9A0B6
+:0301AE0000F6E078
+:0301AF0000F41F3A
+:0301B00000F15A01
+:0301B10000EE94C9
+:0301B20000EBCB94
+:0301B30000E90060
+:0301B40000E6332F
+:0301B50000E36400
+:0301B60000E092D4
+:0301B70000DDBEAA
+:0301B80000DAE882
+:0301B90000D8105B
+:0301BA0000D53637
+:0301BB0000D25A15
+:0301BC0000CF7BF6
+:0301BD0000CC9BD8
+:0301BE0000C9B9BC
+:0301BF0000C6D5A2
+:0301C00000C3EF8A
+:0301C10000C10773
+:0301C20000BE1D5F
+:0301C30000BB314D
+:0301C40000B8443C
+:0301C50000B5552D
+:0301C60000B26420
+:0301C70000AF7115
+:0301C80000AC7C0C
+:0301C90000A98604
+:0301CA0000A68FFD
+:0301CB0000A395F9
+:0301CC0000A09BF5
+:0301CD00009D9EF4
+:0301CE00009AA0F4
+:0301CF000097A1F5
+:0301D0000094A0F8
+:0301D10000919EFC
+:0301D200008E9A02
+:0301D300008B9509
+:0301D40000888E12
+:0301D5000085871B
+:0301D60000827D27
+:0301D700007F7333
+:0301D800007C6840
+:0301D90000795B4F
+:0301DA0000764D5F
+:0301DB0000733E70
+:0301DC0000702E82
+:0301DD00006D1D95
+:0301DE00006A0AAA
+:0301DF000066F7C0
+:0301E0000063E3D6
+:0301E1000060CDEE
+:0301E200005DB706
+:0301E300005AA01F
+:0301E40000578839
+:0301E50000546F54
+:0301E6000051566F
+:0301E700004E3B8C
+:0301E800004B20A9
+:0301E900004804C7
+:0301EA000044E8E6
+:0301EB000041CA06
+:0301EC00003EAC26
+:0301ED00003B8E46
+:0301EE0000386F67
+:0301EF0000354F89
+:0301F00000322FAB
+:0301F100002F0FCD
+:0301F200002BEEF1
+:0301F3000028CC15
+:0301F4000025AA39
+:0301F5000022885D
+:0301F600001F6582
+:0301F700001C42A7
+:0301F80000191FCC
+:0301F9000015FCF2
+:0301FA000012D818
+:0301FB00000FB53D
+:0301FC00000C9163
+:0301FD0000096D89
+:0301FE00000648B0
+:0301FF00000324D6
+:03020000000000FB
+:0302010003FCDC1F
+:0302020003F9B845
+:0302030003F6936C
+:0302040003F36F92
+:0302050003F04BB8
+:0302060003ED28DD
+:0302070003EA0403
+:0302080003E6E129
+:0302090003E3BE4E
+:03020A0003E09B73
+:03020B0003DD7898
+:03020C0003DA56BC
+:03020D0003D734E0
+:03020E0003D41204
+:03020F0003D0F128
+:0302100003CDD14A
+:0302110003CAB16C
+:0302120003C7918E
+:0302130003C472AF
+:0302140003C154CF
+:0302150003BE36EF
+:0302160003BB180F
+:0302170003B7FC2E
+:0302180003B4E04C
+:0302190003B1C569
+:03021A0003AEAA86
+:03021B0003AB91A1
+:03021C0003A878BC
+:03021D0003A560D6
+:03021E0003A249EF
+:03021F00039F3307
+:03022000039C1D1F
+:0302210003990935
+:030222000395F64B
+:030223000392E360
+:03022400038FD273
+:03022500038CC285
+:030226000389B396
+:030227000386A5A6
+:03022800038398B5
+:0302290003808DC2
+:03022A00037D83CE
+:03022B00037A79DA
+:03022C00037772E3
+:03022D0003746BEC
+:03022E00037166F3
+:03022F00036E62F9
+:03023000036B60FD
+:0302310003685F00
+:0302320003656001
+:0302330003626201
+:03023400035F6500
+:03023500035C6BFC
+:03023600035971F8
+:0302370003567AF1
+:03023800035384E9
+:0302390003508FE0
+:03023A00034D9CD5
+:03023B00034AABC8
+:03023C000347BCB9
+:03023D000344CFA8
+:03023E000341E396
+:03023F00033EF982
+:03024000033C116B
+:0302410003392B53
+:0302420003364739
+:030243000333651D
+:03024400033085FF
+:03024500032DA6E0
+:03024600032ACABE
+:030247000327F09A
+:0302480003251873
+:030249000322424B
+:03024A00031F6E21
+:03024B00031C9CF5
+:03024C000319CDC6
+:03024D0003170094
+:03024E0003143561
+:03024F0003116C2C
+:03025000030EA6F4
+:03025100030BE1BB
+:030252000309207D
+:030253000306603F
+:030254000303A3FE
+:030255000300E9BA
+:0302560002FE3174
+:0302570002FB7B2C
+:0302580002F8C8E1
+:0302590002F61793
+:03025A0002F36A42
+:03025B0002F0BEF0
+:03025C0002EE159A
+:03025D0002EB6F42
+:03025E0002E8CCE7
+:03025F0002E62B89
+:0302600002E38D29
+:0302610002E0F2C6
+:0302620002DE5960
+:0302630002DBC3F8
+:0302640002D9308C
+:0302650002D6A01E
+:0302660002D413AC
+:0302670002D18938
+:0302680002CF01C1
+:0302690002CC7D47
+:03026A0002C9FBCB
+:03026B0002C77D4A
+:03026C0002C501C7
+:03026D0002C28842
+:03026E0002C013B8
+:03026F0002BDA12C
+:0302700002BB319D
+:0302710002B8C50B
+:0302720002B65C75
+:0302730002B3F7DC
+:0302740002B19440
+:0302750002AF35A0
+:0302760002ACD9FE
+:0302770002AA8058
+:0302780002A82AAF
+:0302790002A5D803
+:03027A0002A38953
+:03027B0002A13DA0
+:03027C00029EF5EA
+:03027D00029CB030
+:03027E00029A6F72
+:03027F00029831B1
+:030280000295F7ED
+:030281000293C025
+:0302820002918C5A
+:03028300028F5D8A
+:03028400028D30B8
+:03028500028B07E2
+:030286000288E209
+:030287000286C12B
+:030288000284A34A
+:0302890002828965
+:03028A000280727D
+:03028B00027E5F91
+:03028C00027C50A1
+:03028D00027A44AE
+:03028E0002783DB6
+:03028F00027639BB
+:03029000027439BC
+:0302910002723CBA
+:03029200027044B3
+:03029300026E4FA9
+:03029400026C5F9A
+:03029500026A7288
+:0302960002688972
+:030297000266A458
+:030298000264C33A
+:030299000262E618
+:03029A0002610DF1
+:03029B00025F37C8
+:03029C00025D669A
+:03029D00025B9968
+:03029E000259D032
+:03029F0002580BF7
+:0302A00002564AB9
+:0302A10002548E76
+:0302A2000252D530
+:0302A300025121E4
+:0302A400024F7096
+:0302A500024DC443
+:0302A600024C1CEB
+:0302A700024A7890
+:0302A8000248D930
+:0302A90002473DCC
+:0302AA000245A664
+:0302AB00024413F7
+:0302AC0002428586
+:0302AD000240FB11
+:0302AE00023F7597
+:0302AF00023DF31A
+:0302B000023C7697
+:0302B100023AFD11
+:0302B20002398886
+:0302B300023818F6
+:0302B4000236AC63
+:0302B500023545CA
+:0302B6000233E22E
+:0302B7000232838D
+:0302B800023129E7
+:0302B900022FD43D
+:0302BA00022E828F
+:0302BB00022D36DB
+:0302BC00022BEE24
+:0302BD00022AAA68
+:0302BE0002296BA7
+:0302BF00022830E2
+:0302C0000226FA19
+:0302C1000225C94A
+:0302C20002249C77
+:0302C300022373A0
+:0302C400022250C3
+:0302C500022131E2
+:0302C600022016FD
+:0302C700021F0013
+:0302C800021DEF25
+:0302C900021CE232
+:0302CA00021BDA3A
+:0302CB00021AD73D
+:0302CC000219D83C
+:0302CD000218DE36
+:0302CE000217E92B
+:0302CF000216F91B
+:0302D00002160D06
+:0302D100021526ED
+:0302D200021443D0
+:0302D300021366AD
+:0302D40002128D86
+:0302D5000211B95A
+:0302D6000210E92A
+:0302D70002101FF3
+:0302D800020F59B9
+:0302D900020E987A
+:0302DA00020DDC36
+:0302DB00020D24ED
+:0302DC00020C729F
+:0302DD00020BC44D
+:0302DE00020B1BF5
+:0302DF00020A7799
+:0302E0000209D739
+:0302E10002093DD2
+:0302E2000208A768
+:0302E300020817F7
+:0302E40002078B83
+:0302E50002070409
+:0302E6000206818C
+:0302E70002060408
+:0302E80002058C80
+:0302E900020518F3
+:0302EA000204A962
+:0302EB00020440CA
+:0302EC000203DB2F
+:0302ED0002037B8E
+:0302EE00020320E8
+:0302EF000202C93F
+:0302F0000202788F
+:0302F10002022CDA
+:0302F2000201E422
+:0302F3000201A263
+:0302F400020164A0
+:0302F50002012BD8
+:0302F6000200F80B
+:0302F7000200C939
+:0302F80002009F62
+:0302F90002007A86
+:0302FA0002005AA5
+:0302FB0002003FBF
+:0302FC00020028D5
+:0302FD00020017E5
+:0302FE0002000BF0
+:0302FF00020003F7
+:03030000020001F7
+:03030100020003F4
+:0303020002000BEB
+:03030300020017DE
+:03030400020028CC
+:0303050002003FB4
+:0303060002005A98
+:0303070002007A77
+:0303080002009F51
+:030309000200C926
+:03030A000200F8F6
+:03030B0002012BC1
+:03030C0002016487
+:03030D000201A248
+:03030E000201E405
+:03030F0002022CBB
+:030310000202786E
+:030311000202C91C
+:03031200020320C3
+:0303130002037B67
+:030314000203DB06
+:030315000204409F
+:030316000204A935
+:03031700020518C4
+:0303180002058C4F
+:03031900020604D5
+:03031A0002068157
+:03031B00020704D2
+:03031C0002078B4A
+:03031D00020817BC
+:03031E000208A72B
+:03031F0002093D93
+:030320000209D7F8
+:03032100020A7756
+:03032200020B1BB0
+:03032300020BC406
+:03032400020C7256
+:03032500020D24A2
+:03032600020DDCE9
+:03032700020E982B
+:03032800020F5968
+:0303290002101FA0
+:03032A000210E9D5
+:03032B000211B903
+:03032C0002128D2D
+:03032D0002136652
+:03032E0002144373
+:03032F000215268E
+:0303300002160DA5
+:030331000216F9B8
+:030332000217E9C6
+:030333000218DECF
+:030334000219D8D3
+:03033500021AD7D2
+:03033600021BDACD
+:03033700021CE2C3
+:03033800021DEFB4
+:03033900021F00A0
+:03033A0002201688
+:03033B000221316B
+:03033C000222504A
+:03033D0002237325
+:03033E0002249CFA
+:03033F000225C9CB
+:030340000226FA98
+:030341000228305F
+:0303420002296B22
+:03034300022AAAE1
+:03034400022BEE9B
+:03034500022D3650
+:03034600022E8202
+:03034700022FD4AE
+:0303480002312956
+:03034900023283FA
+:03034A000233E299
+:03034B0002354533
+:03034C000236ACCA
+:03034D000238185B
+:03034E00023988E9
+:03034F00023AFD72
+:03035000023C76F6
+:03035100023DF377
+:03035200023F75F2
+:030353000240FB6A
+:03035400024285DD
+:030355000244134C
+:030356000245A6B7
+:0303570002473D1D
+:030358000248D97F
+:03035900024A78DD
+:03035A00024C1C36
+:03035B00024DC48C
+:03035C00024F70DD
+:03035D0002512129
+:03035E000252D573
+:03035F0002548EB7
+:0303600002564AF8
+:0303610002580B34
+:030362000259D06D
+:03036300025B99A1
+:03036400025D66D1
+:03036500025F37FD
+:0303660002610D24
+:030367000262E649
+:030368000264C369
+:030369000266A485
+:03036A000268899D
+:03036B00026A72B1
+:03036C00026C5FC1
+:03036D00026E4FCE
+:03036E00027044D6
+:03036F0002723CDB
+:03037000027439DB
+:03037100027639D8
+:0303720002783DD1
+:03037300027A44C7
+:03037400027C50B8
+:03037500027E5FA6
+:0303760002807290
+:0303770002828976
+:030378000284A359
+:030379000286C138
+:03037A000288E214
+:03037B00028B07EB
+:03037C00028D30BF
+:03037D00028F5D8F
+:03037E0002918C5D
+:03037F000293C026
+:030380000295F7EC
+:03038100029831AE
+:03038200029A6F6D
+:03038300029CB029
+:03038400029EF5E1
+:0303850002A13D95
+:0303860002A38946
+:0303870002A5D8F4
+:0303880002A82A9E
+:0303890002AA8045
+:03038A0002ACD9E9
+:03038B0002AF3589
+:03038C0002B19427
+:03038D0002B3F7C1
+:03038E0002B65C58
+:03038F0002B8C5EC
+:0303900002BB317C
+:0303910002BDA109
+:0303920002C01393
+:0303930002C2881B
+:0303940002C5019E
+:0303950002C77D1F
+:0303960002C9FB9E
+:0303970002CC7D18
+:0303980002CF0190
+:0303990002D18905
+:03039A0002D41377
+:03039B0002D6A0E7
+:03039C0002D93053
+:03039D0002DBC3BD
+:03039E0002DE5923
+:03039F0002E0F287
+:0303A00002E38DE8
+:0303A10002E62B46
+:0303A20002E8CCA2
+:0303A30002EB6FFB
+:0303A40002EE1551
+:0303A50002F0BEA5
+:0303A60002F36AF5
+:0303A70002F61744
+:0303A80002F8C890
+:0303A90002FB7BD9
+:0303AA0002FE311F
+:0303AB000300E963
+:0303AC000303A3A5
+:0303AD00030660E4
+:0303AE0003092020
+:0303AF00030BE15C
+:0303B000030EA693
+:0303B10003116CC9
+:0303B200031435FC
+:0303B3000317002D
+:0303B4000319CD5D
+:0303B500031C9C8A
+:0303B600031F6EB4
+:0303B700032242DC
+:0303B80003251802
+:0303B9000327F027
+:0303BA00032ACA49
+:0303BB00032DA669
+:0303BC0003308586
+:0303BD00033365A2
+:0303BE00033647BC
+:0303BF0003392BD4
+:0303C000033C11EA
+:0303C100033EF9FF
+:0303C2000341E311
+:0303C3000344CF21
+:0303C4000347BC30
+:0303C500034AAB3D
+:0303C600034D9C48
+:0303C70003508F51
+:0303C80003538458
+:0303C90003567A5E
+:0303CA0003597163
+:0303CB00035C6B65
+:0303CC00035F6567
+:0303CD0003626266
+:0303CE0003656064
+:0303CF0003685F61
+:0303D000036B605C
+:0303D100036E6256
+:0303D2000371664E
+:0303D30003746B45
+:0303D4000377723A
+:0303D500037A792F
+:0303D600037D8321
+:0303D70003808D13
+:0303D80003839804
+:0303D9000386A5F3
+:0303DA000389B3E1
+:0303DB00038CC2CE
+:0303DC00038FD2BA
+:0303DD000392E3A5
+:0303DE000395F68E
+:0303DF0003990976
+:0303E000039C1D5E
+:0303E100039F3344
+:0303E20003A2492A
+:0303E30003A5600F
+:0303E40003A878F3
+:0303E50003AB91D6
+:0303E60003AEAAB9
+:0303E70003B1C59A
+:0303E80003B4E07B
+:0303E90003B7FC5B
+:0303EA0003BB183A
+:0303EB0003BE3618
+:0303EC0003C154F6
+:0303ED0003C472D4
+:0303EE0003C791B1
+:0303EF0003CAB18D
+:0303F00003CDD169
+:0303F10003D0F145
+:0303F20003D4121F
+:0303F30003D734F9
+:0303F40003DA56D3
+:0303F50003DD78AD
+:0303F60003E09B86
+:0303F70003E3BE5F
+:0303F80003E6E138
+:0303F90003EA0410
+:0303FA0003ED28E8
+:0303FB0003F04BC1
+:0303FC0003F36F99
+:0303FD0003F69371
+:0303FE0003F9B848
+:0303FF0003FCDC20
+:00000001FF
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/data/diag_sin_1024x8.hex b/applications/lofar2/designs/lofar2_unb2b_adc/src/data/diag_sin_1024x8.hex
new file mode 100644
index 0000000000000000000000000000000000000000..b73e91443a5e6cae9a7ed345ac4f13c13c08bca1
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/data/diag_sin_1024x8.hex
@@ -0,0 +1,1025 @@
+:0100000000FF
+:0100010001FD
+:0100020002FB
+:0100030002FA
+:0100040003F8
+:0100050004F6
+:0100060005F4
+:0100070005F3
+:0100080006F1
+:0100090007EF
+:01000A0008ED
+:01000B0009EB
+:01000C0009EA
+:01000D000AE8
+:01000E000BE6
+:01000F000CE4
+:010010000CE3
+:010011000DE1
+:010012000EDF
+:010013000FDD
+:0100140010DB
+:0100150010DA
+:0100160011D8
+:0100170012D6
+:0100180013D4
+:0100190013D3
+:01001A0014D1
+:01001B0015CF
+:01001C0016CD
+:01001D0016CC
+:01001E0017CA
+:01001F0018C8
+:0100200019C6
+:010021001AC4
+:010022001AC3
+:010023001BC1
+:010024001CBF
+:010025001DBD
+:010026001DBC
+:010027001EBA
+:010028001FB8
+:0100290020B6
+:01002A0020B5
+:01002B0021B3
+:01002C0022B1
+:01002D0023AF
+:01002E0023AE
+:01002F0024AC
+:0100300025AA
+:0100310026A8
+:0100320026A7
+:0100330027A5
+:0100340028A3
+:0100350029A1
+:0100360029A0
+:010037002A9E
+:010038002B9C
+:010039002C9A
+:01003A002C99
+:01003B002D97
+:01003C002E95
+:01003D002E94
+:01003E002F92
+:01003F003090
+:01004000318E
+:01004100318D
+:01004200328B
+:010043003389
+:010044003388
+:010045003486
+:010046003584
+:010047003682
+:010048003681
+:01004900377F
+:01004A00387D
+:01004B00387C
+:01004C00397A
+:01004D003A78
+:01004E003A77
+:01004F003B75
+:010050003C73
+:010051003D71
+:010052003D70
+:010053003E6E
+:010054003F6C
+:010055003F6B
+:010056004069
+:010057004167
+:010058004166
+:010059004264
+:01005A004362
+:01005B004361
+:01005C00445F
+:01005D00455D
+:01005E00455C
+:01005F00465A
+:010060004758
+:010061004757
+:010062004855
+:010063004854
+:010064004952
+:010065004A50
+:010066004A4F
+:010067004B4D
+:010068004C4B
+:010069004C4A
+:01006A004D48
+:01006B004E46
+:01006C004E45
+:01006D004F43
+:01006E004F42
+:01006F005040
+:01007000513E
+:01007100513D
+:01007200523B
+:01007300523A
+:010074005338
+:010075005436
+:010076005435
+:010077005533
+:010078005532
+:010079005630
+:01007A00562F
+:01007B00572D
+:01007C00582B
+:01007D00582A
+:01007E005928
+:01007F005927
+:010080005A25
+:010081005A24
+:010082005B22
+:010083005B21
+:010084005C1F
+:010085005D1D
+:010086005D1C
+:010087005E1A
+:010088005E19
+:010089005F17
+:01008A005F16
+:01008B006014
+:01008C006013
+:01008D006111
+:01008E006110
+:01008F00620E
+:01009000620D
+:01009100630B
+:01009200630A
+:010093006408
+:010094006407
+:010095006505
+:010096006504
+:010097006602
+:010098006601
+:010099006600
+:01009A0067FE
+:01009B0067FD
+:01009C0068FB
+:01009D0068FA
+:01009E0069F8
+:01009F0069F7
+:0100A0006AF5
+:0100A1006AF4
+:0100A2006AF3
+:0100A3006BF1
+:0100A4006BF0
+:0100A5006CEE
+:0100A6006CED
+:0100A7006DEB
+:0100A8006DEA
+:0100A9006DE9
+:0100AA006EE7
+:0100AB006EE6
+:0100AC006FE4
+:0100AD006FE3
+:0100AE006FE2
+:0100AF0070E0
+:0100B00070DF
+:0100B10070DE
+:0100B20071DC
+:0100B30071DB
+:0100B40071DA
+:0100B50072D8
+:0100B60072D7
+:0100B70072D6
+:0100B80073D4
+:0100B90073D3
+:0100BA0073D2
+:0100BB0074D0
+:0100BC0074CF
+:0100BD0074CE
+:0100BE0075CC
+:0100BF0075CB
+:0100C00075CA
+:0100C10076C8
+:0100C20076C7
+:0100C30076C6
+:0100C40076C5
+:0100C50077C3
+:0100C60077C2
+:0100C70077C1
+:0100C80078BF
+:0100C90078BE
+:0100CA0078BD
+:0100CB0078BC
+:0100CC0079BA
+:0100CD0079B9
+:0100CE0079B8
+:0100CF0079B7
+:0100D0007AB5
+:0100D1007AB4
+:0100D2007AB3
+:0100D3007AB2
+:0100D4007AB1
+:0100D5007BAF
+:0100D6007BAE
+:0100D7007BAD
+:0100D8007BAC
+:0100D9007BAB
+:0100DA007CA9
+:0100DB007CA8
+:0100DC007CA7
+:0100DD007CA6
+:0100DE007CA5
+:0100DF007CA4
+:0100E0007DA2
+:0100E1007DA1
+:0100E2007DA0
+:0100E3007D9F
+:0100E4007D9E
+:0100E5007D9D
+:0100E6007D9C
+:0100E7007E9A
+:0100E8007E99
+:0100E9007E98
+:0100EA007E97
+:0100EB007E96
+:0100EC007E95
+:0100ED007E94
+:0100EE007E93
+:0100EF007E92
+:0100F0007E91
+:0100F1007E90
+:0100F2007F8E
+:0100F3007F8D
+:0100F4007F8C
+:0100F5007F8B
+:0100F6007F8A
+:0100F7007F89
+:0100F8007F88
+:0100F9007F87
+:0100FA007F86
+:0100FB007F85
+:0100FC007F84
+:0100FD007F83
+:0100FE007F82
+:0100FF007F81
+:010100007F7F
+:010101007F7E
+:010102007F7D
+:010103007F7C
+:010104007F7B
+:010105007F7A
+:010106007F79
+:010107007F78
+:010108007F77
+:010109007F76
+:01010A007F75
+:01010B007F74
+:01010C007F73
+:01010D007F72
+:01010E007F71
+:01010F007E71
+:010110007E70
+:010111007E6F
+:010112007E6E
+:010113007E6D
+:010114007E6C
+:010115007E6B
+:010116007E6A
+:010117007E69
+:010118007E68
+:010119007E67
+:01011A007D67
+:01011B007D66
+:01011C007D65
+:01011D007D64
+:01011E007D63
+:01011F007D62
+:010120007D61
+:010121007C61
+:010122007C60
+:010123007C5F
+:010124007C5E
+:010125007C5D
+:010126007C5C
+:010127007B5C
+:010128007B5B
+:010129007B5A
+:01012A007B59
+:01012B007B58
+:01012C007A58
+:01012D007A57
+:01012E007A56
+:01012F007A55
+:010130007A54
+:010131007954
+:010132007953
+:010133007952
+:010134007951
+:010135007851
+:010136007850
+:01013700784F
+:01013800784E
+:01013900774E
+:01013A00774D
+:01013B00774C
+:01013C00764C
+:01013D00764B
+:01013E00764A
+:01013F007649
+:010140007549
+:010141007548
+:010142007547
+:010143007447
+:010144007446
+:010145007445
+:010146007345
+:010147007344
+:010148007343
+:010149007243
+:01014A007242
+:01014B007241
+:01014C007141
+:01014D007140
+:01014E00713F
+:01014F00703F
+:01015000703E
+:01015100703D
+:010152006F3D
+:010153006F3C
+:010154006F3B
+:010155006E3B
+:010156006E3A
+:010157006D3A
+:010158006D39
+:010159006D38
+:01015A006C38
+:01015B006C37
+:01015C006B37
+:01015D006B36
+:01015E006A36
+:01015F006A35
+:010160006A34
+:010161006934
+:010162006933
+:010163006833
+:010164006832
+:010165006732
+:010166006731
+:010167006631
+:010168006630
+:01016900662F
+:01016A00652F
+:01016B00652E
+:01016C00642E
+:01016D00642D
+:01016E00632D
+:01016F00632C
+:01017000622C
+:01017100622B
+:01017200612B
+:01017300612A
+:01017400602A
+:010175006029
+:010176005F29
+:010177005F28
+:010178005E28
+:010179005E27
+:01017A005D27
+:01017B005D26
+:01017C005C26
+:01017D005B26
+:01017E005B25
+:01017F005A25
+:010180005A24
+:010181005924
+:010182005923
+:010183005823
+:010184005822
+:010185005722
+:010186005622
+:010187005621
+:010188005521
+:010189005520
+:01018A005420
+:01018B00541F
+:01018C00531F
+:01018D00521F
+:01018E00521E
+:01018F00511E
+:01019000511D
+:01019100501D
+:010192004F1D
+:010193004F1C
+:010194004E1C
+:010195004E1B
+:010196004D1B
+:010197004C1B
+:010198004C1A
+:010199004B1A
+:01019A004A1A
+:01019B004A19
+:01019C004919
+:01019D004819
+:01019E004818
+:01019F004718
+:0101A0004717
+:0101A1004617
+:0101A2004517
+:0101A3004516
+:0101A4004416
+:0101A5004316
+:0101A6004315
+:0101A7004215
+:0101A8004115
+:0101A9004114
+:0101AA004014
+:0101AB003F14
+:0101AC003F13
+:0101AD003E13
+:0101AE003D13
+:0101AF003D12
+:0101B0003C12
+:0101B1003B12
+:0101B2003A12
+:0101B3003A11
+:0101B4003911
+:0101B5003811
+:0101B6003810
+:0101B7003710
+:0101B8003610
+:0101B900360F
+:0101BA00350F
+:0101BB00340F
+:0101BC00330F
+:0101BD00330E
+:0101BE00320E
+:0101BF00310E
+:0101C000310D
+:0101C100300D
+:0101C2002F0D
+:0101C3002E0D
+:0101C4002E0C
+:0101C5002D0C
+:0101C6002C0C
+:0101C7002C0B
+:0101C8002B0B
+:0101C9002A0B
+:0101CA00290B
+:0101CB00290A
+:0101CC00280A
+:0101CD00270A
+:0101CE00260A
+:0101CF002609
+:0101D0002509
+:0101D1002409
+:0101D2002309
+:0101D3002308
+:0101D4002208
+:0101D5002108
+:0101D6002008
+:0101D7002007
+:0101D8001F07
+:0101D9001E07
+:0101DA001D07
+:0101DB001D06
+:0101DC001C06
+:0101DD001B06
+:0101DE001A06
+:0101DF001A05
+:0101E0001905
+:0101E1001805
+:0101E2001705
+:0101E3001605
+:0101E4001604
+:0101E5001504
+:0101E6001404
+:0101E7001304
+:0101E8001303
+:0101E9001203
+:0101EA001103
+:0101EB001003
+:0101EC001002
+:0101ED000F02
+:0101EE000E02
+:0101EF000D02
+:0101F0000C02
+:0101F1000C01
+:0101F2000B01
+:0101F3000A01
+:0101F4000901
+:0101F5000900
+:0101F6000800
+:0101F7000700
+:0101F8000600
+:0101F9000500
+:0101FA0005FF
+:0101FB0004FF
+:0101FC0003FF
+:0101FD0002FF
+:0101FE0002FE
+:0101FF0001FE
+:0102000000FD
+:01020100FFFD
+:01020200FEFD
+:01020300FEFC
+:01020400FDFC
+:01020500FCFC
+:01020600FBFC
+:01020700FBFB
+:01020800FAFB
+:01020900F9FB
+:01020A00F8FB
+:01020B00F7FB
+:01020C00F7FA
+:01020D00F6FA
+:01020E00F5FA
+:01020F00F4FA
+:01021000F4F9
+:01021100F3F9
+:01021200F2F9
+:01021300F1F9
+:01021400F0F9
+:01021500F0F8
+:01021600EFF8
+:01021700EEF8
+:01021800EDF8
+:01021900EDF7
+:01021A00ECF7
+:01021B00EBF7
+:01021C00EAF7
+:01021D00EAF6
+:01021E00E9F6
+:01021F00E8F6
+:01022000E7F6
+:01022100E6F6
+:01022200E6F5
+:01022300E5F5
+:01022400E4F5
+:01022500E3F5
+:01022600E3F4
+:01022700E2F4
+:01022800E1F4
+:01022900E0F4
+:01022A00E0F3
+:01022B00DFF3
+:01022C00DEF3
+:01022D00DDF3
+:01022E00DDF2
+:01022F00DCF2
+:01023000DBF2
+:01023100DAF2
+:01023200DAF1
+:01023300D9F1
+:01023400D8F1
+:01023500D7F1
+:01023600D7F0
+:01023700D6F0
+:01023800D5F0
+:01023900D4F0
+:01023A00D4EF
+:01023B00D3EF
+:01023C00D2EF
+:01023D00D2EE
+:01023E00D1EE
+:01023F00D0EE
+:01024000CFEE
+:01024100CFED
+:01024200CEED
+:01024300CDED
+:01024400CDEC
+:01024500CCEC
+:01024600CBEC
+:01024700CAEC
+:01024800CAEB
+:01024900C9EB
+:01024A00C8EB
+:01024B00C8EA
+:01024C00C7EA
+:01024D00C6EA
+:01024E00C6E9
+:01024F00C5E9
+:01025000C4E9
+:01025100C3E9
+:01025200C3E8
+:01025300C2E8
+:01025400C1E8
+:01025500C1E7
+:01025600C0E7
+:01025700BFE7
+:01025800BFE6
+:01025900BEE6
+:01025A00BDE6
+:01025B00BDE5
+:01025C00BCE5
+:01025D00BBE5
+:01025E00BBE4
+:01025F00BAE4
+:01026000B9E4
+:01026100B9E3
+:01026200B8E3
+:01026300B8E2
+:01026400B7E2
+:01026500B6E2
+:01026600B6E1
+:01026700B5E1
+:01026800B4E1
+:01026900B4E0
+:01026A00B3E0
+:01026B00B2E0
+:01026C00B2DF
+:01026D00B1DF
+:01026E00B1DE
+:01026F00B0DE
+:01027000AFDE
+:01027100AFDD
+:01027200AEDD
+:01027300AEDC
+:01027400ADDC
+:01027500ACDC
+:01027600ACDB
+:01027700ABDB
+:01027800ABDA
+:01027900AADA
+:01027A00AAD9
+:01027B00A9D9
+:01027C00A8D9
+:01027D00A8D8
+:01027E00A7D8
+:01027F00A7D7
+:01028000A6D7
+:01028100A6D6
+:01028200A5D6
+:01028300A5D5
+:01028400A4D5
+:01028500A3D5
+:01028600A3D4
+:01028700A2D4
+:01028800A2D3
+:01028900A1D3
+:01028A00A1D2
+:01028B00A0D2
+:01028C00A0D1
+:01028D009FD1
+:01028E009FD0
+:01028F009ED0
+:010290009ECF
+:010291009DCF
+:010292009DCE
+:010293009CCE
+:010294009CCD
+:010295009BCD
+:010296009BCC
+:010297009ACC
+:010298009ACB
+:010299009ACA
+:01029A0099CA
+:01029B0099C9
+:01029C0098C9
+:01029D0098C8
+:01029E0097C8
+:01029F0097C7
+:0102A00096C7
+:0102A10096C6
+:0102A20096C5
+:0102A30095C5
+:0102A40095C4
+:0102A50094C4
+:0102A60094C3
+:0102A70093C3
+:0102A80093C2
+:0102A90093C1
+:0102AA0092C1
+:0102AB0092C0
+:0102AC0091C0
+:0102AD0091BF
+:0102AE0091BE
+:0102AF0090BE
+:0102B00090BD
+:0102B10090BC
+:0102B2008FBC
+:0102B3008FBB
+:0102B4008FBA
+:0102B5008EBA
+:0102B6008EB9
+:0102B7008EB8
+:0102B8008DB8
+:0102B9008DB7
+:0102BA008DB6
+:0102BB008CB6
+:0102BC008CB5
+:0102BD008CB4
+:0102BE008BB4
+:0102BF008BB3
+:0102C0008BB2
+:0102C1008AB2
+:0102C2008AB1
+:0102C3008AB0
+:0102C4008AAF
+:0102C50089AF
+:0102C60089AE
+:0102C70089AD
+:0102C80088AD
+:0102C90088AC
+:0102CA0088AB
+:0102CB0088AA
+:0102CC0087AA
+:0102CD0087A9
+:0102CE0087A8
+:0102CF0087A7
+:0102D00086A7
+:0102D10086A6
+:0102D20086A5
+:0102D30086A4
+:0102D40086A3
+:0102D50085A3
+:0102D60085A2
+:0102D70085A1
+:0102D80085A0
+:0102D900859F
+:0102DA00849F
+:0102DB00849E
+:0102DC00849D
+:0102DD00849C
+:0102DE00849B
+:0102DF00849A
+:0102E000839A
+:0102E1008399
+:0102E2008398
+:0102E3008397
+:0102E4008396
+:0102E5008395
+:0102E6008394
+:0102E7008294
+:0102E8008293
+:0102E9008292
+:0102EA008291
+:0102EB008290
+:0102EC00828F
+:0102ED00828E
+:0102EE00828D
+:0102EF00828C
+:0102F000828B
+:0102F100828A
+:0102F200818A
+:0102F3008189
+:0102F4008188
+:0102F5008187
+:0102F6008186
+:0102F7008185
+:0102F8008184
+:0102F9008183
+:0102FA008182
+:0102FB008181
+:0102FC008180
+:0102FD00817F
+:0102FE00817E
+:0102FF00817D
+:01030000817B
+:01030100817A
+:010302008179
+:010303008178
+:010304008177
+:010305008176
+:010306008175
+:010307008174
+:010308008173
+:010309008172
+:01030A008171
+:01030B008170
+:01030C00816F
+:01030D00816E
+:01030E00816D
+:01030F00826B
+:01031000826A
+:010311008269
+:010312008268
+:010313008267
+:010314008266
+:010315008265
+:010316008264
+:010317008263
+:010318008262
+:010319008261
+:01031A00835F
+:01031B00835E
+:01031C00835D
+:01031D00835C
+:01031E00835B
+:01031F00835A
+:010320008359
+:010321008457
+:010322008456
+:010323008455
+:010324008454
+:010325008453
+:010326008452
+:010327008550
+:01032800854F
+:01032900854E
+:01032A00854D
+:01032B00854C
+:01032C00864A
+:01032D008649
+:01032E008648
+:01032F008647
+:010330008646
+:010331008744
+:010332008743
+:010333008742
+:010334008741
+:01033500883F
+:01033600883E
+:01033700883D
+:01033800883C
+:01033900893A
+:01033A008939
+:01033B008938
+:01033C008A36
+:01033D008A35
+:01033E008A34
+:01033F008A33
+:010340008B31
+:010341008B30
+:010342008B2F
+:010343008C2D
+:010344008C2C
+:010345008C2B
+:010346008D29
+:010347008D28
+:010348008D27
+:010349008E25
+:01034A008E24
+:01034B008E23
+:01034C008F21
+:01034D008F20
+:01034E008F1F
+:01034F00901D
+:01035000901C
+:01035100901B
+:010352009119
+:010353009118
+:010354009117
+:010355009215
+:010356009214
+:010357009312
+:010358009311
+:010359009310
+:01035A00940E
+:01035B00940D
+:01035C00950B
+:01035D00950A
+:01035E009608
+:01035F009607
+:010360009606
+:010361009704
+:010362009703
+:010363009801
+:010364009800
+:0103650099FE
+:0103660099FD
+:010367009AFB
+:010368009AFA
+:010369009AF9
+:01036A009BF7
+:01036B009BF6
+:01036C009CF4
+:01036D009CF3
+:01036E009DF1
+:01036F009DF0
+:010370009EEE
+:010371009EED
+:010372009FEB
+:010373009FEA
+:01037400A0E8
+:01037500A0E7
+:01037600A1E5
+:01037700A1E4
+:01037800A2E2
+:01037900A2E1
+:01037A00A3DF
+:01037B00A3DE
+:01037C00A4DC
+:01037D00A5DA
+:01037E00A5D9
+:01037F00A6D7
+:01038000A6D6
+:01038100A7D4
+:01038200A7D3
+:01038300A8D1
+:01038400A8D0
+:01038500A9CE
+:01038600AACC
+:01038700AACB
+:01038800ABC9
+:01038900ABC8
+:01038A00ACC6
+:01038B00ACC5
+:01038C00ADC3
+:01038D00AEC1
+:01038E00AEC0
+:01038F00AFBE
+:01039000AFBD
+:01039100B0BB
+:01039200B1B9
+:01039300B1B8
+:01039400B2B6
+:01039500B2B5
+:01039600B3B3
+:01039700B4B1
+:01039800B4B0
+:01039900B5AE
+:01039A00B6AC
+:01039B00B6AB
+:01039C00B7A9
+:01039D00B8A7
+:01039E00B8A6
+:01039F00B9A4
+:0103A000B9A3
+:0103A100BAA1
+:0103A200BB9F
+:0103A300BB9E
+:0103A400BC9C
+:0103A500BD9A
+:0103A600BD99
+:0103A700BE97
+:0103A800BF95
+:0103A900BF94
+:0103AA00C092
+:0103AB00C190
+:0103AC00C18F
+:0103AD00C28D
+:0103AE00C38B
+:0103AF00C38A
+:0103B000C488
+:0103B100C586
+:0103B200C684
+:0103B300C683
+:0103B400C781
+:0103B500C87F
+:0103B600C87E
+:0103B700C97C
+:0103B800CA7A
+:0103B900CA79
+:0103BA00CB77
+:0103BB00CC75
+:0103BC00CD73
+:0103BD00CD72
+:0103BE00CE70
+:0103BF00CF6E
+:0103C000CF6D
+:0103C100D06B
+:0103C200D169
+:0103C300D267
+:0103C400D266
+:0103C500D364
+:0103C600D462
+:0103C700D461
+:0103C800D55F
+:0103C900D65D
+:0103CA00D75B
+:0103CB00D75A
+:0103CC00D858
+:0103CD00D956
+:0103CE00DA54
+:0103CF00DA53
+:0103D000DB51
+:0103D100DC4F
+:0103D200DD4D
+:0103D300DD4C
+:0103D400DE4A
+:0103D500DF48
+:0103D600E046
+:0103D700E045
+:0103D800E143
+:0103D900E241
+:0103DA00E33F
+:0103DB00E33E
+:0103DC00E43C
+:0103DD00E53A
+:0103DE00E638
+:0103DF00E637
+:0103E000E735
+:0103E100E833
+:0103E200E931
+:0103E300EA2F
+:0103E400EA2E
+:0103E500EB2C
+:0103E600EC2A
+:0103E700ED28
+:0103E800ED27
+:0103E900EE25
+:0103EA00EF23
+:0103EB00F021
+:0103EC00F020
+:0103ED00F11E
+:0103EE00F21C
+:0103EF00F31A
+:0103F000F418
+:0103F100F417
+:0103F200F515
+:0103F300F613
+:0103F400F711
+:0103F500F710
+:0103F600F80E
+:0103F700F90C
+:0103F800FA0A
+:0103F900FB08
+:0103FA00FB07
+:0103FB00FC05
+:0103FC00FD03
+:0103FD00FE01
+:0103FE00FE00
+:0103FF00FFFE
+:00000001FF
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/data/diag_sin_2048x18.hex b/applications/lofar2/designs/lofar2_unb2b_adc/src/data/diag_sin_2048x18.hex
new file mode 100644
index 0000000000000000000000000000000000000000..709e6ec6b706ffbdb062c62907c7a76ce04b7431
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/data/diag_sin_2048x18.hex
@@ -0,0 +1,2049 @@
+:03000000000000fd
+:0300010000019269
+:03000200000324d4
+:030003000004b640
+:03000400000648ab
+:030005000007db16
+:0300060000096d81
+:03000700000affed
+:03000800000c9158
+:03000900000e23c3
+:03000a00000fb52f
+:03000b000011469b
+:03000c000012d807
+:03000d0000146a72
+:03000e000015fcde
+:03000f0000178e49
+:0300100000191fb5
+:03001100001ab121
+:03001200001c428d
+:03001300001dd4f9
+:03001400001f6565
+:030015000020f7d1
+:030016000022883d
+:03001700002419a9
+:030018000025aa16
+:0300190000273b82
+:03001a000028ccef
+:03001b00002a5d5b
+:03001c00002beec8
+:03001d00002d7e35
+:03001e00002f0fa1
+:03001f0000309f0f
+:0300200000322f7c
+:030021000033bfea
+:0300220000354f57
+:030023000036dfc5
+:0300240000386f32
+:030025000039ffa0
+:03002600003b8e0e
+:03002700003d1d7c
+:03002800003eaceb
+:0300290000403c58
+:03002a000041cac8
+:03002b0000435936
+:03002c000044e8a5
+:03002d0000467614
+:03002e0000480483
+:03002f00004992f3
+:03003000004b2062
+:03003100004caed2
+:03003200004e3b42
+:03003300004fc9b2
+:0300340000515622
+:030035000052e393
+:0300360000546f04
+:030037000055fc75
+:03003800005788e6
+:0300390000591457
+:03003a00005aa0c9
+:03003b00005c2c3a
+:03003c00005db7ad
+:03003d00005f421f
+:03003e000060cd92
+:03003f0000625804
+:030040000063e377
+:0300410000656dea
+:030042000066f75e
+:03004300006881d1
+:03004400006a0a45
+:03004500006b94b9
+:03004600006d1d2d
+:03004700006ea5a3
+:0300480000702e17
+:030049000071b68d
+:03004a0000733e02
+:03004b000074c678
+:03004c0000764dee
+:03004d000077d465
+:03004e0000795bdb
+:03004f00007ae153
+:03005000007c68c9
+:03005100007dee41
+:03005200007f73b9
+:030053000080f832
+:0300540000827daa
+:0300550000840222
+:030056000085879b
+:0300570000870b14
+:0300580000888e8f
+:03005900008a1208
+:03005a00008b9583
+:03005b00008d17fe
+:03005c00008e9a79
+:03005d0000901cf4
+:03005e0000919e70
+:03005f0000931fec
+:030060000094a069
+:03006100009621e5
+:030062000097a163
+:03006300009921e0
+:03006400009aa05f
+:03006500009c1fdd
+:03006600009d9e5c
+:03006700009f1dda
+:0300680000a09b5a
+:0300690000a218da
+:03006a0000a3955b
+:03006b0000a512db
+:03006c0000a68f5c
+:03006d0000a80bdd
+:03006e0000a98660
+:03006f0000ab02e1
+:0300700000ac7c65
+:0300710000adf7e8
+:0300720000af716b
+:0300730000b0eaf0
+:0300740000b26473
+:0300750000b3dcf9
+:0300760000b5557d
+:0300770000b6cc04
+:0300780000b84489
+:0300790000b9bb10
+:03007a0000bb3197
+:03007b0000bca71f
+:03007c0000be1da6
+:03007d0000bf922f
+:03007e0000c107b7
+:03007f0000c27b41
+:0300800000c3efcb
+:0300810000c56255
+:0300820000c6d5e0
+:0300830000c8476b
+:0300840000c9b9f7
+:0300850000cb2a83
+:0300860000cc9b10
+:0300870000ce0c9c
+:0300880000cf7b2b
+:0300890000d0ebb9
+:03008a0000d25a47
+:03008b0000d3c8d7
+:03008c0000d53666
+:03008d0000d6a3f7
+:03008e0000d81087
+:03008f0000d97c19
+:0300900000dae8ab
+:0300910000dc533d
+:0300920000ddbed0
+:0300930000df2863
+:0300940000e092f7
+:0300950000e1fb8c
+:0300960000e36420
+:0300970000e4ccb6
+:0300980000e6334c
+:0300990000e79ae3
+:03009a0000e9007a
+:03009b0000ea6612
+:03009c0000ebcbab
+:03009d0000ed3043
+:03009e0000ee94dd
+:03009f0000eff877
+:0300a00000f15a12
+:0300a10000f2bdad
+:0300a20000f41f48
+:0300a30000f580e5
+:0300a40000f6e083
+:0300a50000f84020
+:0300a60000f9a0be
+:0300a70000fafe5e
+:0300a80000fc5dfc
+:0300a90000fdba9d
+:0300aa0000ff173d
+:0300ab00010074dd
+:0300ac000101cf80
+:0300ad0001032a22
+:0300ae00010485c5
+:0300af000105df69
+:0300b0000107380d
+:0300b100010891b2
+:0300b2000109e958
+:0300b300010b40fe
+:0300b400010c96a6
+:0300b500010ded4d
+:0300b600010f42f5
+:0300b7000110979e
+:0300b8000111eb48
+:0300b90001133ef2
+:0300ba000114919d
+:0300bb000115e349
+:0300bc00011734f5
+:0300bd00011885a2
+:0300be000119d550
+:0300bf00011b24fe
+:0300c000011c73ad
+:0300c100011dc15d
+:0300c200011f0e0d
+:0300c30001205bbe
+:0300c4000121a770
+:0300c5000122f223
+:0300c60001243dd5
+:0300c70001258789
+:0300c8000126d03e
+:0300c900012818f3
+:0300ca00012960a9
+:0300cb00012aa760
+:0300cc00012bed18
+:0300cd00012d33cf
+:0300ce00012e7789
+:0300cf00012fbc42
+:0300d0000130fffd
+:0300d100013242b7
+:0300d20001338374
+:0300d3000134c530
+:0300d400013605ed
+:0300d500013745ab
+:0300d6000138836b
+:0300d7000139c22a
+:0300d800013affeb
+:0300d900013c3cab
+:0300da00013d786d
+:0300db00013eb330
+:0300dc00013fedf4
+:0300dd00014127b7
+:0300de0001425f7d
+:0300df0001439743
+:0300e0000144cf09
+:0300e100014605d0
+:0300e20001473b98
+:0300e30001487061
+:0300e4000149a42b
+:0300e500014ad7f6
+:0300e600014c09c1
+:0300e700014d3b8d
+:0300e800014e6c5a
+:0300e900014f9c28
+:0300ea000150cbf7
+:0300eb000151fac6
+:0300ec0001532796
+:0300ed0001545467
+:0300ee0001558039
+:0300ef000156ac0b
+:0300f0000157d6df
+:0300f1000158ffb4
+:0300f200015a2888
+:0300f300015b505e
+:0300f400015c7735
+:0300f500015d9d0d
+:0300f600015ec3e5
+:0300f700015fe7bf
+:0300f80001610b98
+:0300f90001622e73
+:0300fa000163504f
+:0300fb000164712c
+:0300fc000165910a
+:0300fd000166b0e9
+:0300fe000167cfc8
+:0300ff000168eca9
+:03010000016a0988
+:03010100016b256a
+:03010200016c404d
+:03010300016d5a31
+:03010400016e7415
+:03010500016f8cfb
+:030106000170a3e2
+:030107000171bac9
+:030108000172d0b1
+:030109000173e59a
+:03010a000174f984
+:03010b0001760c6e
+:03010c0001771e5a
+:03010d0001782f47
+:03010e0001793f35
+:03010f00017a4f23
+:03011000017b5d13
+:03011100017c6b03
+:03011200017d77f5
+:03011300017e83e7
+:03011400017f8eda
+:03011500018098ce
+:030116000181a1c3
+:030117000182a9b9
+:030118000183b0b0
+:030119000184b6a8
+:03011a000185bca0
+:03011b000186c09a
+:03011c000187c395
+:03011d000188c690
+:03011e000189c78d
+:03011f00018ac88a
+:03012000018bc789
+:03012100018cc688
+:03012200018dc488
+:03012300018ec08a
+:03012400018fbc8c
+:030125000190b78f
+:030126000191b193
+:030127000192a999
+:030128000193a19f
+:03012900019498a6
+:03012a0001958eae
+:03012b00019683b7
+:03012c00019777c1
+:03012d0001986acc
+:03012e0001995cd8
+:03012f00019a4de5
+:03013000019b3df3
+:03013100019c2c02
+:03013200019d1a12
+:03013300019e0723
+:03013400019ef336
+:03013500019fde49
+:0301360001a0c95c
+:0301370001a1b271
+:0301380001a29a87
+:0301390001a3819e
+:03013a0001a467b6
+:03013b0001a54ccf
+:03013c0001a630e9
+:03013d0001a71304
+:03013e0001a7f521
+:03013f0001a8d63e
+:0301400001a9b65c
+:0301410001aa947c
+:0301420001ab729c
+:0301430001ac4fbd
+:0301440001ad2bdf
+:0301450001ae0602
+:0301460001aedf28
+:0301470001afb84d
+:0301480001b09073
+:0301490001b1669b
+:03014a0001b23cc3
+:03014b0001b311ec
+:03014c0001b3e418
+:03014d0001b4b644
+:03014e0001b58870
+:03014f0001b6589e
+:0301500001b727cd
+:0301510001b7f6fd
+:0301520001b8c32e
+:0301530001b98f60
+:0301540001ba5a93
+:0301550001bb24c7
+:0301560001bbedfd
+:0301570001bcb434
+:0301580001bd7b6b
+:0301590001be41a3
+:03015a0001bf05dd
+:03015b0001bfc918
+:03015c0001c08b54
+:03015d0001c14d90
+:03015e0001c20dce
+:03015f0001c2cc0e
+:0301600001c38a4e
+:0301610001c4478f
+:0301620001c503d1
+:0301630001c5be15
+:0301640001c67859
+:0301650001c7309f
+:0301660001c7e8e6
+:0301670001c89e2e
+:0301680001c95476
+:0301690001ca08c0
+:03016a0001cabb0c
+:03016b0001cb6d58
+:03016c0001cc1ea5
+:03016d0001cccef4
+:03016e0001cd7d43
+:03016f0001ce2a94
+:0301700001ced7e6
+:0301710001cf8239
+:0301720001d02c8d
+:0301730001d0d6e2
+:0301740001d17e38
+:0301750001d22490
+:0301760001d2cae9
+:0301770001d36f42
+:0301780001d4129d
+:0301790001d4b5f9
+:03017a0001d55656
+:03017b0001d5f6b5
+:03017c0001d69514
+:03017d0001d73374
+:03017e0001d7d0d6
+:03017f0001d86b39
+:0301800001d9069c
+:0301810001d99f02
+:0301820001da3768
+:0301830001daced0
+:0301840001db6438
+:0301850001dbf9a2
+:0301860001dc8d0c
+:0301870001dd1f78
+:0301880001ddb0e6
+:0301890001de4054
+:03018a0001decfc4
+:03018b0001df5d34
+:03018c0001dfeaa6
+:03018d0001e07519
+:03018e0001e1008c
+:03018f0001e18902
+:0301900001e21178
+:0301910001e298f0
+:0301920001e31e68
+:0301930001e3a2e3
+:0301940001e4265d
+:0301950001e4a8da
+:0301960001e52957
+:0301970001e5a9d6
+:0301980001e62855
+:0301990001e6a5d7
+:03019a0001e72258
+:03019b0001e79ddc
+:03019c0001e81760
+:03019d0001e890e6
+:03019e0001e9076d
+:03019f0001e97ef5
+:0301a00001e9f37f
+:0301a10001ea6709
+:0301a20001eada95
+:0301a30001eb4c21
+:0301a40001ebbdaf
+:0301a50001ec2c3e
+:0301a60001ec9acf
+:0301a70001ed0760
+:0301a80001ed73f3
+:0301a90001edde87
+:0301aa0001ee471c
+:0301ab0001eeafb3
+:0301ac0001ef1749
+:0301ad0001ef7ce3
+:0301ae0001efe17d
+:0301af0001f04517
+:0301b00001f0a7b4
+:0301b10001f10851
+:0301b20001f168f0
+:0301b30001f1c790
+:0301b40001f22431
+:0301b50001f281d3
+:0301b60001f2dc77
+:0301b70001f3361b
+:0301b80001f38ec2
+:0301b90001f3e669
+:0301ba0001f43c11
+:0301bb0001f491bb
+:0301bc0001f4e566
+:0301bd0001f53811
+:0301be0001f589bf
+:0301bf0001f5d96e
+:0301c00001f6291c
+:0301c10001f676ce
+:0301c20001f6c380
+:0301c30001f70e33
+:0301c40001f759e7
+:0301c50001f7a29d
+:0301c60001f7e955
+:0301c70001f8300c
+:0301c80001f875c6
+:0301c90001f8b981
+:0301ca0001f8fc3d
+:0301cb0001f93ef9
+:0301cc0001f97fb7
+:0301cd0001f9be77
+:0301ce0001f9fc38
+:0301cf0001fa39f9
+:0301d00001fa74bd
+:0301d10001faaf81
+:0301d20001fae847
+:0301d30001fb200d
+:0301d40001fb57d5
+:0301d50001fb8c9f
+:0301d60001fbc06a
+:0301d70001fbf336
+:0301d80001fc2502
+:0301d90001fc56d0
+:0301da0001fc85a0
+:0301db0001fcb371
+:0301dc0001fce043
+:0301dd0001fd0c15
+:0301de0001fd37e9
+:0301df0001fd60bf
+:0301e00001fd8896
+:0301e10001fdaf6e
+:0301e20001fdd448
+:0301e30001fdf922
+:0301e40001fe1cfd
+:0301e50001fe3eda
+:0301e60001fe5eb9
+:0301e70001fe7e98
+:0301e80001fe9c79
+:0301e90001feb95b
+:0301ea0001fed53e
+:0301eb0001feef23
+:0301ec0001ff0808
+:0301ed0001ff20ef
+:0301ee0001ff37d7
+:0301ef0001ff4dc0
+:0301f00001ff61ab
+:0301f10001ff7497
+:0301f20001ff8684
+:0301f30001ff9772
+:0301f40001ffa662
+:0301f50001ffb453
+:0301f60001ffc145
+:0301f70001ffcd38
+:0301f80001ffd82c
+:0301f90001ffe122
+:0301fa0001ffe919
+:0301fb0001fff011
+:0301fc0001fff50b
+:0301fd0001fff906
+:0301fe0001fffd01
+:0301ff0001fffeff
+:0302000001fffffc
+:0302010001fffefc
+:0302020001fffdfc
+:0302030001fff9ff
+:0302040001fff502
+:0302050001fff006
+:0302060001ffe90c
+:0302070001ffe113
+:0302080001ffd81b
+:0302090001ffcd25
+:03020a0001ffc130
+:03020b0001ffb43c
+:03020c0001ffa649
+:03020d0001ff9757
+:03020e0001ff8667
+:03020f0001ff7478
+:0302100001ff618a
+:0302110001ff4d9d
+:0302120001ff37b2
+:0302130001ff20c8
+:0302140001ff08df
+:0302150001feeff8
+:0302160001fed511
+:0302170001feb92c
+:0302180001fe9c48
+:0302190001fe7e65
+:03021a0001fe5e84
+:03021b0001fe3ea3
+:03021c0001fe1cc4
+:03021d0001fdf9e7
+:03021e0001fdd40b
+:03021f0001fdaf2f
+:0302200001fd8855
+:0302210001fd607c
+:0302220001fd37a4
+:0302230001fd0cce
+:0302240001fce0fa
+:0302250001fcb326
+:0302260001fc8553
+:0302270001fc5681
+:0302280001fc25b1
+:0302290001fbf3e3
+:03022a0001fbc015
+:03022b0001fb8c48
+:03022c0001fb577c
+:03022d0001fb20b2
+:03022e0001fae8ea
+:03022f0001faaf22
+:0302300001fa745c
+:0302310001fa3996
+:0302320001f9fcd3
+:0302330001f9be10
+:0302340001f97f4e
+:0302350001f93e8e
+:0302360001f8fcd0
+:0302370001f8b912
+:0302380001f87555
+:0302390001f83099
+:03023a0001f7e9e0
+:03023b0001f7a226
+:03023c0001f7596e
+:03023d0001f70eb8
+:03023e0001f6c303
+:03023f0001f6764f
+:0302400001f6299b
+:0302410001f5d9eb
+:0302420001f5893a
+:0302430001f5388a
+:0302440001f4e5dd
+:0302450001f49130
+:0302460001f43c84
+:0302470001f3e6da
+:0302480001f38e31
+:0302490001f33688
+:03024a0001f2dce2
+:03024b0001f2813c
+:03024c0001f22498
+:03024d0001f1c7f5
+:03024e0001f16853
+:03024f0001f108b2
+:0302500001f0a713
+:0302510001f04574
+:0302520001efe1d8
+:0302530001ef7c3c
+:0302540001ef17a0
+:0302550001eeaf08
+:0302560001ee476f
+:0302570001edded8
+:0302580001ed7342
+:0302590001ed07ad
+:03025a0001ec9a1a
+:03025b0001ec2c87
+:03025c0001ebbdf6
+:03025d0001eb4c66
+:03025e0001eadad8
+:03025f0001ea674a
+:0302600001e9f3be
+:0302610001e97e32
+:0302620001e907a8
+:0302630001e8901f
+:0302640001e81797
+:0302650001e79d11
+:0302660001e7228b
+:0302670001e6a508
+:0302680001e62884
+:0302690001e5a903
+:03026a0001e52982
+:03026b0001e4a803
+:03026c0001e42684
+:03026d0001e3a208
+:03026e0001e31e8b
+:03026f0001e29811
+:0302700001e21197
+:0302710001e1891f
+:0302720001e100a7
+:0302730001e07532
+:0302740001dfeabd
+:0302750001df5d49
+:0302760001decfd7
+:0302770001de4065
+:0302780001ddb0f5
+:0302790001dd1f85
+:03027a0001dc8d17
+:03027b0001dbf9ab
+:03027c0001db643f
+:03027d0001daced5
+:03027e0001da376b
+:03027f0001d99f03
+:0302800001d9069b
+:0302810001d86b36
+:0302820001d7d0d1
+:0302830001d7336d
+:0302840001d6950b
+:0302850001d5f6aa
+:0302860001d55649
+:0302870001d4b5ea
+:0302880001d4128c
+:0302890001d36f2f
+:03028a0001d2cad4
+:03028b0001d22479
+:03028c0001d17e1f
+:03028d0001d0d6c7
+:03028e0001d02c70
+:03028f0001cf821a
+:0302900001ced7c5
+:0302910001ce2a71
+:0302920001cd7d1e
+:0302930001cccecd
+:0302940001cc1e7c
+:0302950001cb6d2d
+:0302960001cabbdf
+:0302970001ca0891
+:0302980001c95445
+:0302990001c89efb
+:03029a0001c7e8b1
+:03029b0001c73068
+:03029c0001c67820
+:03029d0001c5beda
+:03029e0001c50394
+:03029f0001c44750
+:0302a00001c38a0d
+:0302a10001c2cccb
+:0302a20001c20d89
+:0302a30001c14d49
+:0302a40001c08b0b
+:0302a50001bfc9cd
+:0302a60001bf0590
+:0302a70001be4154
+:0302a80001bd7b1a
+:0302a90001bcb4e1
+:0302aa0001bbeda8
+:0302ab0001bb2470
+:0302ac0001ba5a3a
+:0302ad0001b98f05
+:0302ae0001b8c3d1
+:0302af0001b7f69e
+:0302b00001b7276c
+:0302b10001b6583b
+:0302b20001b5880b
+:0302b30001b4b6dd
+:0302b40001b3e4af
+:0302b50001b31181
+:0302b60001b23c56
+:0302b70001b1662c
+:0302b80001b09002
+:0302b90001afb8da
+:0302ba0001aedfb3
+:0302bb0001ae068b
+:0302bc0001ad2b66
+:0302bd0001ac4f42
+:0302be0001ab721f
+:0302bf0001aa94fd
+:0302c00001a9b6db
+:0302c10001a8d6bb
+:0302c20001a7f59c
+:0302c30001a7137d
+:0302c40001a63060
+:0302c50001a54c44
+:0302c60001a46729
+:0302c70001a3810f
+:0302c80001a29af6
+:0302c90001a1b2de
+:0302ca0001a0c9c7
+:0302cb00019fdeb2
+:0302cc00019ef39d
+:0302cd00019e0788
+:0302ce00019d1a75
+:0302cf00019c2c63
+:0302d000019b3d52
+:0302d100019a4d42
+:0302d20001995c33
+:0302d30001986a25
+:0302d40001977718
+:0302d5000196830c
+:0302d60001958e01
+:0302d700019498f7
+:0302d8000193a1ee
+:0302d9000192a9e6
+:0302da000191b1de
+:0302db000190b7d8
+:0302dc00018fbcd3
+:0302dd00018ec0cf
+:0302de00018dc4cb
+:0302df00018cc6c9
+:0302e000018bc7c8
+:0302e100018ac8c7
+:0302e2000189c7c8
+:0302e3000188c6c9
+:0302e4000187c3cc
+:0302e5000186c0cf
+:0302e6000185bcd3
+:0302e7000184b6d9
+:0302e8000183b0df
+:0302e9000182a9e6
+:0302ea000181a1ee
+:0302eb00018098f7
+:0302ec00017f8e01
+:0302ed00017e830c
+:0302ee00017d7718
+:0302ef00017c6b24
+:0302f000017b5d32
+:0302f100017a4f40
+:0302f20001793f50
+:0302f30001782f60
+:0302f40001771e71
+:0302f50001760c83
+:0302f6000174f997
+:0302f7000173e5ab
+:0302f8000172d0c0
+:0302f9000171bad6
+:0302fa000170a3ed
+:0302fb00016f8c04
+:0302fc00016e741c
+:0302fd00016d5a36
+:0302fe00016c4050
+:0302ff00016b256b
+:03030000016a0986
+:030301000168eca4
+:030302000167cfc1
+:030303000166b0e0
+:03030400016591ff
+:030305000164711f
+:0303060001635040
+:0303070001622e62
+:0303080001610b85
+:03030900015fe7aa
+:03030a00015ec3ce
+:03030b00015d9df4
+:03030c00015c771a
+:03030d00015b5041
+:03030e00015a2869
+:03030f000158ff93
+:030310000157d6bc
+:030311000156ace6
+:0303120001558012
+:030313000154543e
+:030314000153276b
+:030315000151fa99
+:030316000150cbc8
+:03031700014f9cf7
+:03031800014e6c27
+:03031900014d3b58
+:03031a00014c098a
+:03031b00014ad7bd
+:03031c000149a4f0
+:03031d0001487024
+:03031e0001473b59
+:03031f000146058f
+:030320000144cfc6
+:03032100014397fe
+:0303220001425f36
+:030323000141276e
+:03032400013feda9
+:03032500013eb3e3
+:03032600013d781e
+:03032700013c3c5a
+:03032800013aff98
+:030329000139c2d5
+:03032a0001388314
+:03032b0001374552
+:03032c0001360592
+:03032d000134c5d3
+:03032e0001338315
+:03032f0001324256
+:030330000130ff9a
+:03033100012fbcdd
+:03033200012e7722
+:03033300012d3366
+:03033400012bedad
+:03033500012aa7f3
+:030336000129603a
+:0303370001281882
+:030338000126d0cb
+:0303390001258714
+:03033a0001243d5e
+:03033b000122f2aa
+:03033c000121a7f5
+:03033d0001205b41
+:03033e00011f0e8e
+:03033f00011dc1dc
+:03034000011c732a
+:03034100011b2479
+:030342000119d5c9
+:0303430001188519
+:030344000117346a
+:030345000115e3bc
+:030346000114910e
+:0303470001133e61
+:030348000111ebb5
+:0303490001109709
+:03034a00010f425e
+:03034b00010dedb4
+:03034c00010c960b
+:03034d00010b4061
+:03034e000109e9b9
+:03034f0001089111
+:030350000107386a
+:030351000105dfc4
+:030352000104851e
+:0303530001032a79
+:030354000101cfd5
+:0303550001007430
+:0303560000ff178e
+:0303570000fdbaec
+:0303580000fc5d49
+:0303590000fafea9
+:03035a0000f9a007
+:03035b0000f84067
+:03035c0000f6e0c8
+:03035d0000f58028
+:03035e0000f41f89
+:03035f0000f2bdec
+:0303600000f15a4f
+:0303610000eff8b2
+:0303620000ee9416
+:0303630000ed307a
+:0303640000ebcbe0
+:0303650000ea6645
+:0303660000e900ab
+:0303670000e79a12
+:0303680000e63379
+:0303690000e4cce1
+:03036a0000e36449
+:03036b0000e1fbb3
+:03036c0000e0921c
+:03036d0000df2886
+:03036e0000ddbef1
+:03036f0000dc535c
+:0303700000dae8c8
+:0303710000d97c34
+:0303720000d810a0
+:0303730000d6a30e
+:0303740000d5367b
+:0303750000d3c8ea
+:0303760000d25a58
+:0303770000d0ebc8
+:0303780000cf7b38
+:0303790000ce0ca7
+:03037a0000cc9b19
+:03037b0000cb2a8a
+:03037c0000c9b9fc
+:03037d0000c8476e
+:03037e0000c6d5e1
+:03037f0000c56254
+:0303800000c3efc8
+:0303810000c27b3c
+:0303820000c107b0
+:0303830000bf9226
+:0303840000be1d9b
+:0303850000bca712
+:0303860000bb3188
+:0303870000b9bbff
+:0303880000b84476
+:0303890000b6ccef
+:03038a0000b55566
+:03038b0000b3dce0
+:03038c0000b26458
+:03038d0000b0ead3
+:03038e0000af714c
+:03038f0000adf7c7
+:0303900000ac7c42
+:0303910000ab02bc
+:0303920000a98639
+:0303930000a80bb4
+:0303940000a68f31
+:0303950000a512ae
+:0303960000a3952c
+:0303970000a218a9
+:0303980000a09b27
+:03039900009f1da5
+:03039a00009d9e25
+:03039b00009c1fa4
+:03039c00009aa024
+:03039d00009921a3
+:03039e000097a124
+:03039f00009621a4
+:0303a0000094a026
+:0303a10000931fa7
+:0303a20000919e29
+:0303a30000901cab
+:0303a400008e9a2e
+:0303a500008d17b1
+:0303a600008b9534
+:0303a700008a12b7
+:0303a80000888e3c
+:0303a90000870bbf
+:0303aa0000858744
+:0303ab00008402c9
+:0303ac0000827d4f
+:0303ad000080f8d5
+:0303ae00007f735a
+:0303af00007deee0
+:0303b000007c6866
+:0303b100007ae1ee
+:0303b20000795b74
+:0303b3000077d4fc
+:0303b40000764d83
+:0303b5000074c60b
+:0303b60000733e93
+:0303b7000071b61c
+:0303b80000702ea4
+:0303b900006ea52e
+:0303ba00006d1db6
+:0303bb00006b9440
+:0303bc00006a0aca
+:0303bd0000688154
+:0303be000066f7df
+:0303bf0000656d69
+:0303c0000063e3f4
+:0303c1000062587f
+:0303c2000060cd0b
+:0303c300005f4296
+:0303c400005db722
+:0303c500005c2cad
+:0303c600005aa03a
+:0303c700005914c6
+:0303c80000578853
+:0303c9000055fce0
+:0303ca0000546f6d
+:0303cb000052e3fa
+:0303cc0000515687
+:0303cd00004fc915
+:0303ce00004e3ba3
+:0303cf00004cae31
+:0303d000004b20bf
+:0303d1000049924e
+:0303d200004804dc
+:0303d3000046766b
+:0303d4000044e8fa
+:0303d50000435989
+:0303d6000041ca19
+:0303d70000403ca7
+:0303d800003eac38
+:0303d900003d1dc7
+:0303da00003b8e57
+:0303db000039ffe7
+:0303dc0000386f77
+:0303dd000036df08
+:0303de0000354f98
+:0303df000033bf29
+:0303e00000322fb9
+:0303e10000309f4a
+:0303e200002f0fda
+:0303e300002d7e6c
+:0303e400002beefd
+:0303e500002a5d8e
+:0303e6000028cc20
+:0303e70000273bb1
+:0303e8000025aa43
+:0303e900002419d4
+:0303ea0000228866
+:0303eb000020f7f8
+:0303ec00001f658a
+:0303ed00001dd41c
+:0303ee00001c42ae
+:0303ef00001ab140
+:0303f00000191fd2
+:0303f10000178e64
+:0303f2000015fcf7
+:0303f30000146a89
+:0303f4000012d81c
+:0303f500001146ae
+:0303f600000fb540
+:0303f700000e23d2
+:0303f800000c9165
+:0303f900000afff8
+:0303fa0000096d8a
+:0303fb000007db1d
+:0303fc00000648b0
+:0303fd000004b643
+:0303fe00000324d5
+:0303ff0000019268
+:03040000000000f9
+:0304010003fe6e89
+:0304020003fcdc1c
+:0304030003fb4aae
+:0304040003f9b841
+:0304050003f825d4
+:0304060003f69367
+:0304070003f501f9
+:0304080003f36f8c
+:0304090003f1dd1f
+:03040a0003f04bb1
+:03040b0003eeba43
+:03040c0003ed28d5
+:03040d0003eb9668
+:03040e0003ea04fa
+:03040f0003e8728d
+:0304100003e6e11f
+:0304110003e54fb1
+:0304120003e3be43
+:0304130003e22cd5
+:0304140003e09b67
+:0304150003df09f9
+:0304160003dd788b
+:0304170003dbe71d
+:0304180003da56ae
+:0304190003d8c540
+:03041a0003d734d1
+:03041b0003d5a363
+:03041c0003d412f4
+:03041d0003d28285
+:03041e0003d0f117
+:03041f0003cf61a7
+:0304200003cdd138
+:0304210003cc41c8
+:0304220003cab159
+:0304230003c921e9
+:0304240003c7917a
+:0304250003c6010a
+:0304260003c4729a
+:0304270003c2e32a
+:0304280003c154b9
+:0304290003bfc44a
+:03042a0003be36d8
+:03042b0003bca768
+:03042c0003bb18f7
+:03042d0003b98a86
+:03042e0003b7fc15
+:03042f0003b66ea3
+:0304300003b4e032
+:0304310003b352c0
+:0304320003b1c54e
+:0304330003b037dc
+:0304340003aeaa6a
+:0304350003ad1df7
+:0304360003ab9184
+:0304370003aa0411
+:0304380003a8789e
+:0304390003a6ec2b
+:03043a0003a560b7
+:03043b0003a3d444
+:03043c0003a249cf
+:03043d0003a0be5b
+:03043e00039f33e6
+:03043f00039da872
+:03044000039c1dfd
+:03044100039a9388
+:0304420003990912
+:0304430003977f9d
+:030444000395f627
+:0304450003946cb1
+:030446000392e33b
+:0304470003915bc3
+:03044800038fd24d
+:03044900038e4ad5
+:03044a00038cc25e
+:03044b00038b3ae6
+:03044c000389b36e
+:03044d0003882cf5
+:03044e000386a57d
+:03044f0003851f03
+:030450000383988b
+:0304510003821211
+:0304520003808d97
+:03045300037f081c
+:03045400037d83a2
+:03045500037bfe28
+:03045600037a79ad
+:030457000378f532
+:03045800037772b5
+:030459000375ee3a
+:03045a0003746bbd
+:03045b000372e940
+:03045c00037166c3
+:03045d00036fe446
+:03045e00036e62c8
+:03045f00036ce14a
+:03046000036b60cb
+:030461000369df4d
+:0304620003685fcd
+:030463000366df4e
+:03046400036560cd
+:030465000363e14d
+:03046600036262cc
+:030467000360e34c
+:03046800035f65ca
+:03046900035de848
+:03046a00035c6bc5
+:03046b00035aee43
+:03046c00035971c0
+:03046d000357f53d
+:03046e0003567ab8
+:03046f000354fe35
+:03047000035384af
+:030471000352092a
+:0304720003508fa5
+:03047300034f161e
+:03047400034d9c99
+:03047500034c2411
+:03047600034aab8b
+:0304770003493402
+:030478000347bc7b
+:03047900034645f2
+:03047a000344cf69
+:03047b00034359df
+:03047c000341e356
+:03047d0003406ecb
+:03047e00033ef941
+:03047f00033d85b5
+:03048000033c1129
+:03048100033a9e9d
+:0304820003392b10
+:030483000337b983
+:03048400033647f5
+:030485000334d667
+:03048600033365d8
+:030487000331f44a
+:03048800033085b9
+:03048900032f1529
+:03048a00032da699
+:03048b00032c3807
+:03048c00032aca76
+:03048d0003295de3
+:03048e000327f051
+:03048f00032684bd
+:0304900003251829
+:030491000323ad95
+:0304920003224200
+:030493000320d86b
+:03049400031f6ed5
+:03049500031e053e
+:03049600031c9ca8
+:03049700031b3410
+:030498000319cd78
+:03049900031866df
+:03049a0003170045
+:03049b0003159aac
+:03049c0003143511
+:03049d000312d077
+:03049e0003116cdb
+:03049f000310083f
+:0304a000030ea6a2
+:0304a100030d4305
+:0304a200030be168
+:0304a300030a80c9
+:0304a40003092029
+:0304a5000307c08a
+:0304a600030660ea
+:0304a70003050248
+:0304a8000303a3a8
+:0304a90003024605
+:0304aa000300e963
+:0304ab0002ff8cc1
+:0304ac0002fe311c
+:0304ad0002fcd678
+:0304ae0002fb7bd3
+:0304af0002fa212d
+:0304b00002f8c887
+:0304b10002f76fe0
+:0304b20002f61738
+:0304b30002f4c090
+:0304b40002f36ae6
+:0304b50002f2133d
+:0304b60002f0be93
+:0304b70002ef69e8
+:0304b80002ee153c
+:0304b90002ecc290
+:0304ba0002eb6fe3
+:0304bb0002ea1d35
+:0304bc0002e8cc87
+:0304bd0002e77bd8
+:0304be0002e62b28
+:0304bf0002e4dc78
+:0304c00002e38dc7
+:0304c10002e23f15
+:0304c20002e0f263
+:0304c30002dfa5b0
+:0304c40002de59fc
+:0304c50002dd0e47
+:0304c60002dbc393
+:0304c70002da79dd
+:0304c80002d93026
+:0304c90002d7e86f
+:0304ca0002d6a0b7
+:0304cb0002d559fe
+:0304cc0002d41344
+:0304cd0002d2cd8b
+:0304ce0002d189cf
+:0304cf0002d04414
+:0304d00002cf0157
+:0304d10002cdbe9b
+:0304d20002cc7ddc
+:0304d30002cb3b1e
+:0304d40002c9fb5f
+:0304d50002c8bb9f
+:0304d60002c77ddd
+:0304d70002c63e1c
+:0304d80002c50159
+:0304d90002c3c497
+:0304da0002c288d3
+:0304db0002c14d0e
+:0304dc0002c01348
+:0304dd0002bed983
+:0304de0002bda1bb
+:0304df0002bc69f3
+:0304e00002bb312b
+:0304e10002b9fb62
+:0304e20002b8c598
+:0304e30002b790cd
+:0304e40002b65c01
+:0304e50002b52934
+:0304e60002b3f767
+:0304e70002b2c599
+:0304e80002b194ca
+:0304e90002b064fa
+:0304ea0002af3529
+:0304eb0002ae0658
+:0304ec0002acd986
+:0304ed0002abacb3
+:0304ee0002aa80df
+:0304ef0002a9540b
+:0304f00002a82a35
+:0304f10002a7015e
+:0304f20002a5d888
+:0304f30002a4b0b0
+:0304f40002a389d7
+:0304f50002a263fd
+:0304f60002a13d23
+:0304f70002a01947
+:0304f800029ef56c
+:0304f900029dd28f
+:0304fa00029cb0b1
+:0304fb00029b8fd2
+:0304fc00029a6ff2
+:0304fd0002995011
+:0304fe0002983130
+:0304ff000297144d
+:030500000295f76a
+:030501000294db86
+:030502000293c0a1
+:030503000292a6bb
+:0305040002918cd5
+:03050500029074ed
+:03050600028f5d04
+:03050700028e461b
+:03050800028d3031
+:03050900028c1b46
+:03050a00028b075a
+:03050b000289f46e
+:03050c000288e280
+:03050d000287d191
+:03050e000286c1a1
+:03050f000285b1b1
+:030510000284a3bf
+:03051100028395cd
+:03051200028289d9
+:0305130002817de5
+:03051400028072f0
+:03051500027f68fa
+:03051600027e5f03
+:03051700027d570b
+:03051800027c5012
+:03051900027b4a18
+:03051a00027a441e
+:03051b0002794022
+:03051c0002783d25
+:03051d0002773a28
+:03051e0002763929
+:03051f000275382a
+:0305200002743929
+:0305210002733a28
+:0305220002723c26
+:0305230002714022
+:030524000270441e
+:03052500026f4919
+:03052600026e4f13
+:03052700026d570b
+:03052800026c5f03
+:03052900026b68fa
+:03052a00026a72f0
+:03052b0002697de5
+:03052c00026889d9
+:03052d00026796cc
+:03052e000266a4be
+:03052f000265b3af
+:030530000264c39f
+:030531000263d48e
+:030532000262e67c
+:030533000261f969
+:0305340002610d54
+:030535000260223f
+:03053600025f372a
+:03053700025e4e13
+:03053800025d66fb
+:03053900025c7fe2
+:03053a00025b99c8
+:03053b00025ab4ad
+:03053c000259d091
+:03053d000258ed74
+:03053e0002580b55
+:03053f0002572a36
+:0305400002564a16
+:0305410002556cf4
+:0305420002548ed2
+:030543000253b1af
+:030544000252d58b
+:030545000251fa66
+:030546000251213e
+:0305470002504817
+:03054800024f70ef
+:03054900024e9ac5
+:03054a00024dc49b
+:03054b00024cef70
+:03054c00024c1c42
+:03054d00024b4a14
+:03054e00024a78e6
+:03054f000249a8b6
+:030550000248d985
+:0305510002480a53
+:0305520002473d20
+:03055300024671ec
+:030554000245a6b7
+:030555000244dc81
+:0305560002441349
+:0305570002434c10
+:03055800024285d7
+:030559000241bf9d
+:03055a000240fb61
+:03055b0002403724
+:03055c00023f75e6
+:03055d00023eb3a8
+:03055e00023df368
+:03055f00023d3426
+:03056000023c76e4
+:03056100023bb9a1
+:03056200023afd5d
+:03056300023a4217
+:03056400023988d1
+:030565000238d089
+:0305660002381840
+:03056700023762f6
+:030568000236acac
+:030569000235f860
+:03056a0002354512
+:03056b00023493c4
+:03056c000233e275
+:03056d0002333224
+:03056e00023283d3
+:03056f000231d680
+:030570000231292c
+:0305710002307ed7
+:03057200022fd481
+:03057300022f2a2a
+:03057400022e82d2
+:03057500022ddc78
+:03057600022d361d
+:03057700022c91c2
+:03057800022bee65
+:03057900022b4b07
+:03057a00022aaaa8
+:03057b00022a0a47
+:03057c0002296be6
+:03057d000228cd84
+:03057e0002283020
+:03057f00022795bb
+:030580000226fa56
+:03058100022661ee
+:030582000225c986
+:030583000225321c
+:0305840002249cb2
+:0305850002240746
+:03058600022373da
+:030587000222e16c
+:03058800022250fc
+:030589000221c08c
+:03058a000221311a
+:03058b000220a3a8
+:03058c0002201634
+:03058d00021f8bbf
+:03058e00021f0049
+:03058f00021e77d2
+:03059000021def5a
+:03059100021d68e0
+:03059200021ce266
+:03059300021c5ee9
+:03059400021bda6d
+:03059500021b58ee
+:03059600021ad76f
+:03059700021a57ee
+:030598000219d86d
+:0305990002195be9
+:03059a000218de66
+:03059b00021863e0
+:03059c000217e95a
+:03059d00021770d2
+:03059e000216f949
+:03059f00021682bf
+:0305a00002160d33
+:0305a100021599a7
+:0305a20002152619
+:0305a3000214b48b
+:0305a400021443fb
+:0305a5000213d46a
+:0305a600021366d7
+:0305a7000212f944
+:0305a80002128daf
+:0305a90002122219
+:0305aa000211b982
+:0305ab00021151e9
+:0305ac000210e951
+:0305ad00021084b5
+:0305ae0002101f19
+:0305af00020fbb7d
+:0305b000020f59de
+:0305b100020ef83f
+:0305b200020e989e
+:0305b300020e39fc
+:0305b400020ddc59
+:0305b500020d7fb5
+:0305b600020d240f
+:0305b700020cca69
+:0305b800020c72c0
+:0305b900020c1a17
+:0305ba00020bc46d
+:0305bb00020b6fc1
+:0305bc00020b1b14
+:0305bd00020ac867
+:0305be00020a77b7
+:0305bf00020a2706
+:0305c0000209d756
+:0305c10002098aa2
+:0305c20002093dee
+:0305c3000208f239
+:0305c4000208a783
+:0305c50002085ecb
+:0305c60002081711
+:0305c7000207d058
+:0305c80002078b9c
+:0305c900020747df
+:0305ca0002070421
+:0305cb000206c263
+:0305cc00020681a3
+:0305cd00020642e1
+:0305ce000206041e
+:0305cf000205c75b
+:0305d00002058c95
+:0305d100020551cf
+:0305d20002051807
+:0305d3000204e03f
+:0305d4000204a975
+:0305d500020474a9
+:0305d600020440dc
+:0305d70002040d0e
+:0305d8000203db40
+:0305d9000203aa70
+:0305da0002037b9e
+:0305db0002034dcb
+:0305dc00020320f7
+:0305dd000202f423
+:0305de000202c94d
+:0305df000202a075
+:0305e0000202789c
+:0305e100020251c2
+:0305e20002022ce6
+:0305e3000202070a
+:0305e4000201e42d
+:0305e5000201c24e
+:0305e6000201a26d
+:0305e7000201828c
+:0305e800020164a9
+:0305e900020147c5
+:0305ea0002012be0
+:0305eb00020111f9
+:0305ec000200f812
+:0305ed000200e029
+:0305ee000200c93f
+:0305ef000200b354
+:0305f00002009f67
+:0305f10002008c79
+:0305f20002007a8a
+:0305f3000200699a
+:0305f40002005aa8
+:0305f50002004cb5
+:0305f60002003fc1
+:0305f700020033cc
+:0305f800020028d6
+:0305f90002001fde
+:0305fa00020017e5
+:0305fb00020010eb
+:0305fc0002000bef
+:0305fd00020007f2
+:0305fe00020003f5
+:0305ff00020002f5
+:03060000020001f4
+:03060100020002f2
+:03060200020003f0
+:03060300020007eb
+:0306040002000be6
+:03060500020010e0
+:03060600020017d8
+:0306070002001fcf
+:03060800020028c5
+:03060900020033b9
+:03060a0002003fac
+:03060b0002004c9e
+:03060c0002005a8f
+:03060d000200697f
+:03060e0002007a6d
+:03060f0002008c5a
+:0306100002009f46
+:030611000200b331
+:030612000200c91a
+:030613000200e002
+:030614000200f8e9
+:03061500020111ce
+:0306160002012bb3
+:0306170002014796
+:0306180002016478
+:0306190002018259
+:03061a000201a238
+:03061b000201c217
+:03061c000201e4f4
+:03061d00020207cf
+:03061e0002022ca9
+:03061f0002025183
+:030620000202785b
+:030621000202a032
+:030622000202c908
+:030623000202f4dc
+:03062400020320ae
+:0306250002034d80
+:0306260002037b51
+:030627000203aa21
+:030628000203dbef
+:0306290002040dbb
+:03062a0002044087
+:03062b0002047452
+:03062c000204a91c
+:03062d000204e0e4
+:03062e00020518aa
+:03062f0002055170
+:0306300002058c34
+:030631000205c7f8
+:03063200020604b9
+:030633000206427a
+:030634000206813a
+:030635000206c2f8
+:03063600020704b4
+:0306370002074770
+:0306380002078b2b
+:030639000207d0e5
+:03063a000208179c
+:03063b0002085e54
+:03063c000208a70a
+:03063d000208f2be
+:03063e0002093d71
+:03063f0002098a23
+:030640000209d7d5
+:03064100020a2783
+:03064200020a7732
+:03064300020ac8e0
+:03064400020b1b8b
+:03064500020b6f36
+:03064600020bc4e0
+:03064700020c1a88
+:03064800020c722f
+:03064900020ccad6
+:03064a00020d247a
+:03064b00020d7f1e
+:03064c00020ddcc0
+:03064d00020e3961
+:03064e00020e9801
+:03064f00020ef8a0
+:03065000020f593d
+:03065100020fbbda
+:0306520002101f74
+:030653000210840e
+:030654000210e9a8
+:030655000211513e
+:030656000211b9d5
+:030657000212226a
+:0306580002128dfe
+:030659000212f991
+:03065a0002136622
+:03065b000213d4b3
+:03065c0002144342
+:03065d000214b4d0
+:03065e000215265c
+:03065f00021599e8
+:0306600002160d72
+:03066100021682fc
+:030662000216f984
+:030663000217700b
+:030664000217e991
+:0306650002186315
+:030666000218de99
+:0306670002195b1a
+:030668000219d89c
+:03066900021a571b
+:03066a00021ad79a
+:03066b00021b5817
+:03066c00021bda94
+:03066d00021c5e0e
+:03066e00021ce289
+:03066f00021d6801
+:03067000021def79
+:03067100021e77ef
+:03067200021f0064
+:03067300021f8bd8
+:030674000220164b
+:030675000220a3bd
+:030676000221312d
+:030677000221c09d
+:030678000222500b
+:030679000222e179
+:03067a00022373e5
+:03067b000224074f
+:03067c0002249cb9
+:03067d0002253221
+:03067e000225c989
+:03067f00022661ef
+:030680000226fa55
+:03068100022795b8
+:030682000228301b
+:030683000228cd7d
+:0306840002296bdd
+:03068500022a0a3c
+:03068600022aaa9b
+:03068700022b4bf8
+:03068800022bee54
+:03068900022c91af
+:03068a00022d3608
+:03068b00022ddc61
+:03068c00022e82b9
+:03068d00022f2a0f
+:03068e00022fd464
+:03068f0002307eb8
+:030690000231290b
+:030691000231d65d
+:03069200023283ae
+:03069300023332fd
+:030694000233e24c
+:0306950002349399
+:03069600023545e5
+:030697000235f831
+:030698000236ac7b
+:03069900023762c3
+:03069a000238180b
+:03069b000238d052
+:03069c0002398898
+:03069d00023a42dc
+:03069e00023afd20
+:03069f00023bb962
+:0306a000023c76a3
+:0306a100023d34e3
+:0306a200023df323
+:0306a300023eb361
+:0306a400023f759d
+:0306a500024037d9
+:0306a6000240fb14
+:0306a7000241bf4e
+:0306a80002428586
+:0306a90002434cbd
+:0306aa00024413f4
+:0306ab000244dc2a
+:0306ac000245a65e
+:0306ad0002467191
+:0306ae0002473dc3
+:0306af0002480af4
+:0306b0000248d924
+:0306b1000249a853
+:0306b200024a7881
+:0306b300024b4aad
+:0306b400024c1cd9
+:0306b500024cef05
+:0306b600024dc42e
+:0306b700024e9a56
+:0306b800024f707e
+:0306b900025048a4
+:0306ba00025121c9
+:0306bb000251faef
+:0306bc000252d512
+:0306bd000253b134
+:0306be0002548e55
+:0306bf0002556c75
+:0306c00002564a95
+:0306c10002572ab3
+:0306c20002580bd0
+:0306c3000258eded
+:0306c4000259d008
+:0306c500025ab422
+:0306c600025b993b
+:0306c700025c7f53
+:0306c800025d666a
+:0306c900025e4e80
+:0306ca00025f3795
+:0306cb00026022a8
+:0306cc0002610dbb
+:0306cd000261f9ce
+:0306ce000262e6df
+:0306cf000263d4ef
+:0306d0000264c3fe
+:0306d1000265b30c
+:0306d2000266a419
+:0306d30002679625
+:0306d40002688930
+:0306d50002697d3a
+:0306d600026a7243
+:0306d700026b684b
+:0306d800026c5f52
+:0306d900026d5758
+:0306da00026e4f5e
+:0306db00026f4962
+:0306dc0002704465
+:0306dd0002714067
+:0306de0002723c69
+:0306df0002733a69
+:0306e00002743968
+:0306e10002753867
+:0306e20002763964
+:0306e30002773a61
+:0306e40002783d5c
+:0306e50002794057
+:0306e600027a4451
+:0306e700027b4a49
+:0306e800027c5041
+:0306e900027d5738
+:0306ea00027e5f2e
+:0306eb00027f6823
+:0306ec0002807217
+:0306ed0002817d0a
+:0306ee00028289fc
+:0306ef00028395ee
+:0306f0000284a3de
+:0306f1000285b1ce
+:0306f2000286c1bc
+:0306f3000287d1aa
+:0306f4000288e297
+:0306f5000289f483
+:0306f600028b076d
+:0306f700028c1b57
+:0306f800028d3040
+:0306f900028e4628
+:0306fa00028f5d0f
+:0306fb00029074f6
+:0306fc0002918cdc
+:0306fd000292a6c0
+:0306fe000293c0a4
+:0306ff000294db87
+:030700000295f768
+:0307010002971448
+:0307020002983129
+:0307030002995008
+:03070400029a6fe7
+:03070500029b8fc5
+:03070600029cb0a2
+:03070700029dd27e
+:03070800029ef559
+:0307090002a01932
+:03070a0002a13d0c
+:03070b0002a263e4
+:03070c0002a389bc
+:03070d0002a4b093
+:03070e0002a5d869
+:03070f0002a7013d
+:0307100002a82a12
+:0307110002a954e6
+:0307120002aa80b8
+:0307130002abac8a
+:0307140002acd95b
+:0307150002ae062b
+:0307160002af35fa
+:0307170002b064c9
+:0307180002b19497
+:0307190002b2c564
+:03071a0002b3f730
+:03071b0002b529fb
+:03071c0002b65cc6
+:03071d0002b79090
+:03071e0002b8c559
+:03071f0002b9fb21
+:0307200002bb31e8
+:0307210002bc69ae
+:0307220002bda174
+:0307230002bed93a
+:0307240002c013fd
+:0307250002c14dc1
+:0307260002c28884
+:0307270002c3c446
+:0307280002c50106
+:0307290002c63ec7
+:03072a0002c77d86
+:03072b0002c8bb46
+:03072c0002c9fb04
+:03072d0002cb3bc1
+:03072e0002cc7d7d
+:03072f0002cdbe3a
+:0307300002cf01f4
+:0307310002d044af
+:0307320002d18968
+:0307330002d2cd22
+:0307340002d413d9
+:0307350002d55991
+:0307360002d6a048
+:0307370002d7e8fe
+:0307380002d930b3
+:0307390002da7968
+:03073a0002dbc31c
+:03073b0002dd0ece
+:03073c0002de5981
+:03073d0002dfa533
+:03073e0002e0f2e4
+:03073f0002e23f94
+:0307400002e38d44
+:0307410002e4dcf3
+:0307420002e62ba1
+:0307430002e77b4f
+:0307440002e8ccfc
+:0307450002ea1da8
+:0307460002eb6f54
+:0307470002ecc2ff
+:0307480002ee15a9
+:0307490002ef6953
+:03074a0002f0befc
+:03074b0002f213a4
+:03074c0002f36a4b
+:03074d0002f4c0f3
+:03074e0002f61799
+:03074f0002f76f3f
+:0307500002f8c8e4
+:0307510002fa2188
+:0307520002fb7b2c
+:0307530002fcd6cf
+:0307540002fe3171
+:0307550002ff8c14
+:030756000300e9b4
+:0307570003024654
+:030758000303a3f5
+:0307590003050293
+:03075a0003066033
+:03075b000307c0d1
+:03075c000309206e
+:03075d00030a800c
+:03075e00030be1a9
+:03075f00030d4344
+:03076000030ea6df
+:030761000310087a
+:0307620003116c14
+:030763000312d0ae
+:0307640003143546
+:0307650003159adf
+:0307660003170076
+:030767000318660e
+:030768000319cda5
+:03076900031b343b
+:03076a00031c9cd1
+:03076b00031e0565
+:03076c00031f6efa
+:03076d000320d88e
+:03076e0003224221
+:03076f000323adb4
+:0307700003251846
+:03077100032684d8
+:030772000327f06a
+:0307730003295dfa
+:03077400032aca8b
+:03077500032c381a
+:03077600032da6aa
+:03077700032f1538
+:03077800033085c6
+:030779000331f455
+:03077a00033365e1
+:03077b000334d66e
+:03077c00033647fa
+:03077d000337b986
+:03077e0003392b11
+:03077f00033a9e9c
+:03078000033c1126
+:03078100033d85b0
+:03078200033ef93a
+:0307830003406ec2
+:030784000341e34b
+:03078500034359d2
+:030786000344cf5a
+:03078700034645e1
+:030788000347bc68
+:03078900034934ed
+:03078a00034aab74
+:03078b00034c24f8
+:03078c00034d9c7e
+:03078d00034f1601
+:03078e0003508f86
+:03078f0003520909
+:030790000353848c
+:030791000354fe10
+:0307920003567a91
+:030793000357f514
+:0307940003597195
+:03079500035aee16
+:03079600035c6b96
+:03079700035de817
+:03079800035f6597
+:030799000360e317
+:03079a0003626295
+:03079b000363e114
+:03079c0003656092
+:03079d000366df11
+:03079e0003685f8e
+:03079f000369df0c
+:0307a000036b6088
+:0307a100036ce105
+:0307a200036e6281
+:0307a300036fe4fd
+:0307a40003716678
+:0307a5000372e9f3
+:0307a60003746b6e
+:0307a7000375eee9
+:0307a80003777262
+:0307a9000378f5dd
+:0307aa00037a7956
+:0307ab00037bfecf
+:0307ac00037d8347
+:0307ad00037f08bf
+:0307ae0003808d38
+:0307af00038212b0
+:0307b00003839828
+:0307b10003851f9e
+:0307b2000386a516
+:0307b30003882c8c
+:0307b4000389b303
+:0307b500038b3a79
+:0307b600038cc2ef
+:0307b700038e4a64
+:0307b800038fd2da
+:0307b90003915b4e
+:0307ba000392e3c4
+:0307bb0003946c38
+:0307bc000395f6ac
+:0307bd0003977f20
+:0307be0003990993
+:0307bf00039a9307
+:0307c000039c1d7a
+:0307c100039da8ed
+:0307c200039f335f
+:0307c30003a0bed2
+:0307c40003a24944
+:0307c50003a3d4b7
+:0307c60003a56028
+:0307c70003a6ec9a
+:0307c80003a8780b
+:0307c90003aa047c
+:0307ca0003ab91ed
+:0307cb0003ad1d5e
+:0307cc0003aeaacf
+:0307cd0003b0373f
+:0307ce0003b1c5af
+:0307cf0003b3521f
+:0307d00003b4e08f
+:0307d10003b66efe
+:0307d20003b7fc6e
+:0307d30003b98add
+:0307d40003bb184c
+:0307d50003bca7bb
+:0307d60003be3629
+:0307d70003bfc499
+:0307d80003c15406
+:0307d90003c2e375
+:0307da0003c472e3
+:0307db0003c60151
+:0307dc0003c791bf
+:0307dd0003c9212c
+:0307de0003cab19a
+:0307df0003cc4107
+:0307e00003cdd175
+:0307e10003cf61e2
+:0307e20003d0f150
+:0307e30003d282bc
+:0307e40003d41229
+:0307e50003d5a396
+:0307e60003d73402
+:0307e70003d8c56f
+:0307e80003da56db
+:0307e90003dbe748
+:0307ea0003dd78b4
+:0307eb0003df0920
+:0307ec0003e09b8c
+:0307ed0003e22cf8
+:0307ee0003e3be64
+:0307ef0003e54fd0
+:0307f00003e6e13c
+:0307f10003e872a8
+:0307f20003ea0413
+:0307f30003eb967f
+:0307f40003ed28ea
+:0307f50003eeba56
+:0307f60003f04bc2
+:0307f70003f1dd2e
+:0307f80003f36f99
+:0307f90003f50104
+:0307fa0003f69370
+:0307fb0003f825db
+:0307fc0003f9b846
+:0307fd0003fb4ab1
+:0307fe0003fcdc1d
+:0307ff0003fe6e88
+:00000001ff
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
index f60e4dcda8561d97a4b9e8665570d81614227164..79405773c74135b778f5a10be375ba70bc57d76a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
@@ -159,33 +159,68 @@ BEGIN
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
-    u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
-                                               PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+    u_mm_file_reg_unb_system_info    : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+                                                  PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
 
-    u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
-                                               PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+    u_mm_file_rom_unb_system_info    : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+                                                  PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
 
-    u_mm_file_reg_wdi             : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
-                                               PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+    u_mm_file_reg_wdi                : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+                                                  PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
 
-    u_mm_file_reg_unb_sens        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
-                                               PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+    u_mm_file_reg_unb_sens           : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+                                                  PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
 
-    u_mm_file_reg_unb_pmbus       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
-                                               PORT MAP(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+    u_mm_file_reg_unb_pmbus          : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+                                                  PORT MAP(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
 
-    u_mm_file_reg_fpga_temp_sens  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
-                                               PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+    u_mm_file_reg_fpga_temp_sens     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+                                                PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
 
-    u_mm_file_reg_fpga_voltage_sens :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
-                                               PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+    u_mm_file_reg_fpga_voltage_sens  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+                                                PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
 
-    u_mm_file_reg_ppsh            : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+    u_mm_file_reg_ppsh               : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
                                                PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
 
     -- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
-    u_mm_file_reg_eth             : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
-                                               PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+    u_mm_file_reg_eth                : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+                                                PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+    u_mm_file_jesd204b               : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
+                                                PORT MAP(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+
+    u_mm_file_reg_dp_shiftram        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
+                                                PORT MAP(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+
+    u_mm_file_reg_bsn_source         : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
+                                                PORT MAP(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+
+    u_mm_file_reg_bsn_scheduler      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+                                                PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+
+    u_mm_file_reg_bsn_monitor_input  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
+                                                PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+
+    u_mm_file_reg_wg                 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
+                                                PORT MAP(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
+    u_mm_file_ram_wg                 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
+                                               PORT MAP(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+
+    u_mm_file_ram_diag_data_buf_jesd : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
+                                               PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
+    u_mm_file_reg_diag_data_buf_jesd : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
+                                               PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
+
+    u_mm_file_ram_diag_data_buf_bsn  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
+                                               PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
+    u_mm_file_reg_diag_data_buf_bsn  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
+                                               PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+
+    u_mm_file_ram_aduh_monitor       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
+                                               PORT MAP(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
+    u_mm_file_reg_aduh_monitor       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
+                                               PORT MAP(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
 
     ----------------------------------------------------------------------------
     -- Procedure that polls a sim control file that can be used to e.g. get
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 392b5eac21f078d7f3bbb56f04619092bbfe325a..2894ca55e4d73e521d026f154b371d1808c9d0d5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -1,513 +1,513 @@
--------------------------------------------------------------------------------
---
--- Copyright 2020
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- Licensed under the Apache License, Version 2.0 (the "License");
--- you may not use this file except in compliance with the License.
--- You may obtain a copy of the License at
---
---     http://www.apache.org/licenses/LICENSE-2.0
---
--- Unless required by applicable law or agreed to in writing, software
--- distributed under the License is distributed on an "AS IS" BASIS,
--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--- See the License for the specific language governing permissions and
--- limitations under the License.
---
--------------------------------------------------------------------------------
-
--- Author : J Hargreaves
--- Purpose:  
---   AIT - ADC (Jesd) receiver, input, timing and associated diagnostic blocks
--- Description:
---   Unb2b version for lab testing
---   Contains all the signal processing blocks to receive and time the ADC input data
---   See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
-
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
-USE unb2b_board_lib.unb2b_board_pkg.ALL;
-USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
-USE diag_lib.diag_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-USE work.lofar2_unb2b_adc_pkg.ALL;
-
-ENTITY node_adc_input_and_timing IS
-  GENERIC (
-    g_technology              : NATURAL := c_tech_arria10_e1sg;
-    g_buf_nof_data            : NATURAL := 8192; --1024;
-    g_nof_streams             : NATURAL := 12;
-    g_nof_sync_n              : NATURAL := 4;          -- Three ADCs per RCU share a sync
-    g_aduh_buffer_nof_symbols : NATURAL := 512;        -- Default 512
-    g_bsn_sync_timeout        : NATURAL := 200000000;  -- Default 200M, overide for short simulation 
-    g_sim                     : BOOLEAN := FALSE  
-  );
-  PORT (
-    -- clocks and resets
-    mm_clk                         : IN STD_LOGIC;
-    mm_rst                         : IN STD_LOGIC;
-    dp_clk                         : IN STD_LOGIC;
-    dp_rst                         : IN STD_LOGIC;
-
-    -- mm control buses
-    -- JESD 
-    jesd204b_mosi                  : IN  t_mem_mosi := c_mem_mosi_rst;
-    jesd204b_miso                  : OUT t_mem_miso := c_mem_miso_rst; 
- 
-    -- Shiftram (applies per-antenna delay)
-    reg_dp_shiftram_mosi           : IN  t_mem_mosi := c_mem_mosi_rst;
-    reg_dp_shiftram_miso           : OUT t_mem_miso := c_mem_miso_rst;
-
-    -- bsn source
-    reg_bsn_source_mosi            : IN  t_mem_mosi := c_mem_mosi_rst;
-    reg_bsn_source_miso            : OUT t_mem_miso := c_mem_miso_rst;
-
-    -- bsn scheduler
-    reg_bsn_scheduler_wg_mosi      : IN  t_mem_mosi := c_mem_mosi_rst;
-    reg_bsn_scheduler_wg_miso      : OUT t_mem_miso := c_mem_miso_rst;
-
-    -- WG
-    reg_wg_mosi                    : IN  t_mem_mosi := c_mem_mosi_rst;
-    reg_wg_miso                    : OUT t_mem_miso := c_mem_miso_rst;
-    ram_wg_mosi                    : IN  t_mem_mosi := c_mem_mosi_rst;
-    ram_wg_miso                    : OUT t_mem_miso := c_mem_miso_rst;
-
-    -- BSN MONITOR
-    reg_bsn_monitor_input_mosi     : IN  t_mem_mosi;
-    reg_bsn_monitor_input_miso     : OUT t_mem_miso;
-
-    -- Data buffer for raw samples
-    ram_diag_data_buf_jesd_mosi    : IN  t_mem_mosi;
-    ram_diag_data_buf_jesd_miso    : OUT t_mem_miso;
-    reg_diag_data_buf_jesd_mosi    : IN  t_mem_mosi;
-    reg_diag_data_buf_jesd_miso    : OUT t_mem_miso;
-
-    -- Data buffer for framed samples (variable depth)
-    ram_diag_data_buf_bsn_mosi     : IN  t_mem_mosi;
-    ram_diag_data_buf_bsn_miso     : OUT t_mem_miso;
-    reg_diag_data_buf_bsn_mosi     : IN  t_mem_mosi;
-    reg_diag_data_buf_bsn_miso     : OUT t_mem_miso;
-
-    -- Aduh (statistics) monitor
-    ram_aduh_monitor_mosi          : IN  t_mem_mosi;
-    ram_aduh_monitor_miso          : OUT t_mem_miso;
-    reg_aduh_monitor_mosi          : IN  t_mem_mosi;
-    reg_aduh_monitor_miso          : OUT t_mem_miso;
-
-    -- JESD io signals
-    jesd204b_serial_data           : IN    STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0); 
-    jesd204b_refclk                : IN    STD_LOGIC; 
-    jesd204b_sysref                : IN    STD_LOGIC;
-    jesd204b_sync_n                : OUT   STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
-
-    -- Streaming data output
-    out_sosi_arr                   : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)        
-
-  );
-END node_adc_input_and_timing;
-
-
-ARCHITECTURE str OF node_adc_input_and_timing IS
-
-  -- Firmware version x.y
-  CONSTANT c_fw_version             : t_unb2b_board_fw_version := (1, 1);
-  CONSTANT c_mm_clk_freq            : NATURAL := c_unb2b_board_mm_clk_freq_100M;
-  CONSTANT c_lofar2_sample_clk_freq : NATURAL := 200 * 10**6;  -- alternate 160MHz. TODO: Use to check PPS
-
-  CONSTANT c_nof_streams_jesd204b   : NATURAL := 12;     -- IP is set up for 12 streams
-  CONSTANT c_nof_streams_db         : NATURAL := 2;      -- Streams of raw samples to record in db 
-
-  -- Waveform Generator
-  CONSTANT c_wg_buf_directory       : STRING := "data/";
-  CONSTANT c_wg_buf_dat_w           : NATURAL := c_unb2b_board_peripherals_mm_reg_default.ram_diag_wg_dat_w;
-  CONSTANT c_wg_buf_addr_w          : NATURAL := c_unb2b_board_peripherals_mm_reg_default.ram_diag_wg_adr_w;
-  SIGNAL wg_out_ovr                 : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);    
-  SIGNAL wg_out_val                 : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);    
-  SIGNAL wg_out_data                : STD_LOGIC_VECTOR(g_nof_streams*c_wg_buf_dat_w-1 DOWNTO 0);    
-  SIGNAL wg_out_sync                : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);    
-  SIGNAL trigger_wg                 : STD_LOGIC;
-
-  -- Frame parameters TBC
-  CONSTANT c_bs_bsn_w               : NATURAL := 64; --51;
-  CONSTANT c_bs_block_size          : NATURAL := 1024;
-  CONSTANT c_bs_nof_block_per_sync  : NATURAL := 390625;  -- generate a sync every 2s for testing
-  CONSTANT c_dp_shiftram_nof_samples: NATURAL := 4096;
-  CONSTANT c_data_w                 : NATURAL := 16;
-  CONSTANT c_dp_fifo_dc_size        : NATURAL := 64;
- 
- 
-  -- QSFP leds
-  SIGNAL qsfp_green_led_arr         : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
-  SIGNAL qsfp_red_led_arr           : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
-
-  -- JESD signals
-  SIGNAL rx_clk                     : STD_LOGIC; -- formerly jesd204b_frame_clk
-  SIGNAL rx_rst                     : STD_LOGIC; 
-  SIGNAL rx_sysref                  : STD_LOGIC; 
-
-  -- Sosis and sosi arrays
-  SIGNAL rx_sosi_arr                : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);         
-  SIGNAL dp_shiftram_snk_in_arr     : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);         
-  SIGNAL ant_sosi_arr               : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
-  SIGNAL diag_data_buf_snk_in_arr   : t_dp_sosi_arr(c_nof_streams_db-1 DOWNTO 0);
-  SIGNAL bs_sosi                    : t_dp_sosi;    
-  SIGNAL wg_sosi_arr                : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    
-  SIGNAL mux_sosi_arr               : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);         
-  SIGNAL nxt_mux_sosi_arr           : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
-  SIGNAL st_sosi_arr                : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    
-
-
-BEGIN
-
-  -----------------------------------------------------------------------------
-  -- JESD204B IP (ADC Handler)
-  -----------------------------------------------------------------------------
-  
-  u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b 
-  GENERIC MAP(
-    g_sim                => g_sim,                
-    g_nof_streams        => c_nof_streams_jesd204b,
-    g_nof_sync_n         => g_nof_sync_n        
-  )
-  PORT MAP(
-    jesd204b_refclk      => JESD204B_REFCLK,   
-    jesd204b_sysref      => JESD204B_SYSREF,   
-    jesd204b_sync_n_arr  => jesd204b_sync_n,   
-  
-    rx_sosi_arr          => rx_sosi_arr,          
-    rx_clk               => rx_clk,          
-    rx_rst               => rx_rst,          
-    rx_sysref            => rx_sysref,          
-  
-    -- MM
-    mm_clk               => mm_clk,           
-    mm_rst               => mm_rst,           
-  
-    jesd204b_mosi        => jesd204b_mosi,         
-    jesd204b_miso        => jesd204b_miso,         
-  
-     -- Serial
-    serial_tx_arr        => open,
-    serial_rx_arr        => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b-1 downto 0)
-  );
-
-
-  gen_jesd_mon_in : FOR i IN 0 TO c_nof_streams_db-1 GENERATE
-    diag_data_buf_snk_in_arr(i).data(c_data_w-1 downto 0) <= rx_sosi_arr(i).data(c_data_w-1 downto 0);
-    diag_data_buf_snk_in_arr(i).valid <= rx_sosi_arr(i).valid;
-    diag_data_buf_snk_in_arr(i).sop   <= '0';
-    diag_data_buf_snk_in_arr(i).eop   <= '0';
-    diag_data_buf_snk_in_arr(i).err   <= (OTHERS=>'0');
-  END GENERATE;
-
-
-  -----------------------------------------------------------------------------
-  -- Diagnostic Data Buffer (Records 8192 raw ADC samples after the PPS)
-  --   ToDo: Remove this JESD DB when the second (BSN) data buffer is working correctly
-  -----------------------------------------------------------------------------
-
-  u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
-  GENERIC MAP (
-    g_technology   => g_technology,
-    g_nof_streams  => c_nof_streams_db,
-    g_data_w       => c_data_w,
-    g_buf_nof_data => 8192,
-    g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
-  )
-  PORT MAP (
-    mm_rst            => mm_rst,
-    mm_clk            => mm_clk,
-    dp_rst            => rx_rst,
-    dp_clk            => rx_clk,
-
-    ram_data_buf_mosi => ram_diag_data_buf_jesd_mosi,
-    ram_data_buf_miso => ram_diag_data_buf_jesd_miso,
-    reg_data_buf_mosi => reg_diag_data_buf_jesd_mosi,
-    reg_data_buf_miso => reg_diag_data_buf_jesd_miso,
-
-    in_sosi_arr       => diag_data_buf_snk_in_arr,
-    in_sync           => rx_sysref
-  );
-
-  -----------------------------------------------------------------------------
-  -- Time delay: dp_shiftram
-  -- . copied from unb1_bn_capture_input (apertif)
-  --   Array range reversal is not done because everything is DOWNTO
-  -- . the input valid is always '1', even when there is no data 
-  -----------------------------------------------------------------------------
-  
-  gen_force_valid : FOR I IN 0 TO c_nof_streams_jesd204b-1 GENERATE
-    p_sosi : PROCESS(rx_sosi_arr)
-    BEGIN
-      dp_shiftram_snk_in_arr(I)       <= rx_sosi_arr(I);
-      dp_shiftram_snk_in_arr(I).valid <= '1';
-    END PROCESS;
-  END GENERATE;
-
-
-  u_dp_shiftram : ENTITY dp_lib.dp_shiftram
-  GENERIC MAP (
-    g_nof_streams => c_nof_streams_jesd204b, 
-    g_nof_words   => c_dp_shiftram_nof_samples,
-    g_data_w      => c_data_w, 
-    g_use_sync_in => TRUE
-  )
-  PORT MAP (
-    dp_rst   => rx_rst,
-    dp_clk   => rx_clk,
-
-    mm_rst   => mm_rst,
-    mm_clk   => mm_clk,
-
-    sync_in  => bs_sosi.sync,
-
-    reg_mosi => reg_dp_shiftram_mosi,
-    reg_miso => reg_dp_shiftram_miso,
-
-    snk_in_arr => dp_shiftram_snk_in_arr,
-
-    src_out_arr => ant_sosi_arr
-  );
-
-  -----------------------------------------------------------------------------
-  -- Timestamp
-  -----------------------------------------------------------------------------  
-  u_bsn_source : ENTITY dp_lib.mms_dp_bsn_source
-  GENERIC MAP (
-    g_cross_clock_domain     => TRUE,
-    g_block_size             => c_bs_block_size,
-    g_nof_block_per_sync     => c_bs_nof_block_per_sync,
-    g_bsn_w                  => c_bs_bsn_w
-  )
-  PORT MAP (
-    -- Clocks and reset
-    mm_rst            => mm_rst,
-    mm_clk            => mm_clk,
-    dp_rst            => rx_rst,
-    dp_clk            => rx_clk,
-    dp_pps            => rx_sysref,
-    
-    -- Memory-mapped clock domain
-    reg_mosi          => reg_bsn_source_mosi,
-    reg_miso          => reg_bsn_source_miso,
-    
-    -- Streaming clock domain
-    bs_sosi           => bs_sosi
-  );
-
-  u_bsn_trigger_wg : ENTITY dp_lib.mms_dp_bsn_scheduler
-  GENERIC MAP (
-    g_cross_clock_domain => TRUE,
-    g_bsn_w              => c_bs_bsn_w
-  )
-  PORT MAP (
-    -- Memory-mapped clock domain
-    mm_rst      => mm_rst,
-    mm_clk      => mm_clk,
-
-    reg_mosi    => reg_bsn_scheduler_wg_mosi,
-    reg_miso    => reg_bsn_scheduler_wg_miso,
-
-    -- Streaming clock domain
-    dp_rst      => rx_rst,
-    dp_clk      => rx_clk,
-
-    snk_in      => bs_sosi,  -- only uses eop (= block sync), bsn[]
-    trigger_out => trigger_wg
-  );
-
-
-  -----------------------------------------------------------------------------
-  -- WG (Test Signal Generator)
-  -----------------------------------------------------------------------------
-
-  u_wg_arr : ENTITY diag_lib.mms_diag_wg_wideband_arr
-  GENERIC MAP (
-    g_nof_streams        => g_nof_streams, 
-    g_cross_clock_domain => TRUE,
-    g_buf_dir            => c_wg_buf_directory,
-
-    -- Wideband parameters
-    g_wideband_factor    => 1, 
-
-    -- Basic WG parameters, see diag_wg.vhd for their meaning
-    g_buf_dat_w          => c_wg_buf_dat_w,
-    g_buf_addr_w         => c_wg_buf_addr_w,
-    g_calc_support       => TRUE,
-    g_calc_gain_w        => 1,
-    g_calc_dat_w         => c_wg_buf_dat_w
-  )
-  PORT MAP (
-    -- Memory-mapped clock domain
-    mm_rst              => mm_rst,
-    mm_clk              => mm_clk,
-
-    reg_mosi            => reg_wg_mosi,
-    reg_miso            => reg_wg_miso,
-
-    buf_mosi            => ram_wg_mosi,
-    buf_miso            => ram_wg_miso,
-
-    -- Streaming clock domain
-    st_rst              => rx_rst,
-    st_clk              => rx_clk,
-    st_restart          => trigger_wg,
-
-    out_sosi_arr        => wg_sosi_arr
-  );
-
-
-  -----------------------------------------------------------------------------
-  -- ADC/WG Mux (Input Select)
-  -----------------------------------------------------------------------------
-  
-  gen_mux : FOR I IN 0 TO g_nof_streams-1 GENERATE
-    p_sosi : PROCESS(ant_sosi_arr(I), wg_sosi_arr(I))
-    BEGIN
-      -- Default use the ADC data
-      nxt_mux_sosi_arr(I).data  <= ant_sosi_arr(I).data;
-      IF wg_sosi_arr(I).valid='1' THEN
-        -- Valid WG data overrules ADC data
-        nxt_mux_sosi_arr(I).data <= wg_sosi_arr(I).data;
-      END IF;
-    END PROCESS;
-  END GENERATE;
-
-  mux_sosi_arr  <= nxt_mux_sosi_arr WHEN rising_edge(rx_clk);
-
-  -----------------------------------------------------------------------------
-  -- Concatenate muxed data streams with bsn framing
-  -----------------------------------------------------------------------------
-  
-  gen_concat : FOR I IN 0 TO g_nof_streams-1 GENERATE
-    p_sosi : PROCESS(mux_sosi_arr(I), bs_sosi)
-    BEGIN
-      st_sosi_arr(I)       <= bs_sosi;
-      st_sosi_arr(I).data  <= mux_sosi_arr(I).data;
-    END PROCESS;
-  END GENERATE;
-
-
-  ---------------------------------------------------------------------------------------
-  -- Diagnostics on the bsn-framed data
-  --   . BSN Monitor (ToDo: can be removed as not part of the spec)
-  --   . Aduh monitor
-  --   . Data Buffer (variable depth from 1k-128k)
-  ---------------------------------------------------------------------------------------
-  
-
-  ---------------------------------------------------------------------------------------
-  -- BSN monitor (Block Checker)
-  ---------------------------------------------------------------------------------------
-  u_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
-  GENERIC MAP (
-    g_nof_streams        => 1,  -- They're all the same
-    g_sync_timeout       => g_bsn_sync_timeout,
-    g_bsn_w              => c_bs_bsn_w,
-    g_log_first_bsn      => FALSE
-  )
-  PORT MAP (
-    -- Memory-mapped clock domain
-    mm_rst      => mm_rst,
-    mm_clk      => mm_clk,
-    reg_mosi    => reg_bsn_monitor_input_mosi,
-    reg_miso    => reg_bsn_monitor_input_miso,
-
-    -- Streaming clock domain
-    dp_rst      => rx_rst,
-    dp_clk      => rx_clk,
-    in_sosi_arr => st_sosi_arr(0 downto 0)
-  );
-
-
-  -----------------------------------------------------------------------------
-  -- Monitor ADU/WG output
-  -----------------------------------------------------------------------------
-  u_aduh_monitor : ENTITY aduh_lib.mms_aduh_monitor_arr
-  GENERIC MAP (
-    g_cross_clock_domain   => TRUE,
-    g_nof_streams          => g_nof_streams,
-    g_symbol_w             => c_data_w,   --TBD 16?
-    g_nof_symbols_per_data => 1,          -- Wideband factor is 1          
-    g_nof_accumulations    => 200000512,  -- = 195313 blocks * 1024 samples
-    g_buffer_nof_symbols   => g_aduh_buffer_nof_symbols,  -- default 512, larger for full design
-    g_buffer_use_sync      => TRUE        -- True to capture all streams synchronously
-  )
-  PORT MAP (
-    -- Memory-mapped clock domain
-    mm_rst         => mm_rst,
-    mm_clk         => mm_clk,
-
-    reg_mosi       => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
-    reg_miso       => reg_aduh_monitor_miso,
-    buf_mosi       => ram_aduh_monitor_mosi, -- read and overwrite access to the signal path data buffers
-    buf_miso       => ram_aduh_monitor_miso,
-
-    -- Streaming clock domain
-    st_rst         => rx_rst,
-    st_clk         => rx_clk,
-
-    in_sosi_arr    => st_sosi_arr
-  );
-
-
- -----------------------------------------------------------------------------
--- Diagnostic Data Buffer
-  -----------------------------------------------------------------------------
-
-  u_diag_data_buffer_bsn : ENTITY diag_lib.mms_diag_data_buffer
-  GENERIC MAP (
-    g_technology   => g_technology,
-    g_nof_streams  => g_nof_streams,
-    g_data_w       => c_data_w,
-    g_buf_nof_data => g_buf_nof_data,
-    g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
-  )
-  PORT MAP (
-    mm_rst            => mm_rst,
-    mm_clk            => mm_clk,
-    dp_rst            => rx_rst,
-    dp_clk            => rx_clk,
-
-    ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
-    ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
-    reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
-    reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
-
-    in_sosi_arr       => st_sosi_arr,
-    in_sync           => st_sosi_arr(0).sync
-  );
-
-
-  -----------------------------------------------------------------------------
-  -- Output Stage
-  --   . Thin dual clock fifo to cross from jesd frame clock (rx_clk) to dp_clk domain
-  -----------------------------------------------------------------------------
- 
-  gen_dp_fifo_dc : FOR I IN 0 TO g_nof_streams-1 GENERATE
-    u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc
-      GENERIC MAP (
-        g_data_w         => c_data_w,
-        g_use_empty      => FALSE, --TRUE,
-        g_use_ctrl       => TRUE,
-        g_use_sync       => TRUE,
-        g_use_bsn        => TRUE,
-        g_fifo_size      => c_dp_fifo_dc_size
-      )
-      PORT MAP (
-        wr_rst           => rx_rst,
-        wr_clk           => rx_clk,
-        rd_rst           => dp_rst,
-        rd_clk           => dp_clk,
-        snk_in           => st_sosi_arr(I),
-        src_out          => out_sosi_arr(I)
-      );
-  END GENERATE;
-
-END str;
\ No newline at end of file
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : J Hargreaves
+-- Purpose:  
+--   AIT - ADC (Jesd) receiver, input, timing and associated diagnostic blocks
+-- Description:
+--   Unb2b version for lab testing
+--   Contains all the signal processing blocks to receive and time the ADC input data
+--   See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.lofar2_unb2b_adc_pkg.ALL;
+
+ENTITY node_adc_input_and_timing IS
+  GENERIC (
+    g_technology              : NATURAL := c_tech_arria10_e1sg;
+    g_buf_nof_data            : NATURAL := 8192; --1024;
+    g_nof_streams             : NATURAL := 12;
+    g_nof_sync_n              : NATURAL := 4;          -- Three ADCs per RCU share a sync
+    g_aduh_buffer_nof_symbols : NATURAL := 512;        -- Default 512
+    g_bsn_sync_timeout        : NATURAL := 200000000;  -- Default 200M, overide for short simulation 
+    g_sim                     : BOOLEAN := FALSE  
+  );
+  PORT (
+    -- clocks and resets
+    mm_clk                         : IN STD_LOGIC;
+    mm_rst                         : IN STD_LOGIC;
+    dp_clk                         : IN STD_LOGIC;
+    dp_rst                         : IN STD_LOGIC;
+
+    -- mm control buses
+    -- JESD 
+    jesd204b_mosi                  : IN  t_mem_mosi := c_mem_mosi_rst;
+    jesd204b_miso                  : OUT t_mem_miso := c_mem_miso_rst; 
+ 
+    -- Shiftram (applies per-antenna delay)
+    reg_dp_shiftram_mosi           : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_dp_shiftram_miso           : OUT t_mem_miso := c_mem_miso_rst;
+
+    -- bsn source
+    reg_bsn_source_mosi            : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_bsn_source_miso            : OUT t_mem_miso := c_mem_miso_rst;
+
+    -- bsn scheduler
+    reg_bsn_scheduler_wg_mosi      : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_bsn_scheduler_wg_miso      : OUT t_mem_miso := c_mem_miso_rst;
+
+    -- WG
+    reg_wg_mosi                    : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_wg_miso                    : OUT t_mem_miso := c_mem_miso_rst;
+    ram_wg_mosi                    : IN  t_mem_mosi := c_mem_mosi_rst;
+    ram_wg_miso                    : OUT t_mem_miso := c_mem_miso_rst;
+
+    -- BSN MONITOR
+    reg_bsn_monitor_input_mosi     : IN  t_mem_mosi;
+    reg_bsn_monitor_input_miso     : OUT t_mem_miso;
+
+    -- Data buffer for raw samples
+    ram_diag_data_buf_jesd_mosi    : IN  t_mem_mosi;
+    ram_diag_data_buf_jesd_miso    : OUT t_mem_miso;
+    reg_diag_data_buf_jesd_mosi    : IN  t_mem_mosi;
+    reg_diag_data_buf_jesd_miso    : OUT t_mem_miso;
+
+    -- Data buffer for framed samples (variable depth)
+    ram_diag_data_buf_bsn_mosi     : IN  t_mem_mosi;
+    ram_diag_data_buf_bsn_miso     : OUT t_mem_miso;
+    reg_diag_data_buf_bsn_mosi     : IN  t_mem_mosi;
+    reg_diag_data_buf_bsn_miso     : OUT t_mem_miso;
+
+    -- Aduh (statistics) monitor
+    ram_aduh_monitor_mosi          : IN  t_mem_mosi;
+    ram_aduh_monitor_miso          : OUT t_mem_miso;
+    reg_aduh_monitor_mosi          : IN  t_mem_mosi;
+    reg_aduh_monitor_miso          : OUT t_mem_miso;
+
+    -- JESD io signals
+    jesd204b_serial_data           : IN    STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0); 
+    jesd204b_refclk                : IN    STD_LOGIC; 
+    jesd204b_sysref                : IN    STD_LOGIC;
+    jesd204b_sync_n                : OUT   STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
+
+    -- Streaming data output
+    out_sosi_arr                   : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)        
+
+  );
+END node_adc_input_and_timing;
+
+
+ARCHITECTURE str OF node_adc_input_and_timing IS
+
+  -- Firmware version x.y
+  CONSTANT c_fw_version             : t_unb2b_board_fw_version := (1, 1);
+  CONSTANT c_mm_clk_freq            : NATURAL := c_unb2b_board_mm_clk_freq_100M;
+  CONSTANT c_lofar2_sample_clk_freq : NATURAL := 200 * 10**6;  -- alternate 160MHz. TODO: Use to check PPS
+
+  CONSTANT c_nof_streams_jesd204b   : NATURAL := 12;     -- IP is set up for 12 streams
+  CONSTANT c_nof_streams_db         : NATURAL := 2;      -- Streams of raw samples to record in db 
+
+  -- Waveform Generator
+  CONSTANT c_wg_buf_directory       : STRING := "data/";
+  CONSTANT c_wg_buf_dat_w           : NATURAL := 18; --default value of WG that fits 14 bits of ADC data
+  CONSTANT c_wg_buf_addr_w          : NATURAL := 10; --default value of WG for 1024 samples;
+  SIGNAL wg_out_ovr                 : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);    
+  SIGNAL wg_out_val                 : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);    
+  SIGNAL wg_out_data                : STD_LOGIC_VECTOR(g_nof_streams*c_wg_buf_dat_w-1 DOWNTO 0);    
+  SIGNAL wg_out_sync                : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);    
+  SIGNAL trigger_wg                 : STD_LOGIC;
+
+  -- Frame parameters TBC
+  CONSTANT c_bs_bsn_w               : NATURAL := 64; --51;
+  CONSTANT c_bs_block_size          : NATURAL := 1024;
+  CONSTANT c_bs_nof_block_per_sync  : NATURAL := 390625;  -- generate a sync every 2s for testing
+  CONSTANT c_dp_shiftram_nof_samples: NATURAL := 4096;
+  CONSTANT c_data_w                 : NATURAL := 16;
+  CONSTANT c_dp_fifo_dc_size        : NATURAL := 64;
+ 
+ 
+  -- QSFP leds
+  SIGNAL qsfp_green_led_arr         : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+  SIGNAL qsfp_red_led_arr           : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+
+  -- JESD signals
+  SIGNAL rx_clk                     : STD_LOGIC; -- formerly jesd204b_frame_clk
+  SIGNAL rx_rst                     : STD_LOGIC; 
+  SIGNAL rx_sysref                  : STD_LOGIC; 
+
+  -- Sosis and sosi arrays
+  SIGNAL rx_sosi_arr                : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);         
+  SIGNAL dp_shiftram_snk_in_arr     : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);         
+  SIGNAL ant_sosi_arr               : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+  SIGNAL diag_data_buf_snk_in_arr   : t_dp_sosi_arr(c_nof_streams_db-1 DOWNTO 0);
+  SIGNAL bs_sosi                    : t_dp_sosi;    
+  SIGNAL wg_sosi_arr                : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    
+  SIGNAL mux_sosi_arr               : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);         
+  SIGNAL nxt_mux_sosi_arr           : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL st_sosi_arr                : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    
+
+
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- JESD204B IP (ADC Handler)
+  -----------------------------------------------------------------------------
+  
+  u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b 
+  GENERIC MAP(
+    g_sim                => g_sim,                
+    g_nof_streams        => c_nof_streams_jesd204b,
+    g_nof_sync_n         => g_nof_sync_n        
+  )
+  PORT MAP(
+    jesd204b_refclk      => JESD204B_REFCLK,   
+    jesd204b_sysref      => JESD204B_SYSREF,   
+    jesd204b_sync_n_arr  => jesd204b_sync_n,   
+  
+    rx_sosi_arr          => rx_sosi_arr,          
+    rx_clk               => rx_clk,          
+    rx_rst               => rx_rst,          
+    rx_sysref            => rx_sysref,          
+  
+    -- MM
+    mm_clk               => mm_clk,           
+    mm_rst               => mm_rst,           
+  
+    jesd204b_mosi        => jesd204b_mosi,         
+    jesd204b_miso        => jesd204b_miso,         
+  
+     -- Serial
+    serial_tx_arr        => open,
+    serial_rx_arr        => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b-1 downto 0)
+  );
+
+
+  gen_jesd_mon_in : FOR i IN 0 TO c_nof_streams_db-1 GENERATE
+    diag_data_buf_snk_in_arr(i).data(c_data_w-1 downto 0) <= rx_sosi_arr(i).data(c_data_w-1 downto 0);
+    diag_data_buf_snk_in_arr(i).valid <= rx_sosi_arr(i).valid;
+    diag_data_buf_snk_in_arr(i).sop   <= '0';
+    diag_data_buf_snk_in_arr(i).eop   <= '0';
+    diag_data_buf_snk_in_arr(i).err   <= (OTHERS=>'0');
+  END GENERATE;
+
+
+  -----------------------------------------------------------------------------
+  -- Diagnostic Data Buffer (Records 8192 raw ADC samples after the PPS)
+  --   ToDo: Remove this JESD DB when the second (BSN) data buffer is working correctly
+  -----------------------------------------------------------------------------
+
+  u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
+  GENERIC MAP (
+    g_technology   => g_technology,
+    g_nof_streams  => c_nof_streams_db,
+    g_data_w       => c_data_w,
+    g_buf_nof_data => 8192,
+    g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+  )
+  PORT MAP (
+    mm_rst            => mm_rst,
+    mm_clk            => mm_clk,
+    dp_rst            => rx_rst,
+    dp_clk            => rx_clk,
+
+    ram_data_buf_mosi => ram_diag_data_buf_jesd_mosi,
+    ram_data_buf_miso => ram_diag_data_buf_jesd_miso,
+    reg_data_buf_mosi => reg_diag_data_buf_jesd_mosi,
+    reg_data_buf_miso => reg_diag_data_buf_jesd_miso,
+
+    in_sosi_arr       => diag_data_buf_snk_in_arr,
+    in_sync           => rx_sysref
+  );
+
+  -----------------------------------------------------------------------------
+  -- Time delay: dp_shiftram
+  -- . copied from unb1_bn_capture_input (apertif)
+  --   Array range reversal is not done because everything is DOWNTO
+  -- . the input valid is always '1', even when there is no data 
+  -----------------------------------------------------------------------------
+  
+  gen_force_valid : FOR I IN 0 TO c_nof_streams_jesd204b-1 GENERATE
+    p_sosi : PROCESS(rx_sosi_arr)
+    BEGIN
+      dp_shiftram_snk_in_arr(I)       <= rx_sosi_arr(I);
+      dp_shiftram_snk_in_arr(I).valid <= '1';
+    END PROCESS;
+  END GENERATE;
+
+
+  u_dp_shiftram : ENTITY dp_lib.dp_shiftram
+  GENERIC MAP (
+    g_nof_streams => c_nof_streams_jesd204b, 
+    g_nof_words   => c_dp_shiftram_nof_samples,
+    g_data_w      => c_data_w, 
+    g_use_sync_in => TRUE
+  )
+  PORT MAP (
+    dp_rst   => rx_rst,
+    dp_clk   => rx_clk,
+
+    mm_rst   => mm_rst,
+    mm_clk   => mm_clk,
+
+    sync_in  => bs_sosi.sync,
+
+    reg_mosi => reg_dp_shiftram_mosi,
+    reg_miso => reg_dp_shiftram_miso,
+
+    snk_in_arr => dp_shiftram_snk_in_arr,
+
+    src_out_arr => ant_sosi_arr
+  );
+
+  -----------------------------------------------------------------------------
+  -- Timestamp
+  -----------------------------------------------------------------------------  
+  u_bsn_source : ENTITY dp_lib.mms_dp_bsn_source
+  GENERIC MAP (
+    g_cross_clock_domain     => TRUE,
+    g_block_size             => c_bs_block_size,
+    g_nof_block_per_sync     => c_bs_nof_block_per_sync,
+    g_bsn_w                  => c_bs_bsn_w
+  )
+  PORT MAP (
+    -- Clocks and reset
+    mm_rst            => mm_rst,
+    mm_clk            => mm_clk,
+    dp_rst            => rx_rst,
+    dp_clk            => rx_clk,
+    dp_pps            => rx_sysref,
+    
+    -- Memory-mapped clock domain
+    reg_mosi          => reg_bsn_source_mosi,
+    reg_miso          => reg_bsn_source_miso,
+    
+    -- Streaming clock domain
+    bs_sosi           => bs_sosi
+  );
+
+  u_bsn_trigger_wg : ENTITY dp_lib.mms_dp_bsn_scheduler
+  GENERIC MAP (
+    g_cross_clock_domain => TRUE,
+    g_bsn_w              => c_bs_bsn_w
+  )
+  PORT MAP (
+    -- Memory-mapped clock domain
+    mm_rst      => mm_rst,
+    mm_clk      => mm_clk,
+
+    reg_mosi    => reg_bsn_scheduler_wg_mosi,
+    reg_miso    => reg_bsn_scheduler_wg_miso,
+
+    -- Streaming clock domain
+    dp_rst      => rx_rst,
+    dp_clk      => rx_clk,
+
+    snk_in      => bs_sosi,  -- only uses eop (= block sync), bsn[]
+    trigger_out => trigger_wg
+  );
+
+
+  -----------------------------------------------------------------------------
+  -- WG (Test Signal Generator)
+  -----------------------------------------------------------------------------
+
+  u_wg_arr : ENTITY diag_lib.mms_diag_wg_wideband_arr
+  GENERIC MAP (
+    g_nof_streams        => g_nof_streams, 
+    g_cross_clock_domain => TRUE,
+    g_buf_dir            => c_wg_buf_directory,
+
+    -- Wideband parameters
+    g_wideband_factor    => 1, 
+
+    -- Basic WG parameters, see diag_wg.vhd for their meaning
+    g_buf_dat_w          => c_wg_buf_dat_w,
+    g_buf_addr_w         => c_wg_buf_addr_w,
+    g_calc_support       => TRUE,
+    g_calc_gain_w        => 1,
+    g_calc_dat_w         => c_wg_buf_dat_w
+  )
+  PORT MAP (
+    -- Memory-mapped clock domain
+    mm_rst              => mm_rst,
+    mm_clk              => mm_clk,
+
+    reg_mosi            => reg_wg_mosi,
+    reg_miso            => reg_wg_miso,
+
+    buf_mosi            => ram_wg_mosi,
+    buf_miso            => ram_wg_miso,
+
+    -- Streaming clock domain
+    st_rst              => rx_rst,
+    st_clk              => rx_clk,
+    st_restart          => trigger_wg,
+
+    out_sosi_arr        => wg_sosi_arr
+  );
+
+
+  -----------------------------------------------------------------------------
+  -- ADC/WG Mux (Input Select)
+  -----------------------------------------------------------------------------
+  
+  gen_mux : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    p_sosi : PROCESS(ant_sosi_arr(I), wg_sosi_arr(I))
+    BEGIN
+      -- Default use the ADC data
+      nxt_mux_sosi_arr(I).data  <= ant_sosi_arr(I).data;
+      IF wg_sosi_arr(I).valid='1' THEN
+        -- Valid WG data overrules ADC data
+        nxt_mux_sosi_arr(I).data <= wg_sosi_arr(I).data;
+      END IF;
+    END PROCESS;
+  END GENERATE;
+
+  mux_sosi_arr  <= nxt_mux_sosi_arr WHEN rising_edge(rx_clk);
+
+  -----------------------------------------------------------------------------
+  -- Concatenate muxed data streams with bsn framing
+  -----------------------------------------------------------------------------
+  
+  gen_concat : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    p_sosi : PROCESS(mux_sosi_arr(I), bs_sosi)
+    BEGIN
+      st_sosi_arr(I)       <= bs_sosi;
+      st_sosi_arr(I).data  <= mux_sosi_arr(I).data;
+    END PROCESS;
+  END GENERATE;
+
+
+  ---------------------------------------------------------------------------------------
+  -- Diagnostics on the bsn-framed data
+  --   . BSN Monitor (ToDo: can be removed as not part of the spec)
+  --   . Aduh monitor
+  --   . Data Buffer (variable depth from 1k-128k)
+  ---------------------------------------------------------------------------------------
+  
+
+  ---------------------------------------------------------------------------------------
+  -- BSN monitor (Block Checker)
+  ---------------------------------------------------------------------------------------
+  u_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
+  GENERIC MAP (
+    g_nof_streams        => 1,  -- They're all the same
+    g_sync_timeout       => g_bsn_sync_timeout,
+    g_bsn_w              => c_bs_bsn_w,
+    g_log_first_bsn      => FALSE
+  )
+  PORT MAP (
+    -- Memory-mapped clock domain
+    mm_rst      => mm_rst,
+    mm_clk      => mm_clk,
+    reg_mosi    => reg_bsn_monitor_input_mosi,
+    reg_miso    => reg_bsn_monitor_input_miso,
+
+    -- Streaming clock domain
+    dp_rst      => rx_rst,
+    dp_clk      => rx_clk,
+    in_sosi_arr => st_sosi_arr(0 downto 0)
+  );
+
+
+  -----------------------------------------------------------------------------
+  -- Monitor ADU/WG output
+  -----------------------------------------------------------------------------
+  u_aduh_monitor : ENTITY aduh_lib.mms_aduh_monitor_arr
+  GENERIC MAP (
+    g_cross_clock_domain   => TRUE,
+    g_nof_streams          => g_nof_streams,
+    g_symbol_w             => c_data_w,   --TBD 16?
+    g_nof_symbols_per_data => 1,          -- Wideband factor is 1          
+    g_nof_accumulations    => 200000512,  -- = 195313 blocks * 1024 samples
+    g_buffer_nof_symbols   => g_aduh_buffer_nof_symbols,  -- default 512, larger for full design
+    g_buffer_use_sync      => TRUE        -- True to capture all streams synchronously
+  )
+  PORT MAP (
+    -- Memory-mapped clock domain
+    mm_rst         => mm_rst,
+    mm_clk         => mm_clk,
+
+    reg_mosi       => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
+    reg_miso       => reg_aduh_monitor_miso,
+    buf_mosi       => ram_aduh_monitor_mosi, -- read and overwrite access to the signal path data buffers
+    buf_miso       => ram_aduh_monitor_miso,
+
+    -- Streaming clock domain
+    st_rst         => rx_rst,
+    st_clk         => rx_clk,
+
+    in_sosi_arr    => st_sosi_arr
+  );
+
+
+ -----------------------------------------------------------------------------
+-- Diagnostic Data Buffer
+  -----------------------------------------------------------------------------
+
+  u_diag_data_buffer_bsn : ENTITY diag_lib.mms_diag_data_buffer
+  GENERIC MAP (
+    g_technology   => g_technology,
+    g_nof_streams  => g_nof_streams,
+    g_data_w       => c_data_w,
+    g_buf_nof_data => g_buf_nof_data,
+    g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+  )
+  PORT MAP (
+    mm_rst            => mm_rst,
+    mm_clk            => mm_clk,
+    dp_rst            => rx_rst,
+    dp_clk            => rx_clk,
+
+    ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
+    ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
+    reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
+    reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
+
+    in_sosi_arr       => st_sosi_arr,
+    in_sync           => st_sosi_arr(0).sync
+  );
+
+
+  -----------------------------------------------------------------------------
+  -- Output Stage
+  --   . Thin dual clock fifo to cross from jesd frame clock (rx_clk) to dp_clk domain
+  -----------------------------------------------------------------------------
+ 
+  gen_dp_fifo_dc : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc
+      GENERIC MAP (
+        g_data_w         => c_data_w,
+        g_use_empty      => FALSE, --TRUE,
+        g_use_ctrl       => TRUE,
+        g_use_sync       => TRUE,
+        g_use_bsn        => TRUE,
+        g_fifo_size      => c_dp_fifo_dc_size
+      )
+      PORT MAP (
+        wr_rst           => rx_rst,
+        wr_clk           => rx_clk,
+        rd_rst           => dp_rst,
+        rd_clk           => dp_clk,
+        snk_in           => st_sosi_arr(I),
+        src_out          => out_sosi_arr(I)
+      );
+  END GENERATE;
+
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
index 69af78de2eb6f28f3442d8541a4feadb98093104..3800989f765e705158af54b3325e79242d8a725b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
@@ -420,7 +420,7 @@ BEGIN
   ------------------------------------------------------------------------------
   proc_read_avs_regs : PROCESS
   BEGIN
-    wait for 100ns;
+    wait for 100 ns;
     avs_address(0) <= (others => '0');
     avs_chipselect(0) <= '0';
     avs_read(0) <= '0';
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fc4f4695d416169c17212b0ad4e7c7540a338a1f
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
@@ -0,0 +1,339 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_adc using WG data.
+--
+-- Description:
+--   MM control actions:
+--
+--   1) Enable calc mode for WG via reg_diag_wg with:
+--        freq = 20MHz
+--        ampl = 0.5 * 2**13
+--   
+--   2) Read current BSN from reg_bsn_scheduler_wg and write reg_bsn_scheduler_wg 
+--      to trigger start of WG at BSN.
+--     
+--   3) Read WG data via ram_aduh_mon into sp_sample and replay sp_sample for
+--      analogue view in Wave window:
+--   
+--   4) Read ADUH monitor power sum for via reg_aduh_mon and verify with 
+--      c_exp_wg_power_sp.
+--      View sp_power_sum in Wave window
+--
+-- Usage:
+--   > as 7    # default
+--   > as 12   # for detailed debugging
+--   > run -a  
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_adc_wg IS
+END tb_lofar2_unb2b_adc_wg;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_adc_wg IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 0; 
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb2b_board_fw_version := (1, 0);
+
+  CONSTANT c_eth_clk_period      : TIME := 8 ns;  -- 125 MHz XO on UniBoard
+  CONSTANT c_ext_clk_period      : TIME := 5 ns;
+  CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
+  CONSTANT c_pps_period          : NATURAL := 1000;
+
+  CONSTANT c_tb_clk_period       : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+  CONSTANT c_cable_delay         : TIME := 12 ns
+;
+  CONSTANT c_sample_freq         : NATURAL := c_unb2b_board_ext_clk_freq_200M/10**6;  -- 200 MSps
+  CONSTANT c_sample_period       : TIME := (10**6 / c_sample_freq) * 1 ps; 
+
+  CONSTANT c_nof_sync            : NATURAL := 5;
+  CONSTANT c_nof_block_per_sync  : NATURAL := 16; 
+ 
+  CONSTANT c_percentage          : REAL := 0.05;  -- percentage that actual value may differ from expected value
+  CONSTANT c_lo_factor           : REAL := 1.0 - c_percentage;  -- lower boundary  
+  CONSTANT c_hi_factor           : REAL := 1.0 + c_percentage;  -- higher boundary
+
+  CONSTANT c_nof_points          : NATURAL := 1024; 
+  CONSTANT c_nof_taps            : NATURAL := 16; 
+  
+  CONSTANT c_subband_period      : TIME := c_nof_points * c_sample_period;
+
+  -- WG
+  CONSTANT c_full_scale_ampl      : REAL := REAL(2**(18-1)-1);  -- = full scale of WG
+  CONSTANT c_bsn_start_wg         : NATURAL := 2;  -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+  CONSTANT c_ampl_sp              : NATURAL := 2**(14-1)/2;  -- in number of lsb
+  CONSTANT c_subband_sp           : REAL := 51.2;  -- Select subband at index 512/10 = 51.2 = 20 MHz
+  CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/512.0;  -- subband freq = Fs/512 = 200 MSps/512 = 390625 Hz sinus
+  CONSTANT c_wg_ampl_lsb          : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl;  -- amplitude in number of LSbit resolution steps
+  CONSTANT c_exp_wg_power_sp      : REAL := REAL(c_ampl_sp**2)/2.0 * REAL(c_nof_points*c_nof_block_per_sync);
+   
+  -- ADUH
+  CONSTANT c_mon_buffer_nof_samples  : NATURAL := 1024; --samples per stream 
+  CONSTANT c_mon_buffer_nof_words    : NATURAL := c_mon_buffer_nof_samples; 
+  
+  -- MM  
+  CONSTANT c_mm_file_reg_ppsh               : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
+  CONSTANT c_mm_file_reg_bsn_source         : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE";
+  CONSTANT c_mm_file_reg_bsn_scheduler_wg   : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
+  CONSTANT c_mm_file_reg_diag_wg            : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+  CONSTANT c_mm_file_reg_aduh_mon           : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_ADUH_MONITOR";
+  CONSTANT c_mm_file_ram_aduh_mon           : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ADUH_MONITOR";
+
+
+  -- Tb
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL sim_done            : STD_LOGIC := '0';
+  SIGNAL tb_clk              : STD_LOGIC := '0';  
+  SIGNAL rd_data             : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+
+  -- WG
+  SIGNAL dbg_c_exp_wg_power_sp : REAL := c_exp_wg_power_sp;
+  SIGNAL sp_samples            : t_integer_arr(0 TO c_mon_buffer_nof_samples-1) := (OTHERS=>0); 
+  SIGNAL sp_sample             : INTEGER := 0;
+  SIGNAL sp_power_sum          : UNSIGNED(63 DOWNTO 0);
+  SIGNAL current_bsn_wg        : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+
+  -- DUT
+  SIGNAL ext_clk             : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL ext_pps             : STD_LOGIC := '0'; 
+  SIGNAL pps_rst             : STD_LOGIC := '0';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+  SIGNAL eth_rxp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+  SIGNAL pmbus_scl           : STD_LOGIC;
+  SIGNAL pmbus_sda           : STD_LOGIC;
+
+  -- back transceivers
+  SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+  SIGNAL JESD204B_REFCLK      : STD_LOGIC := '1';
+
+  -- jesd204b syncronization signals
+  SIGNAL jesd204b_sysref     : STD_LOGIC;
+  SIGNAL jesd204b_sync_n     : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+BEGIN
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
+  JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2;  -- JESD sample clock (200MHz) 
+
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+  pmbus_scl <= 'H';  -- pull up
+  pmbus_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+  jesd204b_sysref <= pps;
+  ext_pps <= pps;
+
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_lofar_unb2b_adc : ENTITY work.lofar2_unb2b_adc
+  GENERIC MAP (
+    g_design_name => "lofar2_unb2b_adc_one_node",
+    g_design_note => "Lofar2 adc with one node",
+    g_sim         => c_sim,
+    g_sim_unb_nr  => c_unb_nr,
+    g_sim_node_nr => c_node_nr
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => ext_clk,
+    PPS          => pps,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => c_version,
+    ID           => c_id,
+    TESTIO       => open,
+
+    -- I2C Interface to Sensors
+    SENS_SC      => sens_scl,
+    SENS_SD      => sens_sda,
+
+    PMBUS_SC     => pmbus_scl,
+    PMBUS_SD     => pmbus_sda,
+    PMBUS_ALERT  => open,
+
+    -- 1GbE Control Interface
+    ETH_CLK      => eth_clk,
+    ETH_SGIN     => eth_rxp,
+    ETH_SGOUT    => eth_txp,
+
+    -- LEDs
+    QSFP_LED     => open,
+
+    -- back transceivers
+    JESD204B_SERIAL_DATA  => JESD204B_SERIAL_DATA,
+    JESD204B_REFCLK       => JESD204B_REFCLK,
+  
+    -- jesd204b syncronization signals
+    JESD204B_SYSREF => jesd204b_sysref,
+    JESD204B_SYNC_N => jesd204b_sync_n
+  );
+
+  ------------------------------------------------------------------------------
+  -- MM slave accesses via file IO
+  ------------------------------------------------------------------------------
+  tb_clk  <= NOT tb_clk AFTER c_tb_clk_period/2;    -- Testbench MM clock
+  
+  p_mm_stimuli : PROCESS
+    VARIABLE v_bsn                   : NATURAL;
+    VARIABLE v_sp_power_sum          : REAL;
+  BEGIN
+    -- Wait for DUT power up after reset
+    WAIT FOR 1 us;
+    
+    proc_common_wait_until_hi_lo(ext_clk, ext_pps);
+        
+    ----------------------------------------------------------------------------
+    -- Enable BS
+    ----------------------------------------------------------------------------
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3,                    0, tb_clk);
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2,                    0, tb_clk);  -- Init BSN = 0
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk);  -- nof_block_per_sync
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0,         16#00000003#, tb_clk);  -- Enable BS at PPS
+    
+    ----------------------------------------------------------------------------
+    -- Enable WG
+    ----------------------------------------------------------------------------
+    --   0 : mode[7:0]           --> off=0, calc=1, repeat=2, single=3)
+    --       nof_samples[31:16]  --> <= c_ram_wg_size=1024
+    --   1 : phase[15:0]
+    --   2 : freq[30:0]
+    --   3 : ampl[16:0]
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024*2**16 + 1, tb_clk);  -- nof_samples, mode calc
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, INTEGER(  0.0 * c_diag_wg_phase_unit), tb_clk);  -- phase offset in degrees
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER(c_subband_sp * c_wg_subband_freq_unit), tb_clk);  -- freq
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, INTEGER(REAL(c_ampl_sp) * c_wg_ampl_lsb), tb_clk);  -- ampl
+    
+    -- Read current BSN
+    mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO  0), tb_clk);
+    mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
+    proc_common_wait_some_cycles(tb_clk, 1);
+    
+    -- Write scheduler BSN to trigger start of WG at next block
+    v_bsn := TO_UINT(current_bsn_wg) + 2;
+    ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
+    v_bsn := c_bsn_start_wg;
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);  -- first write low then high part
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1,     0, tb_clk);  -- assume v_bsn < 2**31-1
+    
+    -- Wait for ADUH monitor to have filled with WG data
+    WAIT FOR c_subband_period*c_nof_taps;
+    WAIT FOR c_subband_period*2;
+
+    ----------------------------------------------------------------------------
+    -- WG data : read ADUH monitor buffer
+    ----------------------------------------------------------------------------
+    -- Wait for start of sync interval 
+    mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,                  -- read BSN low
+                            "UNSIGNED", rd_data, ">=", c_nof_block_per_sync*2,  -- this is the wait until condition
+                            c_subband_period, tb_clk);
+    
+    WAIT FOR c_subband_period;  -- ensure that one block of samples has filled the ADUH monitor buffer after the sync
+
+    -- Read via MM    
+    FOR I IN 0 TO c_mon_buffer_nof_words-1 LOOP
+      mmf_mm_bus_rd(c_mm_file_ram_aduh_mon, I, rd_data, tb_clk);
+      sp_samples(I) <= TO_SINT(rd_data(15 DOWNTO 0)); 
+    END LOOP;
+    
+    -- Play to have waveform in time to allow viewing as analogue in the Wave Window
+    FOR I IN 0 TO c_mon_buffer_nof_words-1 LOOP
+      proc_common_wait_some_cycles(ext_clk, 1);
+      sp_sample <= sp_samples(I);
+    END LOOP;
+ 
+    WAIT FOR c_subband_period*3;
+
+    ---------------------------------------------------------------------------
+    -- Read ADUH monitor power sum 
+    ---------------------------------------------------------------------------
+    -- Wait for start of sync interval
+    mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,                   -- read BSN low
+                            "UNSIGNED", rd_data, ">=", c_nof_block_per_sync*3,   -- this is the wait until condition
+                            c_subband_period, tb_clk);
+    
+    -- Read ADUH monitor power sum 
+    mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk);  -- read low part
+    sp_power_sum(31 DOWNTO 0) <= UNSIGNED(rd_data);
+    mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk);  -- read high part
+    sp_power_sum(63 DOWNTO 32) <= UNSIGNED(rd_data);
+    proc_common_wait_some_cycles(tb_clk, 1);
+
+    ---------------------------------------------------------------------------
+    -- Verification 
+    ---------------------------------------------------------------------------
+    -- Convert UNSIGNED sp_power_sum to REAL
+    v_sp_power_sum := REAL(REAL(TO_INTEGER(sp_power_sum(61 DOWNTO 30)))*REAL(2**30) + REAL(TO_INTEGER(sp_power_sum(29 DOWNTO 0)))); 
+
+    ASSERT v_sp_power_sum > c_lo_factor * c_exp_wg_power_sp REPORT "Wrong SP power for SP 0" SEVERITY ERROR;
+    ASSERT v_sp_power_sum < c_hi_factor * c_exp_wg_power_sp REPORT "Wrong SP power for SP 0" SEVERITY ERROR;
+
+    ---------------------------------------------------------------------------
+    -- End Simulation 
+    ---------------------------------------------------------------------------   
+    sim_done <= '1';
+    proc_common_wait_some_cycles(ext_clk, 100);
+    proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+    WAIT;
+  END PROCESS;
+  
+END tb;
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_icd.txt b/applications/lofar2/doc/prestudy/station2_sdp_icd.txt
index 679e720ba482e655210ac304238e9b524fc933c2..d51c651115fe9e44cc9973881fde89befc1524f2 100755
--- a/applications/lofar2/doc/prestudy/station2_sdp_icd.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_icd.txt
@@ -498,7 +498,267 @@ Do not support more than one block per packet, because for SST and BST the paylo
 
 Statistics packet fields format: See ICD SC-SDP in Polarion
 
+The ToD in SC and the ToD in SDPTR shall be within +-10 ms. This value is a compromise between using a measurable value, a feasible value with NTP and not adding too much timing margin between SC and SDP.
+
+
+Direct:
+
+Per memory mapped (MM) point in the register map of a PN on a UniBoard2:
+
+/unb[0:7]/pn[0:3]/mm/peripheral/field
+
+
+Composite:
+
+Per functional point per antenna band, where antenna band is Low Band (= SDP - LBAS) or High Band (= SDP - HBAS)
+
+Monitor and control of SDP
+
+The monitoring and control of the SDP Translator and of the SDP Firmware is done via the OPC-UA interface of the SDP Translator. The SDP Translator is central to entire SDP.
+
+
+The SDP Firmware is distirubuted
+
+List of products with M&C in SDP
+
+Path                Product name
+
+/sdptr              SDP Translator
+/band[0:1]/bsp      SDPFW Board Support Package
+/band[0:1]/general  SDPFW
+/band[0:1]/ait      SDPFW ADC Input and Timing
+/band[0:1]/fsub     SDPFW Subband Filterbank
+/band[0:1]/bf       SDPFW Beamformer
+/band[0:1]/ri       SDPFW Ring
+/band[0:1]/xc       SDPFW Subband Correlator
+/band[0:1]/tbuf     SDPFW Transient Buffer
+/band[0:1]/tdet     SDPFW Transient Detector
+
+
+List of control points per antenna band and per product in SDP
+
+Path               Point
+/sdptr             /sdp_info
+/band[0:1]/bsp     /pn_image
+/band[0:1]/general /sdp_info
+                   /data_flags
+                   /signal_input_range
+/band[0:1]/ait     /processing_enable
+                   /si_sample_delay
+                   /si_waveform_generator
+/band[0:1]/fsub    /pfir_coefficients
+                   /subband_weights
+                   /sst_select
+                   /sst_offload_destination
+                   /sst_offload_enable
+/band[0:1]/bf      /subband_select
+                   /weights_xx
+                   /weights_yy
+                   /bst_offload_destination
+                   /bst_offload_enable
+                   /beamlet_offload_destination
+                   /beamlet_offload_enable
+/band[0:1]/ri/
+/band[0:1]/xc/          
+/band[0:1]/tbuf/
+/band[0:1]/tdet/
+
+
+List of monitor points per antenna band and per product in SDP
+
+Path                Point
+/sdptr              /tr_info
+                    /tr_timing
+                    /tr_network
+/band[0:1]/bsp      /pn_info
+                    /pps_timing
+                    /mc_network
+/band[0:1]/general  /sdp_info
+/band[0:1]/ait      /sdp_status
+                    /si_timing
+                    /si_mean
+                    /si_sigma
+                    /si_data_buffer
+                    /si_histogram
+/band[0:1]/fsub     -                If sst_offload_enable = off, then the SST can be read via direct monitoring.
+/band[0:1]/bf       -                If bst_offload_enable = off, then the BST can be read via direct monitoring.
+/band[0:1]/ri/
+/band[0:1]/xc/
+/band[0:1]/tbuf/
+/band[0:1]/tdet/
+
+
+
+For the SDP Firmware the 
+
+/sdptr/
+    Control:
+    - sdp_info:
+      . station_id
+    Monitor:
+    - tr_info:
+      . software name and version
+      . temperature ? (or via EC2 ?)
+    - tr_timing:
+      . NTP status
+      . PPS status : Locked, not locked, unknown
+        - Not locked = NTP time at SDPTR does not coincide within +- 1 ms with PPS top of second at SDPFW
+        - Locked = NTP time at SDPTR is aligned within +- 1 ms with the PPS top of second at SDPFW → based on the offset_cnt information from the PPSH in one of the PN in the SDPHW / SDPFW
+        - Unknown when the PPS information in SDPFW is not stable or not available
+    - tr_network:
+      . SC-SDPTR link status at SDPTR : nof tx pkts, nof rx pkts, nof crc errors, nof retransmissions, nof timeouts
+      . SDPTR-SDPFW link status at SDPTR : nof tx pkts, nof rx pkts, nof crc errors, nof retransmissions, nof timeouts
+    
+    
+/band[0:1]/bsp/
+    Control for all allocated PN
+    - pn_image : design name
+    
+    Monitor per allocated PN
+    - pn_info : unb_hw_version, gn_id, rn_id, fw_image (design_name with date, time and revision stamp, design note), f_adc, fsub_type
+    - pn_regmap : mmap
+    - pps_timing :
+      . STF-SDPFW PPS status at SDPFW:
+        'not active' = measured PPS count >> f_adc = 200M and clipped at 2**28 - 1
+        'asynchronous' = measured PPS count != expected count -1, +0, or +1
+        'active' = measured PPS count = expected count -1, +0, or +1
+        'active and stable' → measured PPS count has been equal to expected count -1, +0, or +1 since last time it was monitored.
+    - eth1g :
+      . SDPTR-SDPFW link status at SDPFW : nof tx pkts, nof rx pkts, nof crc errors, nof retransmissions, nof timeouts
+
+band[0:1]/general
+    Control
+    - sdp_info: observation_id, nyquist_zone_index
+    - data_flags : beam repositioning flag, calibrated subbands flag
+    - signal_input_range : R_ant = (O_si, N_si) → this will allocate N_pn = N_si / S_pn PN starting with PN with rn_id = O_si / S_pn
+    
+    Both the offset and the amount are a multiple of S_pn = 12 signals inputs, because there are S_pn = 12 signal inputs per FPGA processing node (PN) in the SDP Hardware and because the PN are interconnected in a fixed sequence.
+    
+    Monitor per allocated PN
+    - sdp_info : f_adc, fsub_type
+    - eth10g
+    
+/band[0:1]/ait/    (AIT = adc input and timing)
+    Control:
+    - processing_enable : Start, stop
+    - si_sample_delay, Sample delay buffer : (unit16)ait_sample_delay[R_ant]
+    - si_waveform_generator (WG) : start at BSN, stop, freq[R_ant], ampl[R_ant], phs[R_ant]
+    
+    Monitor:
+    - sdp_status : 'stopped', 'running' or running and stable' → based on read BSN from BSN source being equal and incrementing correctly at all PN
+    - si_timing : (enum)ait_timing[R_ant]
+      'not active' = no data
+      'active' = there is data
+      'active and stable and not aligned' = there is a stable flow of data since last time it was monitored, but the recovered LMFC is not aligned with the local FPGA_SYSREF
+      'aligned' = there is a stable flow of data and it is aligned
+      'aligned and stable' = there is a stable flow of data and it is aligned since the last time it was monitored    
+
+    Monitor on request:
+    - si_mean : (float)ait_mean[R_ant]
+    - si_sigma : (float)ait_sigma[R_ant]
+    - si_data_buffer : (sint16)ait_data_buffer[R_ant][N]  (N = 1k samples)
+    - si_histogram : (uint32)ait_histogram[R_ant][N]  (N = 1k bins)
+
+/band[0:1]/fsub/  (Fsub = subband filterbank)
+    Control:
+    - pfir_coefficients: FIR filter coefficients: (sint16)pfir_coefficients[N_taps*N_fft]
+    - subband_weights : (cint16)subband_weights[R_ant][N_sub]
+    - sst_input_select : (bool)sst_input_select, select calibrated or not calibrated for SST
+    - sst_offload_destination : SST UDP offload header
+      . Destination : (tuple)sst_offload_destination = (MAC address, IPv4 address, UDP port)
+    - sst_offload_enable : SST UDP offload : (bool)sst_offload_enable = on, off
+
+    Monitor: None, if sst_offload = off, then the SST can be read via direct monitoring.
+
+/band[0:1]/bf/ (BF = beamformer)
+    Control: 
+    - Subband select per beam: (uint16)beamlet_subband_select[N_beamlets]
+    - Beamformer weights for X polarization beams: (cint16)beamlet_weights_xx[N_ant][N_beamlets]
+    - Beamformer weights for Y polarization beams: (cint16)beamlet_weights_yy[N_ant][N_beamlets]
+    - BST UDP offload header
+      . Destination : (tuple)bst_offload_destination[N_beamsets] = (MAC address, IPv4 address, UDP port)
+    - BST UDP offload : (bool)bst_offload[N_beamsets] = on, off
+
+    Monitor: None, if bst_offload = off, then the BST can be read via direct monitoring.
+
+/band[0:1]/ri/ (RI = ring)
+
+/band[0:1]/xc/ (XC = subband correlator)
+                         
+/band[0:1]/tbuf/ (Tbuf = Transient Buffer)
+
+/band[0:1]/tdet/ (Tdet = Transient Detector)
+
+
+De SDP Translator is valt ook onder beheer EC2.
+
+
+
+###################################################################################################
+# L3 ICD 11423 SDPTR - SDPFW
+
+ToD
+The SDP maintains timing using the PPS and the sample clock. Hence SDP knows about seconds, but it does not know the time of day (ToD) since 1970 at the PPS. After power up SDP needs to get the ToD information from SC to be able to timestamp SDP output data. Both SC and SDP know the PPS grid. The SC has to provide the ToD information at PPS in one PPS interval and then SDP will apply that ToD in the next PPS interval. The ToD at the PPS is defined at the block sequence number (BSN) grid, using initial BSN and a BSN offset [Does SC care about BSN. IMHO that's SDP internal.] [AD-4]. The SC only has to provide the ToD once, because after that SDP can maintain the ToD by counting PPS pulses and sample clock periods. The SDP provides a monitoring point that reports the time since last PPS. [Do you really mean time since last PPS? What's the purpose? Assuming time distribution is done properly within the station, then all subsystem will receive the PPS at the same time. AFAIK, SC doesn't need to align with the PPS. Maybe you're referring to the ToD when the last PPS occurred? That could indeed be useful to discover inconsistencies between SC and SDP.] The SC can read this monitoring point to check whether is own PPS is aligned to the PPS in SDP.
+
+PPS monitoring
+The monitoring of the status of the PPS in the SDP Firmware reveals: 
+
+    whether the PPS period is correct and stable. This allows SC to monitor whether processing by SDP is possible. If the period is wrong or not stable, then this indicates an issue between the STF and SDP. The stable interval is defined by the time since between monitoring requests by SC of the PPS period. [We have to be careful here, not to make the same mistakes as in APERTIF, where the misalignment detection generated a lot of false positives. What problem are we trying to solve here? Only when we've answered that question, it's time to ask ourselves what is the best solution?]
+    the number of sample clock cycles since last PPS, upon reception of the monitoring message. This allows SC to monitor the synchronisation between SC and SD
+    
+BSN timing grid
+The ToD information defines the BSN timing grid and shall consist of [AD-3]: [Again, isn't this all SDP internals? AFAIC, SC provides the ToD, only. Whatever SDP does internally with BSN is none of SC's business.]
+
+    an initial BSN that counts subband periods T_sub,
+    a BSN offset in ADC sample periods T_adc relative to the initial PPS 
+
+
+SDPTR requirements:
+
+    SC-SDP synchronisation. The Time of Day (ToD) in SC and the PPS in SDP shall be synchronous within a margin of ±100 ms, to ensure that real-time [There is no real-time communication.] M&C communication that starts in a certain PPS interval can also complete in that PPS interval.
+    
+    PPS monitoring. SC shall monitor the status of the PPS in the SDP Firmware, [Like I said before, this is IMHO the wrong (APERTIF) approach. Do we really want to go that route again?] as listed in LOFAR2-8852 - PPS monitoring.
+    
+    Time of Day (ToD) information at PPS. SC shall provide the initial ToD information to SDP within the pulse per second (PPS) interval that precedes the PPS that corresponds to that initial ToD. For subsequent PPS intervals the SDP maintains the ToD information by itself.
+    
+    Block Sequence Number (BSN) timing grid. SC shall provide the ToD information as defined in LOFAR2-8853 - BSN timing grid.
+    
+    Block Sequence Number (BSN) monitoring. The SC shall monitor the BSN monitoring points in the SDP Firmware to monitor whether the processing in SDP is synchronous.
+    
+    SDP processing start and restart.The SC shall start the SDP processing by providing the ToD information to SDP. The SDP processing can be started or restarted at any PPS (i.e. no need to wait for an even second like in LOFAR1).
+
+SDPFW requirements:
+
+    SC-SDP synchronisation. The Timeof Day (ToD) in SC and the PPS in SDP shall be synchronous within a margin of ±100 ms, to ensure that real-time M&C communication that starts in a certain PPS interval can also complete in that PPS interval.
+    
+    PPS monitor. The SDP Firmware shall report the status of the PPS upon request, as listed in LOFAR2-8852 - PPS monitoring.
+    
+    Time of Day (ToD) information at PPS. SDP Firmware shall apply the received ToD information at the next pulse per second (PPS). For subsequent PPS intervals the SDP Firmware shall maintain the ToD information by counting sample clock cycles.
+    
+    Block Sequence Number (BSN) timing grid. [I'm not sure why this should be in the ICD. Like I said, BSN is IMHO SDP internal.] SDP shall apply the ToD information as defined in LOFAR2-8853 - BSN timing grid.
+    
+    Block Sequence Number (BSN) monitor. The SDP Firmware shall provide monitoring points that show the status of the timing within a processing node (PN) and the status of the timing alignment between PN within SDP.
+    
+    SDP processing start and restart.The SDP shall start the SDP processing at the next PPS, when it has received the ToD information from SC. The SDP processing can be started or restarted at any PPS.
+    
+    
+I.011211.SDPTR.SDPFW d.7, Data - Synchronous control using time activated control
+In LOFAR1LOFAR1: RSP driver moet 2 x een setting sturen naar het RSP board, vanwege het per seconde swappen. Dit moeten we voorkomen in LOFAR2.
+Time activated control is control that takes effect in the SDP Firmware at a scheduled instant. The scheduled instant uses the block sequence number (BSN) grid [AD-4], so it is not restricted to the seconds grid. Time activated control implies that the SDP Firmware uses a dual page register to store the control data. One page can accept new control data, while the control data in the other page is being used. At a trigger the pages swap or shift, dependent on whether the register consist of RAM or logic. In LOFAR1 the dual page registers swap at the PPS, independent of whether the RSP driver had updated the setting. This causes that the RSP driver has to set the same setting twice in two successive PPS intervals, to avoid that the page swap of a RAM register results in using old page values. For LOFAR2.0 this is avoided by letting the SC control when the register in SDP should swap, instead of at any PPS. Therefore the time activated control in LOFAR2.0 uses a trigger that is scheduled by SC [I don't think I agree with that approach. Unless I completely misunderstand the issue here, but why should SC have to ensure SDP's internal consistency?!?! This definitely needs to be discussed.] instead of by the PPS. The scheduled instant for the trigger is typically in the future. If the scheduled instant is in the past, then SDP will not do the page swap. If the scheduled instant is at BSN = 0 then SDP will do the page swap immediately. The trigger can be rescheduled by SC as long as its time instant has not yet past. SC has to provide a trigger instant per page swap, otherwise the pages do not swap. Hence SC has full control over when and how often time activated control is applied.
+Linked Work Items	has parent: LOFAR2-8812 - Station Control (L3-SC) - SDP Translator (L4-SDPTR)
+[Create Link] List of time-activated control pointsThe time activated control is used for controlling:
+
+    starting of the subband correlator,
+    starting the waveform generators
+
+SC requirements:
 
+    Time activated control. For time activated control the SC shall provide the control data and a timestamp. The timestamp schedules an instant at the BSN grid. The SDP Firmware shall activate the control at that timestamp. The SC shall use time-activated control for the control points listed in LOFAR2-8854 - List of time-activated control points.
+
+SDP requirements:
+
+    Time activated control. For time activated control the SC shall provide the control data and a timestamp. The timestamp schedules an instant at the BSN grid. The SDP Firmware shall activate the control at that timestamp. The SDP shall use time-activated control for the control points listed in LOFAR2-8854 - List of time-activated control points.
+    
 ###################################################################################################
 # L2 ICD 11207 RCU2S-SDP
 
diff --git a/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl b/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
index f554b7b6e3c7d3546c61bc6268128486dd1f7798..037c4d4c462c599f32268bc1e04c319c71d82015 100644
--- a/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+++ b/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
@@ -19,7 +19,7 @@ set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to PPS
 
 # IO Standard Assignments from Gijs (excluding memory)
 set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_CLK
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ETH_CLK
+#set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ETH_CLK
 set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[0]
 set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[0](n)"
 set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[1]
diff --git a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
index 5dccd3774f52fe485f124ef9e369fb69903a5769..d9e35c4adaac2c6b54d33c8506d25733219adee2 100644
--- a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+++ b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
@@ -55,10 +55,10 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE ON
 set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
 
 set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+#set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+#set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+#set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+#set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
 
 set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 1.8V
 set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
diff --git a/libraries/dsp/st/hdllib.cfg b/libraries/dsp/st/hdllib.cfg
index 21443d39f3629e98383ef0678cc9191f97d8bb4b..3617a5976a7da4b76d245c3cbcd1c1cfdcfb6d71 100644
--- a/libraries/dsp/st/hdllib.cfg
+++ b/libraries/dsp/st/hdllib.cfg
@@ -21,6 +21,7 @@ test_bench_files =
     tb/vhdl/tb_mmf_st_sst.vhd
     tb/vhdl/tb_st_histogram.vhd
     tb/vhdl/tb_mms_st_histogram.vhd
+    tb/vhdl/tb_tb_st_histogram.vhd
 
 regression_test_vhdl = 
     tb/vhdl/tb_st_acc.vhd 
diff --git a/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd b/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd
index 372f5187091d077d31a483556dbfb94ac2b4360d..8472efc40742fd61e77675a888cf84c742b56def 100644
--- a/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd
@@ -26,7 +26,7 @@
 --   mms_st_histogram couples the st_histogram component which works entirely
 --   in the dp clock domain through st_histogram_reg that handles the cross
 --   domain conversion to the MM bus.
---
+--   
 --
 --             --------------------------------------
 --             | mms_st_histogram                   |
diff --git a/libraries/dsp/st/src/vhdl/st_histogram.vhd b/libraries/dsp/st/src/vhdl/st_histogram.vhd
index 4177fdd6c43189ed20f8075d5abe46372fae8057..13b57e0ee13a3d5d2d04a7702d4a33686c2f0c31 100644
--- a/libraries/dsp/st/src/vhdl/st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/st_histogram.vhd
@@ -26,7 +26,7 @@
 -- Description: 
 --   The histogram component separates it's input samples in counter bins based
 --   on the value of the MSbits of the input. These bins are adresses on a RAM
---   block that is swapped with another RAM block at every sync pulse plus 2 
+--   block that is swapped with another RAM block at every sync pulse plus 3 
 --   cycles. While one RAM block is used to count the input samples, the other
 --   is read by the MM bus through st_histogram_reg.
 --
@@ -46,6 +46,14 @@
 -- RAM is swapped after every sync both RAM blocks need to use the dp_clk.
 -- If the MM bus needs to acces the data in a RAM block it has to acces it
 -- through st_histogram_reg as the mm_clk can't be used.
+--
+-- The design is basically devided in the following blocks of code:
+-- . Assign inputs of RAM
+--   . Bin reader
+--   . Bin Writer
+--   . Bin Arbiter
+-- . RAM selector & Dual swapped RAM instances
+-- . Connect interface to DUAL swapped RAM, read out histogram statistics
 -- 
 -- Remarks:
 -- . Because the values of the generics g_nof_bins depends on g_in_data_w
@@ -54,9 +62,10 @@
 --   If exceeded the simulator will throw fatal error ("...Port length (#) does
 --   not match actual length (#)...")
 --
--- . when an adress is determined it takes 1 cycle to receive it's value and
+-- . when an adress is determined it takes 2 cycles to receive it's value and
 --   another cycle before the calculated value can be written into that RAM
---   adress. There is also the limitation of not being able to read and write 
+--   adress (1st cycle: address; 3rd cycle: data available; 5th cycle: write 
+--   data). There is also the limitation of not being able to read and write 
 --   on the same adress at the same time. These limitations cause the following
 --   complications in the implementation:
 --   . repeating samples of the same adress have to be counted first till 
@@ -64,10 +73,12 @@
 --     further consecutive samples and have the read/write limitation)
 --   . If adresses are toggling at every cycle (e.g. adress 0; 1; 0; 1) you
 --     have to remember the data to be written and increment it as you have the
---     read/write limitation and writing takes priority in this case
---   . When a sync signal appears the RAM has to be swapped 2 cycles later so 
---     the first 2 cycles may not be read from the old RAM block 
--- 
+--     read/write limitation (missing samples) and writing takes priority 
+--     in this case
+--   . When a sync signal appears the RAM has to be swapped 4 cycles later so 
+--     the first 3 cycles may/can not ask a read from the old RAM block (the 
+--     read_enable takes one cycle hence the difference of 3 against 4 cycles) 
+--   
 -------------------------------------------------------------------------------
 
 LIBRARY IEEE, common_lib, mm_lib, technology_lib, dp_lib;
@@ -79,98 +90,140 @@ USE technology_lib.technology_select_pkg.ALL;
 
 ENTITY st_histogram IS
   GENERIC (
-    g_in_data_w     : NATURAL := 14;   -- >= 9 when g_nof_bins is 512; (max. c_dp_stream_data_w =768)         <-- maybe just g_data_w ??
-    g_nof_bins      : NATURAL := 512;  -- is a power of 2 and g_nof_bins <= c_data_span; max. 512
-    g_nof_data      : NATURAL;         -- 
-    g_str           : STRING  := "freq.density"  -- to select output to MM bus ("frequency" or "freq.density")
+    g_in_data_w         : NATURAL := 14;   -- >= 9 when g_nof_bins is 512; (max. c_dp_stream_data_w =768)         <-- maybe just g_data_w ??
+    g_nof_bins          : NATURAL := 512;  -- is a power of 2 and g_nof_bins <= c_data_span; max. 512
+    g_nof_data          : NATURAL;         -- 
+    g_str               : STRING  := "freq.density";  -- to select output to MM bus ("frequency" or "freq.density")
+    g_ram_miso_sim_mode : BOOLEAN := FALSE -- when TRUE the ram_miso bus will get a copy of the data written into the RAM.
   );                
   PORT (            
-    dp_rst          : IN  STD_LOGIC;
-    dp_clk          : IN  STD_LOGIC;
+    dp_rst              : IN  STD_LOGIC;
+    dp_clk              : IN  STD_LOGIC;
                     
     -- Streaming    
-    snk_in      : IN  t_dp_sosi;
+    snk_in              : IN  t_dp_sosi;
     
     -- DP clocked memory bus
-    sla_in_ram_mosi : IN  t_mem_mosi;  -- Beware, works in dp clock domain !
-    sla_out_ram_miso : OUT t_mem_miso   --  ''                              !
+    sla_in_ram_mosi     : IN  t_mem_mosi;  -- Beware, works in dp clock domain !
+    sla_out_ram_miso    : OUT t_mem_miso;   --  ''                              !
 --    ram_mosi : IN  t_mem_mosi;  -- Beware, works in dp clock domain !
 --    ram_miso : OUT t_mem_miso   --  ''                              !
+    -- Debug bus
+    dbg_ram_miso        : OUT t_mem_miso
   );
 END st_histogram;
 
 
 ARCHITECTURE rtl OF st_histogram IS
 
-  CONSTANT c_data_span    : NATURAL  := pow2(g_in_data_w);      -- any use?
-  CONSTANT c_bin_w        : NATURAL  := ceil_log2(g_nof_data);  -- any use?
-  CONSTANT c_clear        : NATURAL  := g_nof_data - g_nof_bins;
-  CONSTANT c_adr_w        : NATURAL  := ceil_log2(g_nof_bins);
-  CONSTANT c_adr_low_calc : INTEGER  := g_in_data_w-c_adr_w;          -- Calculation might yield a negative number
-  CONSTANT c_adr_low      : NATURAL  := largest(0, c_adr_low_calc);   -- Override any negative value of c_adr_low_calc
-  
+--  CONSTANT c_data_span    : NATURAL  := pow2(g_in_data_w);      -- any use?
+--  CONSTANT c_bin_w        : NATURAL  := ceil_log2(g_nof_data);  -- any use?
+  CONSTANT c_clear        : NATURAL := g_nof_data - g_nof_bins;
+  CONSTANT c_adr_w        : NATURAL := ceil_log2(g_nof_bins);
+  CONSTANT c_adr_low_calc : INTEGER := g_in_data_w-c_adr_w;          -- Calculation might yield a negative number
+  CONSTANT c_adr_low      : NATURAL := largest(0, c_adr_low_calc);   -- Override any negative value of c_adr_low_calc
   CONSTANT c_ram          : t_c_mem := (latency  => 1,
                                         adr_w    => c_adr_w,          -- 9 bits needed to adress/select 512 adresses
                                         dat_w    => c_word_w,         -- 32bit, def. in common_pkg; >= c_bin_w
                                         nof_dat  => g_nof_bins,       -- 512 adresses with 32 bit words, so 512
                                         init_sl  => '0');             -- MM side : sla_in, sla_out
+                                 
+--  CONSTANT c_mem_miso_setting     : t_mem_miso := (rddata => mem_miso_init,  -- c_mem_miso_rst; -- limit to 32 bit 
+--                                                   rdval => '0',
+--                                                   waitrequest => '0' );
   
-  SIGNAL dp_pipeline_src_out_p : t_dp_sosi;
-  SIGNAL dp_pipeline_src_out_pp : t_dp_sosi;
-  
-  SIGNAL rd_adr_cnt         : NATURAL  := 1;
-  SIGNAL nxt_rd_adr_cnt     : NATURAL;
-  SIGNAL prev_rd_adr        : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
-  
-  -- Toggle implementation signals
-  SIGNAL prev_same_r_w_adr : STD_LOGIC  := '0';
-  SIGNAL same_r_w_adr      : STD_LOGIC  := '0';
-  SIGNAL nxt_same_r_w_adr  : STD_LOGIC  := '0';
+--  SIGNAL mem_miso_init    : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS => '0');
+
+  SIGNAL snk_in_p                : t_dp_sosi;
+  SIGNAL snk_in_pp               : t_dp_sosi;
+  SIGNAL snk_in_pppp             : t_dp_sosi;
+  
+  SIGNAL bin_reader_mosi         : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL prev_bin_reader_mosi    : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL bin_reader_mosi_pp      : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL bin_reader_mosi_ppp     : t_mem_mosi := c_mem_mosi_rst;
+
+  SIGNAL nxt_bin_writer_mosi     : t_mem_mosi;
+  SIGNAL bin_writer_mosi         : t_mem_mosi;
+
+  SIGNAL nxt_bin_arbiter_wr_mosi : t_mem_mosi;
+  SIGNAL bin_arbiter_wr_mosi     : t_mem_mosi;
+
+  SIGNAL nxt_bin_arbiter_rd_mosi : t_mem_mosi;
+  SIGNAL bin_arbiter_rd_mosi     : t_mem_mosi;
+
+  SIGNAL bin_arbiter_rd_miso     : t_mem_miso := c_mem_miso_rst;
+  SIGNAL bin_reader_rd_miso      : t_mem_miso := c_mem_miso_rst;
+  SIGNAL common_ram_r_w_miso   : t_mem_miso := c_mem_miso_rst;
+  
+  SIGNAL init_phase              : STD_LOGIC := '1';
+  SIGNAL nxt_init_phase          : STD_LOGIC;
+                                
+  SIGNAL rd_cnt_allowed          : STD_LOGIC := '0';
+  SIGNAL rd_cnt_allowed_pp       : STD_LOGIC := '0';
+  
+  SIGNAL toggle_detect           : STD_LOGIC := '0';
+  SIGNAL toggle_detect_pp        : STD_LOGIC;
+  SIGNAL toggle_detect_false     : STD_LOGIC := '1';
+  SIGNAL nxt_toggle_detect_false : STD_LOGIC;
+  
+  SIGNAL nxt_prev_wrdata         : NATURAL;
+  SIGNAL prev_wrdata             : NATURAL;
+  SIGNAL prev_prev_wrdata        : NATURAL;
+  SIGNAL prev_prev_prev_wrdata   : NATURAL;
+  
+  SIGNAL sync_detect             : STD_LOGIC := '0';
+  SIGNAL sync_detect_pp          : STD_LOGIC;
+                                 
+  SIGNAL same_r_w_address        : STD_LOGIC;
+  SIGNAL same_r_w_address_pp     : STD_LOGIC;
+  
+  --debug signals
+  SIGNAL dbg_state_string        : STRING(1 TO 3) := "   ";
+  SIGNAL dbg_snk_data            : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0);
 
   
   SIGNAL ram_pointer       : STD_LOGIC  := '0';
   SIGNAL cycle_cnt         : NATURAL    :=  0 ;
   SIGNAL nxt_cycle_cnt     : NATURAL    :=  0 ;
-  SIGNAL wr_en           : STD_LOGIC  := '0';
-  SIGNAL nxt_wr_en       : STD_LOGIC;
-  SIGNAL wr_dat          : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
-  SIGNAL nxt_wr_dat      : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
-  SIGNAL wr_adr             : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
-  SIGNAL rd_adr             : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
-  SIGNAL rd_en           : STD_LOGIC  := '0';
-  SIGNAL rd_dat          : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
-  SIGNAL rd_val          : STD_LOGIC;
+--  SIGNAL wr_en           : STD_LOGIC  := '0';
+--  SIGNAL nxt_wr_en       : STD_LOGIC;
+--  SIGNAL wr_dat          : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
+--  SIGNAL nxt_wr_dat      : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
+--  SIGNAL wr_adr             : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
+--  SIGNAL rd_adr             : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
+--  SIGNAL rd_en           : STD_LOGIC  := '0';
+--  SIGNAL rd_dat          : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
+--  SIGNAL rd_val          : STD_LOGIC;
   
   SIGNAL mm_adr_cnt        : NATURAL   :=  0 ;
   SIGNAL mm_adr_illegal    : STD_LOGIC := '0';
   SIGNAL mm_adr_illegal_pp : STD_LOGIC := '0';
   
   
-  SIGNAL ram_0_wr_en    : STD_LOGIC;
---  SIGNAL ram_0_wr_en_b    : STD_LOGIC  := '0'; -- pointer=1, temp'0'
-  SIGNAL ram_0_wr_dat   : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
---  SIGNAL ram_0_wr_dat_b   : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0) := (OTHERS =>'0'); -- pointer=1, temp'0'
+  SIGNAL ram_0_wr_en       : STD_LOGIC;
+  SIGNAL ram_0_wr_dat      : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
   SIGNAL ram_0_wr_adr      : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
   SIGNAL ram_0_rd_adr      : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
-  SIGNAL ram_0_rd_en    : STD_LOGIC;
-  SIGNAL ram_0_rd_dat   : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
-  SIGNAL ram_0_rd_val   : STD_LOGIC;
-  
-  SIGNAL ram_1_wr_en    : STD_LOGIC;
-  SIGNAL ram_1_wr_dat   : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
+  SIGNAL ram_0_rd_en       : STD_LOGIC;
+  SIGNAL ram_0_rd_dat      : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
+  SIGNAL ram_0_rd_val      : STD_LOGIC;
+                          
+  SIGNAL ram_1_wr_en       : STD_LOGIC;
+  SIGNAL ram_1_wr_dat      : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
   SIGNAL ram_1_wr_adr      : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
   SIGNAL ram_1_rd_adr      : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
-  SIGNAL ram_1_rd_en    : STD_LOGIC;
-  SIGNAL ram_1_rd_dat   : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
-  SIGNAL ram_1_rd_val   : STD_LOGIC;
-  
-  SIGNAL ram_out_wr_en    : STD_LOGIC;
-  SIGNAL ram_out_wr_dat   : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
-  SIGNAL ram_out_wr_adr   : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
-  SIGNAL ram_out_rd_adr   : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
-  SIGNAL ram_out_rd_en    : STD_LOGIC;
-  SIGNAL ram_out_rd_dat   : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
-  SIGNAL ram_out_rd_val   : STD_LOGIC;
+  SIGNAL ram_1_rd_en       : STD_LOGIC;
+  SIGNAL ram_1_rd_dat      : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
+  SIGNAL ram_1_rd_val      : STD_LOGIC;
+  
+  SIGNAL ram_out_wr_en     : STD_LOGIC;
+  SIGNAL ram_out_wr_dat    : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
+  SIGNAL ram_out_wr_adr    : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
+  SIGNAL ram_out_rd_adr    : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
+  SIGNAL ram_out_rd_en     : STD_LOGIC;
+  SIGNAL ram_out_rd_dat    : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
+  SIGNAL ram_out_rd_val    : STD_LOGIC;
   
   SIGNAL prev_ram_out_wr_adr  : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
   SIGNAL ram_out_same_w_r_adr : STD_LOGIC;
@@ -183,30 +236,57 @@ BEGIN
   ASSERT c_adr_low_calc>0 REPORT "ceil_log2(g_nof_bins) is as large as g_in_data_w, don't increase g_nof_bins" SEVERITY WARNING;
   
   -----------------------------------------------------------------------------
-  -- Assign inputs of RAM:
+  -- Assign inputs of RAM:                                                                  <-- use parts of description for bin_writer
   -- . Determine address based on input data
   -- . Compare adress with the two previous adresses and if:
   --   . it is the same as the last adress increase a counter
-  --   . it is the same as 2 cycles back but not the last copy the data to be 
-  --     written directly into the counter instead of trying to read (ask) it 
-  --     back from RAM at the same clock cycle (which is impossible)
-  --   . it is not the same enable the nxt_wr_dat data to be written
-  --     at the next cycle by making nxt_wr_en high
+  --   . it is the same as 2 cycles back but not the last copy the data to be  
+  --     written directly into a local counter instead of trying to read (ask)
+  --     it back from RAM at the same clock cycle (which is impossible)
+  --   . it is not the same enable the nxt_wr_dat data to be written           .
+  --     at the next cycle by making nxt_wr_en high                            .
   -- . Write the wr_dat data to the RAM
   -- . At the snk_in.sync pulse:
-  --   . let first 2 cycles start counting from 0 again
-  --   . (plus 2 cycles) let counting depend on values in RAM (which should
+  --   . let first 3 cycles start counting from 0 again
+  --   . (plus 3 cycles) let counting depend on values in RAM (which should
   --     be 0)
   -- . Restart or pause counting when a snk_in.valid = '0' appears:
   --   . pause when adress is the same as the previous adress
   --   . restart from 0 when adress is not the same as previous adress
   --   . restart from 0 when also a sync appears
+  --
+  --
+  -- . in  : snk_in                (latency: 0)
+  --       : common_ram_r_w_miso   (latency: 2)
+  -- . out : snk_in_pppp.sync      (latency: 4)
+  --       : bin_arbiter_wr_mosi   (latency: 4)
+  --       : bin_arbiter_rd_mosi   (latency: 1)
   -- 
-  -- input: snk_in; rd_dat; rd_val
-  -- output: wr_adr; rd_adr; wr_en; rd_en; wr_dat; 
   ----------------------------------------------------------------------------
-
-  -- cycles after sync
+  
+  -----------------------------------------------------------------------------
+  -- Bin reader: Convert snk_in data to bin_reader_mosi with read request 
+  --             and generate signals for detection of problems in the 
+  --             consecutive data.
+  -- . in  : snk_in               (latency: 0)
+  --       : bin_arbiter_rd_miso  (latency: 2)
+  -- . out : init_phase           (latency: 0 ?
+  --       : bin_reader_mosi      (latency: 0)
+  --       : prev_bin_reader_mosi (latency: 1)
+  --       : bin_reader_mosi_pp   (latency: 2)
+  --       : bin_reader_mosi_ppp  (latency: 3)
+  --       : bin_reader_rd_miso   (latency: 2)
+  --       : rd_cnt_allowed_pp    (latency: 2)
+  --       : same_r_w_address_pp  (latency: 2)
+  --       : toggle_detect_pp     (latency: 2)
+  --       : sync_detect          (latency: 0)
+  --       : sync_detect_pp       (latency: 2)
+  -----------------------------------------------------------------------------
+  bin_reader_mosi.rd                          <= snk_in.valid; -- when 1, count allowed
+  bin_reader_mosi.address(c_adr_w-1 DOWNTO 0) <= snk_in.data(g_in_data_w-1 DOWNTO c_adr_low); 
+  bin_reader_rd_miso                          <= bin_arbiter_rd_miso;
+  
+  --snk_in pipeline; Enable sync and valid comparisons
   u_dp_pipeline_snk_in_1_cycle : ENTITY dp_lib.dp_pipeline
   GENERIC MAP (
     g_pipeline   => 1  -- 0 for wires, > 0 for registers, 
@@ -215,46 +295,96 @@ BEGIN
     rst          => dp_rst,
     clk          => dp_clk,
     snk_in       => snk_in,
-    src_out      => dp_pipeline_src_out_p
+    src_out      => snk_in_p
   );
   
-  p_bin_cnt_switch : PROCESS(snk_in) IS -- misses g_nof_bins ??
+--  init_phase <= '0' WHEN snk_in_p.sync = '1'; -- ELSE will be impossible since the init_phase may only be triggered once on the first sync
+  nxt_init_phase <= '0' WHEN snk_in.sync='1' ELSE init_phase;
+  
+  p_init_phase : PROCESS(dp_clk, dp_rst)
   BEGIN
-    rd_adr <= (OTHERS =>'0');
-    IF g_nof_bins>1 THEN
-      rd_adr <= snk_in.data(g_in_data_w-1 DOWNTO c_adr_low);-- WHEN snk_in.valid='1' ELSE (OTHERS =>'0'); -- AND dp_rst='0';
+    IF dp_rst = '1' THEN
+      init_phase          <= '1';
+      toggle_detect_false <= '1';
+    ELSIF RISING_EDGE(dp_clk) THEN
+      init_phase          <= nxt_init_phase;
+      toggle_detect_false <= nxt_toggle_detect_false;
     END IF;
   END PROCESS;
   
-  -- Pipelined to compare previous rd_adr against current 
-  u_common_pipeline_adr_cnt : ENTITY common_lib.common_pipeline --rename to u_common_pipeline_rd_adr
+  -- Enable sync comparisons
+  u_dp_pipeline_snk_in_2_cycle : ENTITY dp_lib.dp_pipeline
+  GENERIC MAP (
+    g_pipeline   => 2  -- 0 for wires, > 0 for registers, 
+  )
+  PORT MAP (
+    rst          => dp_rst,
+    clk          => dp_clk,
+    snk_in       => snk_in,
+    src_out      => snk_in_pp
+  );
+  
+  -- Enable switching the ram_pointer
+  u_dp_pipeline_snk_in_4_cycle : ENTITY dp_lib.dp_pipeline
+  GENERIC MAP (
+    g_pipeline   => 4  -- 0 for wires, > 0 for registers, 
+  )
+  PORT MAP (
+    rst          => dp_rst,
+    clk          => dp_clk,
+    snk_in       => snk_in,
+    src_out      => snk_in_pppp
+  );
+  
+  dbg_snk_data <= snk_in_pp.data(g_in_data_w-1 DOWNTO 0);
+  
+--  toggle_detect_false <= '0' WHEN snk_in_pp.sync = '1'; -- ELSE will be impossible since the toggle_detect_false may only be triggered once on the first sync
+  nxt_toggle_detect_false <= '0' WHEN snk_in_p.sync='1' ELSE toggle_detect_false;
+  sync_detect <= snk_in.valid WHEN (snk_in.sync='1' OR snk_in_p.sync='1' OR snk_in_pp.sync='1') ELSE '0'; -- @sync, first 3 cycles would try to read from the wrong (old) RAM block, detect this problem
+  
+  -- Line up to p_nxt_bin_writer_mosi process  
+  u_common_pipeline_sl_sync_detect_2_cycle : ENTITY common_lib.common_pipeline_sl
+  GENERIC MAP(
+    g_pipeline       => 2 -- 0 for wires, > 0 for registers, 
+  )
+  PORT MAP (
+    clk     => dp_clk,
+    in_dat  => sync_detect,
+    out_dat => sync_detect_pp
+  );
+  
+  -- Enable adress comparisons 1 cycle back  
+  -- Skip unvalid data with trigger bin_reader_mosi.rd to make comparisons between unvalid-data-seperated data possible.
+  u_common_pipeline_bin_reader_mosi_1_cycle : ENTITY common_lib.common_pipeline
   GENERIC MAP (
     g_representation => "UNSIGNED", --orig. signed
     g_pipeline       => 1,
-    g_in_dat_w       => c_adr_w,
+    g_in_dat_w       => c_adr_w, -- c_mem_address_w
     g_out_dat_w      => c_adr_w
   )
   PORT MAP (
     clk     => dp_clk,
-    clken   => '1',
-    in_dat  => STD_LOGIC_VECTOR(rd_adr),
-    out_dat => prev_rd_adr
+    clken   => bin_reader_mosi.rd, -- '1',
+    in_dat  => STD_LOGIC_VECTOR(bin_reader_mosi.address(c_adr_w-1 DOWNTO 0)),
+    out_dat => prev_bin_reader_mosi.address(c_adr_w-1 DOWNTO 0)
   );
   
-  p_nxt_wr_en : PROCESS(prev_rd_adr, rd_adr, snk_in.sync) IS -- misses g_nof_bins ??
-  BEGIN
-    nxt_wr_en <= '0';
-    IF rd_adr /= prev_rd_adr THEN
-      nxt_wr_en <= '1';
-    ELSIF snk_in.sync = '1' AND g_nof_bins = 1 THEN
-      nxt_wr_en <= '1';
-    ELSIF snk_in.sync = '1' THEN
-      nxt_wr_en <= '1';
-    END IF;
-  END PROCESS;
+  -- Enable adress comparisons 2 cycles back
+  u_common_pipeline_bin_reader_mosi_2_cycle : ENTITY common_lib.common_pipeline
+  GENERIC MAP (
+    g_representation => "UNSIGNED", --orig. signed
+    g_pipeline       => 1,
+    g_in_dat_w       => c_adr_w,
+    g_out_dat_w      => c_adr_w
+  )
+  PORT MAP (
+    clk     => dp_clk,
+    in_dat  => STD_LOGIC_VECTOR(prev_bin_reader_mosi.address(c_adr_w-1 DOWNTO 0)),
+    out_dat => bin_reader_mosi_pp.address(c_adr_w-1 DOWNTO 0)
+  );
   
-  -- requested data on adress can be written back 2 cycles later
-  u_common_pipeline_adr : ENTITY common_lib.common_pipeline
+  -- Enable adress comparisons 3 cycles back
+  u_common_pipeline_bin_reader_mosi_3_cycle : ENTITY common_lib.common_pipeline
   GENERIC MAP (
     g_representation => "UNSIGNED", --orig. signed
     g_pipeline       => 2,
@@ -263,149 +393,219 @@ BEGIN
   )
   PORT MAP (
     clk     => dp_clk,
-    clken   => '1',
-    in_dat  => STD_LOGIC_VECTOR(rd_adr),
-    out_dat => wr_adr
+    in_dat  => STD_LOGIC_VECTOR(prev_bin_reader_mosi.address(c_adr_w-1 DOWNTO 0)),
+    out_dat => bin_reader_mosi_ppp.address(c_adr_w-1 DOWNTO 0)
   );
   
-  p_rd_en : PROCESS(dp_pipeline_src_out_p.sync, snk_in.valid, wr_en, wr_adr, rd_adr, prev_rd_adr) IS
-  BEGIN
-    rd_en <= '1';
-    IF dp_pipeline_src_out_p.sync = '1' AND wr_en = '1' THEN  --
-      rd_en <= '0';
-    ELSIF wr_adr = rd_adr AND wr_adr /= prev_rd_adr THEN  -- toggle implementation
-      rd_en <= '0';                                 -- toggle implementation  
-    ELSIF snk_in.valid = '0' AND wr_en = '1' THEN
-      rd_en <= '1';
-    END IF;
-  END PROCESS;
   
-  -- cycles after sync
-  u_dp_pipeline_snk_in_2_cycle : ENTITY dp_lib.dp_pipeline
-  GENERIC MAP (
-    g_pipeline   => 2   -- 0 for wires, > 0 for registers, 
+  -- Only count sequential valid data on the same address when: address is the same as last and 1 or 2 cycles after the sync when in sync_detect; address is the same as last and past the initialisation and outside sync_detect
+  rd_cnt_allowed <= snk_in.valid WHEN ( bin_reader_mosi.address = prev_bin_reader_mosi.address AND ( snk_in_p.sync='1' OR (snk_in_pp.sync='1' AND snk_in_p.valid='1') ) )
+                                 OR (bin_reader_mosi.address = prev_bin_reader_mosi.address AND init_phase='0' AND sync_detect='0')
+                                 ELSE '0';
+  
+  -- Line rd_cnt_allowed up to p_nxt_bin_writer_mosi process
+  u_common_pipeline_sl_rd_cnt_allowed : ENTITY common_lib.common_pipeline_sl
+  GENERIC MAP(
+    g_pipeline       => 2 -- 0 for wires, > 0 for registers, 
   )
   PORT MAP (
-    rst          => dp_rst,
-    clk          => dp_clk,
-    snk_in       => snk_in,
-    src_out      => dp_pipeline_src_out_pp
+    clk     => dp_clk,
+    in_dat  => rd_cnt_allowed,
+    out_dat => rd_cnt_allowed_pp
   );
+  
+  -- Detect a (valid) repeating address seperated by one other address past the initialisation and outside the first two cycles of a (new) sync                                        --also @sync, one wil be true; use  NOT(1 or 1) instead of (0 or 0)
+  toggle_detect  <= snk_in.valid WHEN (bin_reader_mosi_pp.address = bin_reader_mosi.address AND bin_reader_mosi_pp.address /= prev_bin_reader_mosi.address AND toggle_detect_false = '0' AND NOT(snk_in.sync='1' OR snk_in_p.sync='1') ) 
+                                 ELSE '0';
 
-  p_prev_adr_cnt : PROCESS(wr_adr, rd_adr, prev_rd_adr, rd_adr_cnt, snk_in.sync, snk_in.valid, dp_pipeline_src_out_p.valid, dp_pipeline_src_out_p.sync) IS --change to p_nxt_rd_adr_cnt ;; misses wr_dat; 
-  BEGIN
-    nxt_rd_adr_cnt <= 1;
-    IF rd_adr = prev_rd_adr AND snk_in.valid = '1' AND snk_in.sync = '0' THEN
-      nxt_rd_adr_cnt <= rd_adr_cnt + 1 ;
-    ELSIF snk_in.valid = '0' AND snk_in.sync = '1' THEN  --address doesn't matter at unvalid and sync, removed: rd_adr = prev_rd_adr AND
-      nxt_rd_adr_cnt <= 0;
-    ELSIF rd_adr = prev_rd_adr AND snk_in.valid = '0' THEN
-      nxt_rd_adr_cnt <= rd_adr_cnt;
-    ELSIF rd_adr = prev_rd_adr AND snk_in.valid = '1' AND dp_pipeline_src_out_p.valid = '0' AND snk_in.sync = '1' THEN  -- toggle implementation; do the adresses even matter?
-      nxt_rd_adr_cnt <= 1;                                                                                             -- toggle implementation
-    ELSIF rd_adr = prev_rd_adr AND snk_in.valid = '1' AND dp_pipeline_src_out_p.valid = '0' THEN  -- toggle implementation
-      nxt_rd_adr_cnt <= rd_adr_cnt + 1;                                                           -- toggle implementation
-    ELSIF wr_adr = rd_adr AND snk_in.valid = '1' AND snk_in.sync = '1' THEN    -- toggle implementation; do the adresses even matter?
-      nxt_rd_adr_cnt <= 1;                                                    -- toggle implementation
-    ELSIF wr_adr = rd_adr AND rd_adr /= prev_rd_adr AND snk_in.valid = '0' THEN  -- toggle implementation: disable count; -2 cycles count + 0
-      nxt_rd_adr_cnt <= TO_UINT(wr_dat);                                    -- toggle implementation
-    ELSIF wr_adr = rd_adr AND snk_in.valid = '1' AND dp_pipeline_src_out_p.sync = '0' THEN  -- toggle implentation
-      nxt_rd_adr_cnt <= TO_UINT(wr_dat) + 1;        -- toggle implentation
-    ELSIF wr_adr = rd_adr AND snk_in.valid = '0' THEN  -- toggle implentation
-      nxt_rd_adr_cnt <= rd_adr_cnt;                    -- toggle implentation
-    ELSIF snk_in.valid = '0' AND rd_adr /= prev_rd_adr AND wr_adr /= rd_adr THEN
-      nxt_rd_adr_cnt <= 0;
-    END IF;
-  END PROCESS;
   
-  p_nxt_same_r_w_adr : PROCESS(wr_adr, rd_adr) IS  -- toggle implentation  ;; misses g_nof_bins ??
-  BEGIN
-    nxt_same_r_w_adr <= '0';
-    IF wr_adr = rd_adr AND g_nof_bins > 1 THEN
-      nxt_same_r_w_adr <= '1';
-    END IF;
-  END PROCESS;
+  -- Line up to p_nxt_bin_writer_mosi process
+  u_common_pipeline_sl_toggle_detect : ENTITY common_lib.common_pipeline_sl
+  GENERIC MAP(
+    g_pipeline       => 2 -- 0 for wires, > 0 for registers, 
+  )
+  PORT MAP (
+    clk     => dp_clk,
+    in_dat  => toggle_detect,
+    out_dat => toggle_detect_pp
+  );
+  
+  -- Detect an (valid) address that has to be read as well as written at the same time
+  same_r_w_address <= snk_in.valid WHEN (bin_reader_mosi.address = bin_reader_mosi_ppp.address AND init_phase = '0' AND sync_detect = '0') ELSE '0';
   
-  -- Pipeline for toggle issue
-  u_common_pipeline_sl_same_r_w_adr : ENTITY common_lib.common_pipeline_sl
+  -- Line up top p_nxt_bin_writer_mosi process
+  u_common_pipeline_sl_same_r_w_address : ENTITY common_lib.common_pipeline_sl
   GENERIC MAP(
-    g_pipeline       => 1 -- 0 for wires, > 0 for registers, 
+    g_pipeline       => 2 -- 0 for wires, > 0 for registers, 
   )
   PORT MAP (
     clk     => dp_clk,
-    in_dat  => same_r_w_adr,
-    out_dat => prev_same_r_w_adr
+    in_dat  => same_r_w_address,
+    out_dat => same_r_w_address_pp
   );
+
+
+  -----------------------------------------------------------------------------
+  -- Bin writer : increments current bin value and sets up write request
+  -- . in  : toggle_detect_pp      (latency: 2)
+  -- . in  : same_r_w_address_pp   (latency: 2)
+  -- . in  : bin_reader_mosi_pp    (latency: 2)
+  -- . in  : bin_reader_rd_miso    (latency: 2)  aka bin_arbiter_rd_miso or common_ram_r_w_miso
+  -- . in  : rd_cnt_allowed_pp     (latency: 2)
+  -- . in  : sync_detect_pp
+  -- . out : bin_writer_mosi  (latency: 3)
+  -----------------------------------------------------------------------------
+  p_nxt_bin_writer_mosi : PROCESS(bin_reader_rd_miso, 
+                                  bin_reader_mosi_pp.address, toggle_detect_pp, rd_cnt_allowed_pp, prev_wrdata, prev_prev_wrdata, prev_prev_prev_wrdata, sync_detect_pp, same_r_w_address_pp) IS
+  BEGIN
+    nxt_bin_writer_mosi <= c_mem_mosi_rst;
+    dbg_state_string <= "unv";
+    IF bin_reader_rd_miso.rdval='1' THEN
+      nxt_bin_writer_mosi.wr      <= '1';
+      nxt_bin_writer_mosi.wrdata  <= INCR_UVEC(bin_reader_rd_miso.rddata, 1);
+      nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
+      nxt_prev_wrdata             <= TO_UINT(bin_reader_rd_miso.rddata) + 1;
+      dbg_state_string <= "val";
+
+    ELSIF toggle_detect_pp = '1' THEN
+      nxt_bin_writer_mosi.wr      <= '1';
+      nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_prev_wrdata+1), c_mem_data_w);
+      nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
+      nxt_prev_wrdata             <= prev_prev_wrdata+1;
+      dbg_state_string <= "td ";
+      
+    ELSIF rd_cnt_allowed_pp = '1' THEN
+      nxt_bin_writer_mosi.wr      <= '1';
+      nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_wrdata + 1), c_mem_data_w);
+      nxt_prev_wrdata             <= prev_wrdata + 1;
+      dbg_state_string <= "r# ";
+      nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
+      
+    ELSIF sync_detect_pp = '1' THEN
+      nxt_bin_writer_mosi.wr      <= '1';
+      nxt_bin_writer_mosi.wrdata  <= TO_UVEC(1, c_mem_data_w); -- snk_in.sync: 1; snk_in_p.sync (thus new adress): 1; snk_in_pp.sync (thus new adress): 1
+      nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
+      nxt_prev_wrdata             <= 1;
+      dbg_state_string  <= "sd ";
+      
+    ELSIF same_r_w_address_pp = '1' THEN
+      nxt_bin_writer_mosi.wr      <= '1';
+      nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_prev_prev_wrdata+1), c_mem_data_w);
+      nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
+      nxt_prev_wrdata             <= prev_prev_prev_wrdata + 1;
+      dbg_state_string  <= "srw";
+    END IF;
+  END PROCESS; 
   
-  p_nxt_wr_dat : PROCESS(rd_dat, rd_adr_cnt, rd_val, dp_pipeline_src_out_p.sync, dp_pipeline_src_out_pp.sync, wr_en) IS --misses: same_r_w_adr; c_word_w?; prev_same_r_w_adr;
+  p_prev_wrdata : PROCESS(dp_clk, dp_rst, nxt_bin_writer_mosi.wr) IS  --seperated from p_bin_writer_mosi since the implementation was unwanted
   BEGIN
-    nxt_wr_dat <= (OTHERS => '0');
-    IF dp_pipeline_src_out_p.sync = '1' THEN
-      nxt_wr_dat <= TO_UVEC(rd_adr_cnt, c_word_w);
-    ELSIF dp_pipeline_src_out_pp.sync = '1' THEN
-      nxt_wr_dat <= TO_UVEC(rd_adr_cnt, c_word_w);
-    ELSIF same_r_w_adr = '1' AND rd_val = '0' THEN    -- toggle implementation: same adress forced rd_val to 0, counter instead of ram knows what to write
-      nxt_wr_dat <= TO_UVEC(rd_adr_cnt, c_word_w);     -- toggle implementation
-    ELSIF dp_pipeline_src_out_pp.valid = '0' AND prev_same_r_w_adr = '1' THEN  -- toggle implementation: prevent 2* rd_dat
-      nxt_wr_dat <= TO_UVEC(rd_adr_cnt, c_word_w);     -- toggle implementation
-    ELSIF rd_val = '1' THEN
-      nxt_wr_dat <= INCR_UVEC(rd_dat, rd_adr_cnt);
+    IF dp_rst = '1' THEN
+      prev_wrdata           <= 0;
+      prev_prev_wrdata      <= 0;
+      prev_prev_prev_wrdata <= 0;
+    ELSIF nxt_bin_writer_mosi.wr='1' AND RISING_EDGE(dp_clk) THEN
+      prev_wrdata           <= nxt_prev_wrdata;
+      prev_prev_wrdata      <= prev_wrdata;
+      prev_prev_prev_wrdata <= prev_prev_wrdata;
     END IF;
   END PROCESS;
-  
-  p_clk : PROCESS(dp_clk, dp_rst)
+
+  p_bin_writer_mosi : PROCESS(dp_clk, dp_rst) IS  --, nxt_bin_writer_mosi, nxt_prev_wrdata, prev_wrdata, prev_prev_wrdata
   BEGIN
-  IF dp_rst='1' THEN
-    rd_adr_cnt <= 0;
-    wr_en <= '0';
-  ELSIF rising_edge(dp_clk) THEN
-    rd_adr_cnt <= nxt_rd_adr_cnt;
-    wr_dat <= nxt_wr_dat;
-    wr_en <= nxt_wr_en;
-    same_r_w_adr <= nxt_same_r_w_adr;
-    cycle_cnt <= nxt_cycle_cnt;                     -- ( ander functieblok )
-    prev_ram_out_wr_adr <= ram_out_wr_adr;          --         ''
-  END IF; 
-  END PROCESS;  
+    IF dp_rst = '1' THEN
+       bin_writer_mosi       <= c_mem_mosi_rst;
+--       prev_wrdata           <= 0;
+--       prev_prev_wrdata      <= 0;
+--       prev_prev_prev_wrdata <= 0;
+    ELSIF RISING_EDGE(dp_clk) THEN
+       bin_writer_mosi <= nxt_bin_writer_mosi;
+--       IF nxt_bin_writer_mosi.wr = '1' THEN
+--         prev_wrdata     <= nxt_prev_wrdata;
+--         prev_prev_wrdata<= prev_wrdata;
+--         prev_prev_prev_wrdata <= prev_prev_wrdata;
+--       END IF;
+    END IF;
+  END PROCESS;
+
+
+  -----------------------------------------------------------------------------
+  -- Bin Arbiter: Determine next RAM access
+  -- . in  : bin_reader_mosi       (latency: 0)
+  --       : init_phase            (latency: 0)
+  --       : prev_bin_reader_mosi  (latency: 1)
+  --       : bin_reader_mosi_pp    (latency: 2)
+  --       : bin_reader_mosi_ppp   (latency: 3)
+  --       : bin_writer_mosi       (latency: 3)
+  --       : sync_detect           (latency:    0? or 3?
+  --       : common_ram_r_w_miso   (latency: 2)
+  -- . out : bin_arbiter_rd_mosi   (latency: 1)
+  -- .     : bin_arbiter_rd_miso   (latency: 2)
+  -- .     : bin_arbiter_wr_mosi   (latency: 4)
+  -----------------------------------------------------------------------------
+  nxt_bin_arbiter_wr_mosi <= bin_writer_mosi;
+  -- Read RAM when subsequent addresses are not the same, when there is no toggle detected and only when the same address is not going to be written to. When a sync is detected don't read in the old RAM block.
+  nxt_bin_arbiter_rd_mosi.rd <= bin_reader_mosi.rd WHEN (bin_reader_mosi.address /= prev_bin_reader_mosi.address AND bin_reader_mosi.address /= bin_reader_mosi_pp.address 
+                                                         AND NOT(bin_reader_mosi.address = bin_reader_mosi_ppp.address) AND sync_detect='0')
+                                                   OR (init_phase = '1') ELSE '0';
+  nxt_bin_arbiter_rd_mosi.address <= bin_reader_mosi.address;
+
+  p_bin_arbiter_mosi : PROCESS(dp_clk, dp_rst) IS --, nxt_bin_arbiter_wr_mosi, nxt_bin_arbiter_rd_mosi
+  BEGIN
+    IF dp_rst = '1' THEN
+      bin_arbiter_wr_mosi <= c_mem_mosi_rst;
+      bin_arbiter_rd_mosi <= c_mem_mosi_rst;
+    ELSIF RISING_EDGE(dp_clk) THEN
+      bin_arbiter_wr_mosi <= nxt_bin_arbiter_wr_mosi;
+      bin_arbiter_rd_mosi <= nxt_bin_arbiter_rd_mosi;
+    END IF;
+  END PROCESS;
+  
+--  -- Temporary debug data
+--  sla_out_ram_miso.rddata <= bin_arbiter_wr_mosi.wrdata;
+  
+  -- Make RAM data available for the bin_reader (or bin_writer)
+  bin_arbiter_rd_miso <= common_ram_r_w_miso;
   
   
   -----------------------------------------------------------------------------
   -- RAM selector & Dual swapped RAM instances:
-  --  2 cycles after a sync the RAM block is swapped for an empty one to allow
-  --  the block to be read out till the next sync+2 cycles
+  --  4 cycles after a sync the RAM block is swapped for an empty one to allow
+  --  the block to be read out till the next sync+3 cycles
+  --  The input is the st side, the output is the dp clocked mm side.
   --
   -- Depending on ram_pointer:
   -- ram_pointer = '0': input RAM_0, output RAM_1
   -- ram_pointer = '1': input RAM_1, output RAM_0
   --
-  -- input in:  dp_pipeline_src_out_pp.sync;  wr_en; wr_dat; wr_adr; 
-  --            rd_adr; rd_en; 
-  --       out: rd_dat, rd_val
+  -- input in:  snk_in_pppp.sync      (latency: 4)
+  --            bin_arbiter_wr_mosi   (latency: 4)
+  --            bin_arbiter_rd_mosi   (latency: 1)
+  --       out: common_ram_r_w_miso   (latency: 2)
   --
   -- output in:  ram_out_wr_en; ram_out_wr_dat; ram_out_wr_adr; ram_out_rd_adr;
   --             ram_out_rd_en
   --        out: ram_out_rd_dat; ram_out_rd_val
   -----------------------------------------------------------------------------
-  p_ram_pointer_at_sync : PROCESS(dp_pipeline_src_out_pp) IS -- needs nxt_ram_pointer ??
+  p_ram_pointer_at_sync : PROCESS(snk_in_pppp) IS -- needs nxt_ram_pointer ??
   BEGIN
-    IF dp_pipeline_src_out_pp.sync = '1' THEN
+    IF snk_in_pppp.sync = '1' THEN                                             --needs snk_in_pppp                                                      <--
       ram_pointer <= NOT(ram_pointer);
     END IF;
   END PROCESS;
   
-  p_ram_pointer : PROCESS(ram_pointer, wr_en, wr_dat, wr_adr, rd_adr, rd_en, ram_0_rd_dat, ram_0_rd_val, 
+  p_ram_pointer : PROCESS(ram_pointer, bin_arbiter_wr_mosi, bin_arbiter_rd_mosi, ram_0_rd_dat, ram_0_rd_val, 
                           ram_out_wr_en, ram_out_wr_dat, ram_out_wr_adr, ram_out_rd_adr, ram_out_rd_en, ram_1_rd_dat, ram_1_rd_val) IS
   BEGIN
     IF ram_pointer='0' THEN
     
       -- ST side (RAM 0)
-      ram_0_wr_en <= wr_en;
-      ram_0_wr_dat <= wr_dat;
-      ram_0_wr_adr <= wr_adr;
-      ram_0_rd_adr <= rd_adr;
-      ram_0_rd_en <= rd_en;
-      rd_dat <= ram_0_rd_dat;
-      rd_val <= ram_0_rd_val;
+      ram_0_wr_en  <= bin_arbiter_wr_mosi.wr;                            -- bin_arbiter_wr_mosi.wr        wr_en
+      ram_0_wr_dat <= bin_arbiter_wr_mosi.wrdata(c_word_w-1 DOWNTO 0);   -- bin_arbiter_wr_mosi.wrdata    wr_dat
+      ram_0_wr_adr <= bin_arbiter_wr_mosi.address(c_adr_w-1 DOWNTO 0);   -- bin_arbiter_wr_mosi.address   wr_adr
+      ram_0_rd_adr <= bin_arbiter_rd_mosi.address(c_adr_w-1 DOWNTO 0);   -- bin_arbiter_rd_mosi.address   rd_adr
+      ram_0_rd_en  <= bin_arbiter_rd_mosi.rd;                            -- bin_arbiter_rd_mosi.rd        rd_en
+      common_ram_r_w_miso.rddata(c_word_w-1 DOWNTO 0) <= ram_0_rd_dat;   -- common_ram_r_w_miso.rddata  rd_dat
+      common_ram_r_w_miso.rdval  <= ram_0_rd_val;                        -- common_ram_r_w_miso.rdval   rd_val
       
       
       -- dp_clk'd  MM side (RAM 1)
@@ -421,13 +621,13 @@ BEGIN
     ELSE -- ram_pointer='1'
     
       -- ST side (RAM 1)
-      ram_1_wr_en <= wr_en;
-      ram_1_wr_dat <= wr_dat;
-      ram_1_wr_adr <= wr_adr;
-      ram_1_rd_adr <= rd_adr;
-      ram_1_rd_en <= rd_en;
-      rd_dat <= ram_1_rd_dat;
-      rd_val <= ram_1_rd_val;
+      ram_1_wr_en  <= bin_arbiter_wr_mosi.wr;      
+      ram_1_wr_dat <= bin_arbiter_wr_mosi.wrdata(c_word_w-1 DOWNTO 0);  
+      ram_1_wr_adr <= bin_arbiter_wr_mosi.address(c_adr_w-1 DOWNTO 0); 
+      ram_1_rd_adr <= bin_arbiter_rd_mosi.address(c_adr_w-1 DOWNTO 0); 
+      ram_1_rd_en  <= bin_arbiter_rd_mosi.rd;      
+      common_ram_r_w_miso.rddata(c_word_w-1 DOWNTO 0) <= ram_1_rd_dat;
+      common_ram_r_w_miso.rdval  <= ram_1_rd_val;
       
       --dp_clk'd  MM side (RAM 0)
       ram_0_wr_en <= ram_out_wr_en;
@@ -522,54 +722,72 @@ BEGIN
   mm_adr_cnt <= TO_UINT(sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0)) WHEN sla_in_ram_mosi.rd = '1';
   ram_out_same_w_r_adr <= '1' WHEN ram_out_wr_adr = sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0) ELSE '0';
   
-  p_ram_to_fifo : PROCESS(dp_pipeline_src_out_pp.sync, cycle_cnt, sla_in_ram_mosi.address, sla_in_ram_mosi.rd, ram_out_rd_dat, ram_out_rd_val, prev_ram_out_wr_adr, mm_adr_illegal, ram_out_same_w_r_adr) IS
+  p_ram_to_fifo : PROCESS(snk_in_pp.sync, cycle_cnt, sla_in_ram_mosi.address, sla_in_ram_mosi.rd, ram_out_rd_dat, ram_out_rd_val, prev_ram_out_wr_adr, mm_adr_illegal_pp, ram_out_same_w_r_adr, bin_arbiter_wr_mosi.wrdata) IS
   BEGIN
-    IF dp_pipeline_src_out_pp.sync = '1' THEN
-      ram_out_wr_en <= '0';
-      nxt_cycle_cnt <= 0;
-    ELSIF cycle_cnt = c_clear THEN
-      ram_out_wr_adr <= (OTHERS => '0');
-      ram_out_wr_dat <= (OTHERS => '0');
-      ram_out_wr_en <= '1';
-      IF ram_out_same_w_r_adr = '1' THEN
-        ram_out_rd_en                           <= '0';
-        sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= (OTHERS => '0');
-        sla_out_ram_miso.rdval                          <= ram_out_rd_val;
-      ELSE
+    IF g_ram_miso_sim_mode = FALSE THEN
+      IF snk_in_pppp.sync = '1' THEN
+        ram_out_wr_en <= '0';
+        nxt_cycle_cnt <= 0;
+      ELSIF cycle_cnt = c_clear THEN
+        ram_out_wr_adr <= (OTHERS => '0');
+        ram_out_wr_dat <= (OTHERS => '0');
+        ram_out_wr_en <= '1';
+        IF ram_out_same_w_r_adr = '1' THEN
+          ram_out_rd_en                           <= '0';
+          sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= (OTHERS => '0');
+          sla_out_ram_miso.rdval                          <= ram_out_rd_val;
+        ELSE
+          ram_out_rd_adr                          <= sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0);
+          ram_out_rd_en                           <= sla_in_ram_mosi.rd;
+          sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= ram_out_rd_dat;
+          sla_out_ram_miso.rdval                          <= ram_out_rd_val;
+        END IF;
+        nxt_cycle_cnt <= cycle_cnt +1;
+      ELSIF cycle_cnt > c_clear THEN
+        ram_out_wr_adr <= INCR_UVEC(prev_ram_out_wr_adr, 1);
+        ram_out_wr_dat <= (OTHERS => '0');
+        nxt_cycle_cnt <= cycle_cnt +1;
+        IF ram_out_same_w_r_adr = '1' OR snk_in.sync = '1' THEN
+          sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= (OTHERS => '0');
+          sla_out_ram_miso.rdval                          <= ram_out_rd_val;
+        ELSE
+          ram_out_rd_adr                          <= sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0);
+          ram_out_rd_en                           <= sla_in_ram_mosi.rd;
+          sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= ram_out_rd_dat;
+          sla_out_ram_miso.rdval                          <= ram_out_rd_val;
+        END IF;
+        ram_out_wr_en <= '1';
+      ELSIF mm_adr_illegal_pp = '1' THEN
         ram_out_rd_adr                          <= sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0);
         ram_out_rd_en                           <= sla_in_ram_mosi.rd;
-        sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= ram_out_rd_dat;
-        sla_out_ram_miso.rdval                          <= ram_out_rd_val;
-      END IF;
-      nxt_cycle_cnt <= cycle_cnt +1;
-    ELSIF cycle_cnt > c_clear THEN
-      ram_out_wr_adr <= INCR_UVEC(prev_ram_out_wr_adr, 1);
-      nxt_cycle_cnt <= cycle_cnt +1;
-      IF ram_out_same_w_r_adr = '1' OR snk_in.sync = '1' THEN
         sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= (OTHERS => '0');
         sla_out_ram_miso.rdval                          <= ram_out_rd_val;
+        nxt_cycle_cnt                           <= cycle_cnt +1;
+        ram_out_wr_en                           <= '0';
       ELSE
         ram_out_rd_adr                          <= sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0);
         ram_out_rd_en                           <= sla_in_ram_mosi.rd;
         sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= ram_out_rd_dat;
         sla_out_ram_miso.rdval                          <= ram_out_rd_val;
+        nxt_cycle_cnt                           <= cycle_cnt +1;
+        ram_out_wr_en                           <= '0';
       END IF;
-    ELSIF mm_adr_illegal_pp = '1' THEN
-      ram_out_rd_adr                          <= sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0);
-      ram_out_rd_en                           <= sla_in_ram_mosi.rd;
-      sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= (OTHERS => '0');
-      sla_out_ram_miso.rdval                          <= ram_out_rd_val;
-      nxt_cycle_cnt                           <= cycle_cnt +1;
+      dbg_ram_miso.rddata     <= bin_arbiter_wr_mosi.wrdata;
     ELSE
-      ram_out_rd_adr                          <= sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0);
-      ram_out_rd_en                           <= sla_in_ram_mosi.rd;
-      sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= ram_out_rd_dat;
-      sla_out_ram_miso.rdval                          <= ram_out_rd_val;
-      nxt_cycle_cnt                           <= cycle_cnt +1;
+      sla_out_ram_miso.rddata <= bin_arbiter_wr_mosi.wrdata;
     END IF;
   END PROCESS;
   
   
+  p_clk : PROCESS(dp_clk, dp_rst)
+  BEGIN
+  IF dp_rst='1' THEN
+    cycle_cnt <= 0;
+  ELSIF rising_edge(dp_clk) THEN
+    cycle_cnt <= nxt_cycle_cnt;
+    prev_ram_out_wr_adr <= ram_out_wr_adr;
+  END IF; 
+  END PROCESS;    
       
 
 END rtl;
diff --git a/libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd b/libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd
index 965564ea25c13c9cf8c3ca7feaf62bd5c7b1593b..ed7f5e442446030567452187cff9bf95bc72c0bc 100644
--- a/libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd
+++ b/libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd
@@ -10,9 +10,10 @@ USE technology_lib.technology_select_pkg.ALL;
 
 ENTITY st_histogram_8_april IS
   GENERIC (
-    g_in_data_w     : NATURAL := 14;   -- >= 9 when g_nof_bins is 512; (max. c_dp_stream_data_w =768)         <-- maybe just g_data_w ??
-    g_nof_bins      : NATURAL := 512;  -- is a power of 2 and g_nof_bins <= c_data_span; max. 512
-    g_nof_data      : NATURAL         
+    g_in_data_w         : NATURAL := 14;   -- >= 9 when g_nof_bins is 512; (max. c_dp_stream_data_w =768)         <-- maybe just g_data_w ??
+    g_nof_bins          : NATURAL := 512;  -- is a power of 2 and g_nof_bins <= c_data_span; max. 512
+    g_nof_data          : NATURAL         
+--    g_sim_ram_miso_mode : BOOLEAN := FALSE -- when TRUE the ram_miso bus will get a copy of the data written into the RAM.
   );                
   PORT (            
     dp_rst   : IN  STD_LOGIC;
@@ -57,31 +58,29 @@ ARCHITECTURE rtl OF st_histogram_8_april IS
   SIGNAL nxt_bin_arbiter_rd_mosi  : t_mem_mosi;
   SIGNAL bin_arbiter_rd_mosi      : t_mem_mosi;
 
+  SIGNAL bin_arbiter_rd_miso      : t_mem_miso := c_mem_miso_rst;
+  SIGNAL bin_reader_rd_miso       : t_mem_miso := c_mem_miso_rst;
   SIGNAL common_ram_r_w_0_miso    : t_mem_miso := c_mem_miso_rst;
   
   SIGNAL init_phase           : STD_LOGIC := '1';
+  SIGNAL nxt_init_phase       : STD_LOGIC;
   SIGNAL rd_cnt_allowed       : STD_LOGIC := '0';
   SIGNAL rd_cnt_allowed_pp    : STD_LOGIC := '0';
-  SIGNAL nxt_rd_adr_cnt       : NATURAL := 0;
-  SIGNAL rd_adr_cnt           : NATURAL;-- := 0;
   SIGNAL toggle_detect        : STD_LOGIC := '0';
   SIGNAL toggle_detect_pp     : STD_LOGIC;
   SIGNAL toggle_detect_false  : STD_LOGIC := '1';
---  SIGNAL nxt_toggle_adr_cnt : NATURAL := 0;
---  SIGNAL toggle_adr_cnt     : NATURAL;-- := 0;
   SIGNAL nxt_prev_wrdata      : NATURAL;
   SIGNAL prev_wrdata          : NATURAL;
   SIGNAL prev_prev_wrdata     : NATURAL;
   SIGNAL prev_prev_prev_wrdata: NATURAL;
   SIGNAL sync_detect          : STD_LOGIC := '0';
   SIGNAL sync_detect_pp       : STD_LOGIC;
---  SIGNAL adr_w             : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
   SIGNAL same_r_w_address     : STD_LOGIC;
   SIGNAL same_r_w_address_pp  : STD_LOGIC;
   
   --pipelined signals
-  SIGNAL dp_pipeline_src_out_p    : t_dp_sosi;
-  SIGNAL dp_pipeline_src_out_pp   : t_dp_sosi;
+  SIGNAL snk_in_p    : t_dp_sosi;
+  SIGNAL snk_in_pp   : t_dp_sosi;
   SIGNAL prev_bin_reader_mosi     : t_mem_mosi := c_mem_mosi_rst ;
   SIGNAL bin_reader_mosi_pp       : t_mem_mosi := c_mem_mosi_rst;
   SIGNAL bin_reader_mosi_ppp      : t_mem_mosi := c_mem_mosi_rst;
@@ -96,16 +95,28 @@ ARCHITECTURE rtl OF st_histogram_8_april IS
 BEGIN 
 
   -----------------------------------------------------------------------------
-  -- Bin reader: Convert snk_in data to bin_reader_mosi with read request
-  -- . in  : snk_in          (latency: 0)
-  -- . out : bin_reader_mosi (latency: 0)
-  -- . out : bin_reader_mosi_pp (latency: 2)
-  -- - out : rd_cnt_allowed_pp  (latency: 2)
+  -- Bin reader: Convert snk_in data to bin_reader_mosi with read request 
+  --             and generate signals for detection of problems in the 
+  --             consecutive data.
+  -- . in  : snk_in               (latency: 0)
+  --       : bin_arbiter_rd_miso  (latency: 2)
+  -- . out : init_phase           (latency: 0 ?
+  --       : bin_reader_mosi      (latency: 0)
+  --       : prev_bin_reader_mosi (latency: 1)
+  --       : bin_reader_mosi_pp   (latency: 2)
+  --       : bin_reader_mosi_ppp  (latency: 3)
+  --       : bin_reader_rd_miso   (latency: 2)
+  --       : rd_cnt_allowed_pp    (latency: 2)
+  --       : same_r_w_address_pp  (latency: 2)
+  --       : toggle_detect_pp     (latency: 2)
+  --       : sync_detect          (latency: 0)
+  --       : sync_detect_pp       (latency: 2)
   -----------------------------------------------------------------------------
   bin_reader_mosi.rd                          <= snk_in.valid; -- when 1, count allowed
   bin_reader_mosi.address(c_adr_w-1 DOWNTO 0) <= snk_in.data(g_in_data_w-1 DOWNTO c_adr_low); 
+  bin_reader_rd_miso                          <= bin_arbiter_rd_miso;
   
-  --snk_in pipeline
+  --snk_in pipeline; Enable sync and valid comparisons
   u_dp_pipeline_snk_in_1_cycle : ENTITY dp_lib.dp_pipeline
   GENERIC MAP (
     g_pipeline   => 1  -- 0 for wires, > 0 for registers, 
@@ -114,11 +125,22 @@ BEGIN
     rst          => dp_rst,
     clk          => dp_clk,
     snk_in       => snk_in,
-    src_out      => dp_pipeline_src_out_p
+    src_out      => snk_in_p
   );
   
-  init_phase <= '0' WHEN dp_pipeline_src_out_p.sync = '1';
+  init_phase <= '0' WHEN snk_in_p.sync = '1'; -- ELSE will be impossible since the init_phase may only be triggered once on the first sync
+--  nxt_init_phase <= '0' WHEN snk_in_p_.sync='1' ELSE init_phase;
+  
+--  p_init_phase : PROCESS(dp_clk, dp_rst)
+--  BEGIN
+--    IF dp_rst = '1' THEN
+--      init_phase <= '1';
+--    ELSIF RISING_EDGE(dp_clk) THEN
+--      init_phase <= nxt_init_phase;
+--    END IF;
+--  END PROCESS;
   
+  -- Enable sync comparisons
   u_dp_pipeline_snk_in_2_cycle : ENTITY dp_lib.dp_pipeline
   GENERIC MAP (
     g_pipeline   => 2  -- 0 for wires, > 0 for registers, 
@@ -127,25 +149,15 @@ BEGIN
     rst          => dp_rst,
     clk          => dp_clk,
     snk_in       => snk_in,
-    src_out      => dp_pipeline_src_out_pp
+    src_out      => snk_in_pp
   );
   
-  dbg_snk_data <= dp_pipeline_src_out_pp.data(g_in_data_w-1 DOWNTO 0);
-  
-  toggle_detect_false <= '0' WHEN dp_pipeline_src_out_pp.sync = '1';
-  sync_detect <= snk_in.valid WHEN (snk_in.sync='1' OR dp_pipeline_src_out_p.sync='1' OR dp_pipeline_src_out_pp.sync='1') ELSE '0';
+  dbg_snk_data <= snk_in_pp.data(g_in_data_w-1 DOWNTO 0);
   
---  u_dp_sync_detect_3_cycle : ENTITY dp_lib.dp_pipeline
---  GENERIC MAP (
---    g_pipeline   => 3  -- 0 for wires, > 0 for registers, 
---  )
---  PORT MAP (
---    rst          => dp_rst,
---    clk          => dp_clk,
---    snk_in       => sync_detect,
---    src_out      => sync_detect_ppp
---  );
+  toggle_detect_false <= '0' WHEN snk_in_pp.sync = '1'; -- ELSE will be impossible since the toggle_detect_false may only be triggered once on the first sync
+  sync_detect <= snk_in.valid WHEN (snk_in.sync='1' OR snk_in_p.sync='1' OR snk_in_pp.sync='1') ELSE '0'; -- @sync, first 3 cycles would try to read from the wrong (old) RAM block, detect this problem
   
+  -- Line up to p_nxt_bin_writer_mosi process  
   u_common_pipeline_sl_sync_detect_2_cycle : ENTITY common_lib.common_pipeline_sl
   GENERIC MAP(
     g_pipeline       => 2 -- 0 for wires, > 0 for registers, 
@@ -156,19 +168,8 @@ BEGIN
     out_dat => sync_detect_pp
   );
   
-  --prev_bin_reader_mosi pipeline
---  u_dp_pipeline_bin_reader_mosi_1_cycle : ENTITY dp_lib.dp_pipeline
---  GENERIC MAP (
---    g_pipeline   => 1  -- 0 for wires, > 0 for registers, 
---  )
---  PORT MAP (
---    rst          => dp_rst,
---    clk          => dp_clk,
---    snk_in       => bin_reader_mosi,
---    src_out      => prev_bin_reader_mosi
---  );
-
- 
+  -- Enable adress comparisons 1 cycle back  
+  -- Skip unvalid data with trigger bin_reader_mosi.rd to make comparisons between unvalid-data-seperated data possible.
   u_common_pipeline_bin_reader_mosi_1_cycle : ENTITY common_lib.common_pipeline
   GENERIC MAP (
     g_representation => "UNSIGNED", --orig. signed
@@ -183,7 +184,8 @@ BEGIN
     out_dat => prev_bin_reader_mosi.address(c_adr_w-1 DOWNTO 0)
   );
   
-  u_common_pipeline_bin_reader_mosi_2_cycle : ENTITY common_lib.common_pipeline  -- better to pipeline prev_bin_reader_mosi??
+  -- Enable adress comparisons 2 cycles back
+  u_common_pipeline_bin_reader_mosi_2_cycle : ENTITY common_lib.common_pipeline
   GENERIC MAP (
     g_representation => "UNSIGNED", --orig. signed
     g_pipeline       => 1,
@@ -196,7 +198,8 @@ BEGIN
     out_dat => bin_reader_mosi_pp.address(c_adr_w-1 DOWNTO 0)
   );
   
-  u_common_pipeline_bin_reader_mosi_3_cycle : ENTITY common_lib.common_pipeline  -- better to pipeline prev_bin_reader_mosi??
+  -- Enable adress comparisons 3 cycles back
+  u_common_pipeline_bin_reader_mosi_3_cycle : ENTITY common_lib.common_pipeline
   GENERIC MAP (
     g_representation => "UNSIGNED", --orig. signed
     g_pipeline       => 2,
@@ -210,24 +213,12 @@ BEGIN
   );
   
   
-  --bin_reader_mosi_pp pipeline
---  u_dp_pipeline_bin_reader_mosi_2_cycle : ENTITY dp_lib.dp_pipeline
---  GENERIC MAP (
---    g_pipeline   => 2  -- 0 for wires, > 0 for registers, 
---  )
---  PORT MAP (
---    rst          => dp_rst,
---    clk          => dp_clk,
---    snk_in       => bin_reader_mosi,
---    src_out      => bin_reader_mosi_pp
---  );
-  
---  rd_cnt_allowed <= snk_in.valid WHEN (bin_reader_mosi.address = prev_bin_reader_mosi.address AND init_phase = '0') ELSE '0'; -- AND snk_in.sync='0'
-  rd_cnt_allowed <= snk_in.valid WHEN ( bin_reader_mosi.address = prev_bin_reader_mosi.address AND ( (dp_pipeline_src_out_p.sync='1' AND dp_pipeline_src_out_p.valid='1') OR (dp_pipeline_src_out_pp.sync='1' AND dp_pipeline_src_out_p.valid='1') ) )
-                                 ELSE snk_in.valid WHEN (bin_reader_mosi.address = prev_bin_reader_mosi.address AND init_phase='0' AND snk_in.sync='0')
+  -- Only count sequential valid data on the same address when: address is the same as last and 1 or 2 cycles after the sync when in sync_detect; address is the same as last and past the initialisation and outside sync_detect
+  rd_cnt_allowed <= snk_in.valid WHEN ( bin_reader_mosi.address = prev_bin_reader_mosi.address AND ( snk_in_p.sync='1' OR (snk_in_pp.sync='1' AND snk_in_p.valid='1') ) )
+                                 OR (bin_reader_mosi.address = prev_bin_reader_mosi.address AND init_phase='0' AND sync_detect='0')
                                  ELSE '0';
   
-  --rd_cnt_allowed_pp pipeline
+  -- Line rd_cnt_allowed up to p_nxt_bin_writer_mosi process
   u_common_pipeline_sl_rd_cnt_allowed : ENTITY common_lib.common_pipeline_sl
   GENERIC MAP(
     g_pipeline       => 2 -- 0 for wires, > 0 for registers, 
@@ -238,8 +229,12 @@ BEGIN
     out_dat => rd_cnt_allowed_pp
   );
   
-  toggle_detect  <= snk_in.valid WHEN (bin_reader_mosi_pp.address = bin_reader_mosi.address AND bin_reader_mosi_pp.address /= prev_bin_reader_mosi.address AND toggle_detect_false = '0') ELSE '0'; --AND (snk_in.sync='0' OR dp_pipeline_src_out_p.sync='0')
+  -- Detect a (valid) repeating address seperated by one other address past the initialisation and outside the first two cycles of a (new) sync                                        --also @sync, one wil be true; use  NOT(1 or 1) instead of (0 or 0)
+  toggle_detect  <= snk_in.valid WHEN (bin_reader_mosi_pp.address = bin_reader_mosi.address AND bin_reader_mosi_pp.address /= prev_bin_reader_mosi.address AND toggle_detect_false = '0' AND NOT(snk_in.sync='1' OR snk_in_p.sync='1') ) 
+                                 ELSE '0';
+
   
+  -- Line up to p_nxt_bin_writer_mosi process
   u_common_pipeline_sl_toggle_detect : ENTITY common_lib.common_pipeline_sl
   GENERIC MAP(
     g_pipeline       => 2 -- 0 for wires, > 0 for registers, 
@@ -250,8 +245,10 @@ BEGIN
     out_dat => toggle_detect_pp
   );
   
+  -- Detect an (valid) address that has to be read as well as written at the same time
   same_r_w_address <= snk_in.valid WHEN (bin_reader_mosi.address = bin_reader_mosi_ppp.address AND init_phase = '0' AND sync_detect = '0') ELSE '0';
   
+  -- Line up top p_nxt_bin_writer_mosi process
   u_common_pipeline_sl_same_r_w_address : ENTITY common_lib.common_pipeline_sl
   GENERIC MAP(
     g_pipeline       => 2 -- 0 for wires, > 0 for registers, 
@@ -265,55 +262,44 @@ BEGIN
 
   -----------------------------------------------------------------------------
   -- Bin writer : increments current bin value and sets up write request
-  -- . in  : dp_pipeline_src_out_pp (latency: 2)
   -- . in  : toggle_detect_pp      (latency: 2)
   -- . in  : same_r_w_address_pp   (latency: 2)
   -- . in  : bin_reader_mosi_pp    (latency: 2)
-  -- . in  : common_ram_r_w_0_miso (latency: 2)
+  -- . in  : bin_reader_rd_miso    (latency: 2)  aka bin_arbiter_rd_miso or common_ram_r_w_0_miso
   -- . in  : rd_cnt_allowed_pp     (latency: 2)
+  -- . in  : sync_detect_pp
   -- . out : bin_writer_mosi  (latency: 3)
   -----------------------------------------------------------------------------
-  p_nxt_bin_writer_mosi : PROCESS(common_ram_r_w_0_miso, common_ram_r_w_0_miso.rdval, common_ram_r_w_0_miso.rddata, 
-                                  bin_reader_mosi_pp.address, toggle_detect, rd_cnt_allowed_pp, rd_adr_cnt, init_phase, prev_wrdata, prev_prev_wrdata, sync_detect_pp, same_r_w_address_pp, dp_pipeline_src_out_pp.valid) IS
+  p_nxt_bin_writer_mosi : PROCESS(bin_reader_rd_miso, 
+                                  bin_reader_mosi_pp.address, toggle_detect_pp, rd_cnt_allowed_pp, init_phase, prev_wrdata, prev_prev_wrdata, prev_prev_prev_wrdata, sync_detect_pp, same_r_w_address_pp) IS -- init_phase unnecesary? ; removed: common_ram_r_w_0_miso.rdval, common_ram_r_w_0_miso.rddata,
   BEGIN
     nxt_bin_writer_mosi <= c_mem_mosi_rst;
     dbg_state_string <= "unv";
-    IF common_ram_r_w_0_miso.rdval='1' THEN -- OR rd_cnt_allowed_pp = '1'  -- when not same as last 2 adresses
+    IF bin_reader_rd_miso.rdval='1' THEN  --  common_ram_r_w_0_miso
       nxt_bin_writer_mosi.wr      <= '1';
-      nxt_bin_writer_mosi.wrdata  <= INCR_UVEC(common_ram_r_w_0_miso.rddata, 1); -- c_word_w); -- depends on count case -- rd_adr_cnt
-      nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address; --TODO: what other input do we need for this? -- becomes bin_reader_mosi.address
---      reset count? if toggle detected copy count to toggle counter
-      nxt_prev_wrdata             <= TO_UINT(common_ram_r_w_0_miso.rddata) + 1;
---      nxt_rd_adr_cnt              <= 0;                                                   -- really necessary ??
+      nxt_bin_writer_mosi.wrdata  <= INCR_UVEC(bin_reader_rd_miso.rddata, 1); -- common_ram_r_w_0_miso
+      nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
+      nxt_prev_wrdata             <= TO_UINT(bin_reader_rd_miso.rddata) + 1;  -- common_ram_r_w_0_miso
       dbg_state_string <= "val";
---      IF bin_reader_mosi_pp.address = bin_reader_mosi.address THEN             -- Double implemented ?? toggle?
---        nxt_toggle_adr_cnt <= INCR_UVEC(common_ram_r_w_0_miso.rddata, 1);      -- Double implemented ??
-    ELSIF toggle_detect_pp = '1' THEN -- dp_pipeline_src_out_pp: 2
+
+    ELSIF toggle_detect_pp = '1' THEN
       nxt_bin_writer_mosi.wr      <= '1';
-      nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_prev_wrdata+1), c_mem_data_w); -- prev_wrdata + rd_adr_cnt + toggle_adr_cnt??? + 1  òf prev_prev_wrdata + 1 ??
+      nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_prev_wrdata+1), c_mem_data_w);
       nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
---      nxt_toggle_adr_cnt          <= 0;
       nxt_prev_wrdata             <= prev_prev_wrdata+1;
       dbg_state_string <= "td ";
       
     ELSIF rd_cnt_allowed_pp = '1' THEN
---      nxt_rd_adr_cnt              <= rd_adr_cnt + 1;                                                                                                   -- << !! is rd_adr_cnt really necessary? prev_wrdata might fulfill the need !!
       nxt_bin_writer_mosi.wr      <= '1';
---      IF sync_detect_ppp = '1' THEN
---        nxt_bin_writer_mosi.wrdata <= TO_UVEC( (rd_adr_cnt + 1), c_mem_data_w); -- snk_in.sync (impossible); dp_pipeline_src_out_p (thus 1st cnt): 2 (cnt+1?); dp_pipeline_src_out_pp (1st or maybe 2nd cnt): cnt+1
---        dbg_state_string <= "rs ";
---      ELSE 
-        nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_wrdata + rd_adr_cnt + 1), c_mem_data_w); -- c_word_w); -- maybe RAM + cnt + 1 ??  -- only prev_wrdata + 1 necessary
-        nxt_prev_wrdata             <= prev_wrdata + 1;
-        dbg_state_string <= "r# ";
---      END IF;
+      nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_wrdata + 1), c_mem_data_w);
+      nxt_prev_wrdata             <= prev_wrdata + 1;
+      dbg_state_string <= "r# ";
       nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
       
-    ELSIF sync_detect_pp = '1' THEN -- snk_in.sync at least -- good as it is!
+    ELSIF sync_detect_pp = '1' THEN
       nxt_bin_writer_mosi.wr      <= '1';
-      nxt_bin_writer_mosi.wrdata  <= TO_UVEC(1, c_mem_data_w); -- snk_in.sync: 1; dp_pipeline_src_out_p.sync (thus new adress): 1; dp_pipeline_src_out_pp.sync (thus new adress): 1
+      nxt_bin_writer_mosi.wrdata  <= TO_UVEC(1, c_mem_data_w); -- snk_in.sync: 1; snk_in_p.sync (thus new adress): 1; snk_in_pp.sync (thus new adress): 1
       nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
---      nxt_rd_adr_cnt              <= 0;                             -- really necessary ??
       nxt_prev_wrdata             <= 1;
       dbg_state_string  <= "sd ";
       
@@ -325,38 +311,60 @@ BEGIN
       dbg_state_string  <= "srw";
     END IF;
   END PROCESS; 
+  
+  p_prev_wrdata : PROCESS(dp_clk, dp_rst, nxt_bin_writer_mosi.wr) IS  --seperated from p_bin_writer_mosi since the implementation was unwanted
+  BEGIN
+    IF dp_rst = '1' THEN
+      prev_wrdata           <= 0;
+      prev_prev_wrdata      <= 0;
+      prev_prev_prev_wrdata <= 0;
+    ELSIF nxt_bin_writer_mosi.wr='1' AND RISING_EDGE(dp_clk) THEN
+      prev_wrdata           <= nxt_prev_wrdata;
+      prev_prev_wrdata      <= prev_wrdata;
+      prev_prev_prev_wrdata <= prev_prev_wrdata;
+    END IF;
+  END PROCESS;
 
-  p_bin_writer_mosi : PROCESS(dp_clk, dp_rst, nxt_bin_writer_mosi, nxt_rd_adr_cnt, nxt_prev_wrdata, prev_wrdata, prev_prev_wrdata) IS
+  p_bin_writer_mosi : PROCESS(dp_clk, dp_rst) IS  --, nxt_bin_writer_mosi, nxt_prev_wrdata, prev_wrdata, prev_prev_wrdata
   BEGIN
     IF dp_rst = '1' THEN
-       bin_writer_mosi <= c_mem_mosi_rst;
+       bin_writer_mosi       <= c_mem_mosi_rst;
+--       prev_wrdata           <= 0;
+--       prev_prev_wrdata      <= 0;
+--       prev_prev_prev_wrdata <= 0;
     ELSIF RISING_EDGE(dp_clk) THEN
        bin_writer_mosi <= nxt_bin_writer_mosi;
---       rd_adr_cnt      <= nxt_rd_adr_cnt;
---       toggle_adr_cnt  <= nxt_toggle_adr_cnt;
-       prev_wrdata     <= nxt_prev_wrdata;
-       prev_prev_wrdata<= prev_wrdata;
-       prev_prev_prev_wrdata <= prev_prev_wrdata;
+--       IF nxt_bin_writer_mosi.wr = '1' THEN
+--         prev_wrdata     <= nxt_prev_wrdata;
+--         prev_prev_wrdata<= prev_wrdata;
+--         prev_prev_prev_wrdata <= prev_prev_wrdata;
+--       END IF;
     END IF;
   END PROCESS;
 
 
   -----------------------------------------------------------------------------
   -- Bin Arbiter: Determine next RAM access
-  -- . in  : bin_reader_mosi      (latency: 0)
-  --       : init_phase           (latency: 0)
-  --       : prev_bin_reader_mosi (latency: 1)
-  --       : bin_writer_mosi      (latency: 3)
-  -- . out : bin_arbiter_rd_mosi (latency: 1)
-  -- .     : bin_arbiter_wr_mosi (latency: 4)
+  -- . in  : bin_reader_mosi       (latency: 0)
+  --       : init_phase            (latency: 0)
+  --       : prev_bin_reader_mosi  (latency: 1)
+  --       : bin_reader_mosi_pp    (latency: 2)
+  --       : bin_reader_mosi_ppp   (latency: 3)
+  --       : bin_writer_mosi       (latency: 3)
+  --       : sync_detect           (latency:    0? or 3?
+  --       : common_ram_r_w_0_miso (latency: 2)
+  -- . out : bin_arbiter_rd_mosi   (latency: 1)
+  -- .     : bin_arbiter_rd_miso   (latency: 2)
+  -- .     : bin_arbiter_wr_mosi   (latency: 4)
   -----------------------------------------------------------------------------
-  nxt_bin_arbiter_wr_mosi <= bin_writer_mosi; --TODO - The rd and wr mosi should not have the same address.          v met 2 cycles rd mag, met 3 cycles niet, dus klopt dit wel?, moet hier niet bin_reader_mosi_pp staan? --AND !(A=B)
-  nxt_bin_arbiter_rd_mosi.rd <= bin_reader_mosi.rd WHEN (bin_reader_mosi.address /= prev_bin_reader_mosi.address AND bin_reader_mosi.address /= bin_reader_mosi_pp.address AND NOT(bin_reader_mosi.address = bin_reader_mosi_ppp.address) ) 
-                                                         -- AND sync_detect='0')
-                                                   OR (init_phase = '1') ELSE '0';                                                                                       -- bin_writer_mosi(adress 3cycles ago?) .address when .rd='1' ????
+  nxt_bin_arbiter_wr_mosi <= bin_writer_mosi;
+  -- Read RAM when subsequent addresses are not the same, when there is no toggle detected and only when the same address is not going to be written to. When a sync is detected don't read in the old RAM block.
+  nxt_bin_arbiter_rd_mosi.rd <= bin_reader_mosi.rd WHEN (bin_reader_mosi.address /= prev_bin_reader_mosi.address AND bin_reader_mosi.address /= bin_reader_mosi_pp.address 
+                                                         AND NOT(bin_reader_mosi.address = bin_reader_mosi_ppp.address) AND sync_detect='0')
+                                                   OR (init_phase = '1') ELSE '0';
   nxt_bin_arbiter_rd_mosi.address <= bin_reader_mosi.address;
 
-  p_bin_arbiter_mosi : PROCESS(dp_clk, dp_rst, nxt_bin_arbiter_wr_mosi, nxt_bin_arbiter_rd_mosi) IS
+  p_bin_arbiter_mosi : PROCESS(dp_clk, dp_rst) IS  --, nxt_bin_arbiter_wr_mosi, nxt_bin_arbiter_rd_mosi
   BEGIN
     IF dp_rst = '1' THEN
       bin_arbiter_wr_mosi <= c_mem_mosi_rst;
@@ -366,6 +374,12 @@ BEGIN
       bin_arbiter_rd_mosi <= nxt_bin_arbiter_rd_mosi;
     END IF;
   END PROCESS;
+  
+  -- Temporary debug data
+  ram_miso.rddata <= bin_arbiter_wr_mosi.wrdata;
+  
+  -- Make RAM data available for the bin_reader (or bin_writer)
+  bin_arbiter_rd_miso <= common_ram_r_w_0_miso;
 
 
   -----------------------------------------------------------------------------
diff --git a/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd b/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd
index 98424485a4e1ca3439959fe4098c2b610cf9aa4e..94b5895787d93f9e24bba470440a8a18b13e70a6 100644
--- a/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd
+++ b/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd
@@ -76,7 +76,7 @@ ARCHITECTURE str OF st_histogram_reg IS
 --                                  adr_w    => 1,
 --                                  dat_w    => c_word_w,
 --                                  nof_dat  => 1,
---                                  init_sl  => g_default_value);
+--                                  init_sl  => g_default_value);  
 
   
 BEGIN 
diff --git a/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd
index 8c74592e65fa4a7776fe01c12e73c17808437444..fbb57a6c0ff7b8c3037c3adad36ed70083133620 100644
--- a/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd
@@ -105,7 +105,7 @@ BEGIN
   
   
   ----------------------------------------------------------------------------
-  -- Source: counter stimuli
+  -- Source: counter stimuli 
   ----------------------------------------------------------------------------
   
   p_data : PROCESS(dp_rst, dp_clk, st_histogram_snk_in)
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
index e997850df3698990fdbd06a4a0badc7598ac386b..faad666ee4410b764b11291d621bd29abdc68728 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
@@ -29,23 +29,31 @@
 --   to generate data that can make related problems with that vissible.
 --
 --   To know if there can constantly new data be witten to the RAM blocks 
---   a simple counter is sufficient.
+--   a counter would be sufficient.
 --   
 --   Because there is a delay between requesting and writing back of data of 
---   2 cycles and it is illegal to read and write on the same adres at the 
---   same time, a special situation can happen where the addresses can toggle
---   (e.g. 0; 1; 0; 1) which causes incorrect counting. To simulate this the 
---   g_snk_in_data_sim_type can be set to 'toggle'
+--   3 cycles and it is illegal to read and write on the same adres at the 
+--   same time, there are 2 special situations that can happen. One where the 
+--   addresses can toggle (e.g. 0; 1; 0; 1) and one where a simultanious read 
+--   and write are triggered (e.g. 0; 1; 1; 0). Both would cause incorrect 
+--   counting as the address count can't be updated (written) before it's 
+--   address is requested again. Due to this the counter in st_histogram can 
+--   not be a simple counter that only counts and compares on repeating 
+--   addresses. It also has to compare on 2 and 3 cycles back - which makes 
+--   it complicated enough that it requires additional test stimuli. 
+--   To simulate with the required stimuli the g_snk_in_data_sim_type can be 
+--   set to 'counter', 'toggle', 'same rw' or a 'mix' of it.
 --
 --   Only incoming data while snk_in.valid = '1' may be counted. To keep the
 --   simulation simple there is the option to let there be some gap's in the
 --   valid data (or not) where snk_in.valid = '0' by setting the g_valid_gap 
---   to TRUE or FALSE.
+--   to 'true', 'false' or 'custom'.
 --
 -------------------------------------------------------------------------------
 
 LIBRARY IEEE, common_lib, mm_lib, dp_lib;
 USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;           -- needed by TO_UNSIGNED
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.tb_common_pkg.ALL;
@@ -59,8 +67,8 @@ ENTITY tb_st_histogram IS
     g_nof_bins             : NATURAL := 8; --8 ; 2
     g_nof_data             : NATURAL := 200;
     --g_str                  : STRING  := "freq.density";
-    g_valid_gap            : BOOLEAN := TRUE;
-    g_snk_in_data_sim_type : STRING  := "counter"  -- "counter" or "toggle" or "same rw" or "mix"
+    g_valid_gap            : STRING  := "custom"; -- "false" or "true" or "custom" --BOOLEAN := TRUE
+    g_snk_in_data_sim_type : STRING  := "same rw"  -- "counter" or "toggle" or "same rw" or "mix"
     );
 END tb_st_histogram;
 
@@ -79,6 +87,7 @@ ARCHITECTURE tb OF tb_st_histogram IS
   SIGNAL prev_unvalid           : STD_LOGIC := '0';
   SIGNAL init_phase             : STD_LOGIC := '1';
   SIGNAL toggle_start           : STD_LOGIC := '0';
+  SIGNAL pre_sync               : STD_LOGIC := '0';
   
   
   ----------------------------------------------------------------------------
@@ -87,10 +96,26 @@ ARCHITECTURE tb OF tb_st_histogram IS
   TYPE t_srw_arr IS ARRAY (NATURAL RANGE <>) OF INTEGER;
   CONSTANT c_srw_arr            : t_srw_arr := (0,0,1,1,0,0,1,2,3, 1, 2, 3, 0, 3, 3, 0, 3);
                                             --  1.2.3.4.5.6.7.8.9.10.11.12.13.14.15.16.17
+                                            --0:1.2.    3.4.               05.      06.
+                                            --1:    1.2.    3.    04.
+                                            --2:              1.     02.
+                                            --3:                1.      02.   03.04.   05.
+                                            --srw:      x.  x.     x. x. x.       x. x. u.
   
   SIGNAL srw_index_cnt          : NATURAL   := 0;
   
   
+  ----------------------------------------------------------------------------
+  -- Valid stimuli
+  ----------------------------------------------------------------------------
+  TYPE t_val_arr IS ARRAY (NATURAL RANGE <>) OF INTEGER;
+  CONSTANT c_val_arr            : t_val_arr := (1,1,1,1,0,1,1,1,1, 1, 1, 1, 1, 0, 1, 1, 1);
+                                            --  1.2.3.4.5.6.7.8.9.10.11.12.13.14.15.16.17
+  
+  SIGNAL val_index_cnt          : NATURAL   := 0;
+  SIGNAL dbg_valid              : NATURAL;
+  
+  
   ----------------------------------------------------------------------------
   -- Clocks and resets
   ----------------------------------------------------------------------------   
@@ -109,6 +134,34 @@ ARCHITECTURE tb OF tb_st_histogram IS
   SIGNAL st_histogram_snk_in : t_dp_sosi;
   
   
+  ----------------------------------------------------------------------------
+  -- Streaming Output
+  ----------------------------------------------------------------------------
+  
+  SIGNAL st_histogram_ram_miso     : t_mem_miso;
+  SIGNAL st_histogram_dbg_ram_miso : t_mem_miso;
+  
+  
+  ----------------------------------------------------------------------------
+  -- Self check array
+  ----------------------------------------------------------------------------
+  TYPE t_data_check_arr IS ARRAY (0 TO g_nof_bins) OF INTEGER;
+  SIGNAL data_check_arr         : t_data_check_arr := (OTHERS=> 0);
+                                            
+  SIGNAL check_adr               : NATURAL := 0;
+  SIGNAL prev_check_adr          : NATURAL;
+  SIGNAL nxt_check_arr_cnt       : NATURAL;
+  
+  SIGNAL st_histogram_snk_in_ppp : t_dp_sosi;
+  SIGNAL st_histogram_snk_in_pppp: t_dp_sosi;
+--  SIGNAL dbg_check_adr           :STD_LOGIC_VECTOR(g_data_w-1 DOWNTO c_adr_low); --  : NATURAL;
+  
+  SIGNAL dbg_error_location      : STD_LOGIC;
+  SIGNAL error_cnt               : NATURAL;
+  SIGNAL dbg_int_data_miso       : NATURAL;
+  SIGNAL dbg_int_data_arr        : NATURAL;
+  
+  
 BEGIN 
   
   ----------------------------------------------------------------------------
@@ -122,7 +175,7 @@ BEGIN
   
   ----------------------------------------------------------------------------
   -- Source: stimuli
-  --  st_histogram_snk_in.data    counter or toggle stimuli
+  --  st_histogram_snk_in.data    counter or toggle or same_rw stimuli
   --                     .valid   with or without gap's in valid stimuli
   --                     .sync    sync stimuli
   ---------------------------------------------------------------------------- 
@@ -162,7 +215,7 @@ BEGIN
     ELSIF g_snk_in_data_sim_type = "same rw" THEN
       IF dp_rst='1' THEN
         st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= (OTHERS=>'0');
-      ELSIF rising_edge(dp_clk) AND pre_valid='1' THEN -- AND init_phase='0'   didn't work
+      ELSIF rising_edge(dp_clk) AND pre_sync='1' THEN -- AND init_phase='0'   didn't work
         st_histogram_snk_in.data(g_data_w-1 DOWNTO c_adr_low) <= TO_UVEC(c_srw_arr(srw_index_cnt), c_adr_w); --placeholder !
         IF srw_index_cnt = c_srw_arr'LENGTH -1 THEN
           srw_index_cnt <= 0;
@@ -209,7 +262,7 @@ BEGIN
   
   p_stimuli : PROCESS
   BEGIN
-    IF g_valid_gap = FALSE THEN
+    IF g_valid_gap = "false" THEN
     
       -- initializing
       st_histogram_snk_in.sync <= '0';
@@ -233,13 +286,15 @@ BEGIN
       tb_end <= '1';
       WAIT;
       
-    ELSIF g_valid_gap = TRUE THEN
+    ELSIF g_valid_gap = "true" THEN
     
       -- initializing
       st_histogram_snk_in.sync <= '0';
       st_histogram_snk_in.valid <= '0';
       WAIT UNTIL rising_edge(dp_clk);
-      FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+      FOR I IN 0 TO 8 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+      pre_sync <= '1';
+      WAIT UNTIL rising_edge(dp_clk);
       pre_valid <= '1';
       st_histogram_snk_in.valid <= '1';
       -- generating g_nof_sync-1 sync pulses with gaps in 'valid'
@@ -264,7 +319,7 @@ BEGIN
         WAIT UNTIL rising_edge(dp_clk);
         st_histogram_snk_in.valid <= '0';
         WAIT UNTIL rising_edge(dp_clk);
-        --st_histogram_snk_in.valid <= '0'; -- gap while sync
+        --st_histogram_snk_in.valid <= '0'; -- gap while sync --should not happen, impossible
         st_histogram_snk_in.sync <= '1';
         pre_valid <= '1';
         WAIT UNTIL rising_edge(dp_clk);
@@ -276,21 +331,66 @@ BEGIN
       FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
       tb_end <= '1';
       WAIT;
+      
+    ELSIF g_valid_gap = "custom" THEN
+      
+      -- initializing
+      st_histogram_snk_in.sync <= '0';
+      st_histogram_snk_in.valid <= '0';
+      WAIT UNTIL rising_edge(dp_clk);
+      FOR I IN 0 TO 8 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+      pre_sync <= '1';
+      WAIT UNTIL rising_edge(dp_clk);
+      pre_valid <= '1';
+ --     st_histogram_snk_in.valid <= '1';
+      -- generating g_nof_sync-1 sync pulses with gaps in 'valid'
+      FOR I IN 0 TO g_nof_sync-2 LOOP
+        toggle_start <= '1';
+        st_histogram_snk_in.sync <= '1';
+        st_histogram_snk_in.valid <= STD_LOGIC( TO_UNSIGNED(c_val_arr(0),1)(0) ); -- TO_UVEC(c_val_arr(0), c_adr_w); --placeholder !
+        WAIT UNTIL rising_edge(dp_clk);
+        st_histogram_snk_in.sync <= '0';
+        FOR I IN 1 TO c_val_arr'LENGTH -1 LOOP
+          st_histogram_snk_in.valid <= STD_LOGIC( TO_UNSIGNED( c_val_arr(I) ,1)(0) ); -- TO_UVEC(c_val_arr(J), c_adr_w);
+          dbg_valid <= I;
+          WAIT UNTIL rising_edge(dp_clk);
+        END LOOP;
+        proc_common_wait_some_cycles(dp_clk, (g_sync_length - (c_val_arr'LENGTH -2) )); --the -2 has to be ditched as the sync happens 2 cycles to soon
+      END LOOP;
+      -- ending
+      FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+      tb_end <= '1';
+      WAIT;
     END IF;
   END PROCESS;
   
   
   
+--  p_mm_stimuli : PROCESS --(st_histogram_snk_in.sync)
+--  BEGIN
+--    st_histogram_ram_mosi <= c_mem_mosi_rst;  --.address(c_adr_w-1 DOWNTO 0) <= (OTHERS=>'0');
+--    WAIT UNTIL st_histogram_snk_in.sync = '1';
+--    -- wait till one RAM block is written
+--    FOR I IN 0 TO (g_sync_length) LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+--    -- wait for some more cycles
+--    FOR I IN 0 TO 2 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+--    -- read all bins
+--    FOR I IN 0 TO g_nof_bins-1 LOOP
+--      proc_mem_mm_bus_rd(I, dp_clk, st_histogram_ram_mosi);
+--      proc_common_wait_some_cycles(dp_clk, 1);
+--    END LOOP;
+--  END PROCESS;
+  
   ----------------------------------------------------------------------------
   -- DUT: Device Under Test
   ----------------------------------------------------------------------------
   
-  u_st_histogram : ENTITY work.st_histogram_8_april
+  u_st_histogram : ENTITY work.st_histogram --_8_april
   GENERIC MAP(
-    g_in_data_w  => g_data_w,
-    g_nof_bins   => g_nof_bins,
-    g_nof_data   => g_nof_data
-    --g_str        => g_str
+    g_in_data_w         => g_data_w,
+    g_nof_bins          => g_nof_bins,
+    g_nof_data          => g_nof_data,
+    g_ram_miso_sim_mode => FALSE         -- TRUE
   )
   PORT MAP (
     dp_rst       => dp_rst,
@@ -300,8 +400,141 @@ BEGIN
     snk_in       => st_histogram_snk_in,
   
     -- Memory Mapped
-    ram_mosi     => c_mem_mosi_rst,-- sla_in_
-    ram_miso     => OPEN -- sla_out_
+    sla_in_ram_mosi     => c_mem_mosi_rst,-- sla_in_
+    sla_out_ram_miso     => st_histogram_ram_miso, --OPEN -- sla_out_
+    dbg_ram_miso        => st_histogram_dbg_ram_miso
   );
   
+  
+  
+  ----------------------------------------------------------------------------
+  -- Selfcheck:
+  --  The selfcheck is done by counting the adresses created from 3 cycles 
+  --  delayed snk_in data into an address separated array (when in the array, 
+  --  the data is 4 cycles delayed). This data is used as reference for 
+  --  comparing it with the data written into a RAM block in st_histogram. 
+  --  Because the data in st_histogram is written 4 cycles later than it got 
+  --  in, both data are in sync and can be compared directly. 
+  --  When the data is valid but is not the same as the reference data the 
+  --  debug signal dbg_error_location becomes '1' so the location can be 
+  --  easily spotted in the wave window and a report is made.
+  ----------------------------------------------------------------------------
+  
+  
+  u_dp_pipeline_st_histogram_snk_in_3_cycle : ENTITY dp_lib.dp_pipeline
+  GENERIC MAP (
+    g_pipeline   => 3  -- 0 for wires, > 0 for registers, 
+  )
+  PORT MAP (
+    rst          => dp_rst,
+    clk          => dp_clk,
+    snk_in       => st_histogram_snk_in,
+    src_out      => st_histogram_snk_in_ppp
+  );
+  
+  u_dp_pipeline_st_histogram_snk_in_4_cycle : ENTITY dp_lib.dp_pipeline
+  GENERIC MAP (
+    g_pipeline   => 4  -- 0 for wires, > 0 for registers, 
+  )
+  PORT MAP (
+    rst          => dp_rst,
+    clk          => dp_clk,
+    snk_in       => st_histogram_snk_in,
+    src_out      => st_histogram_snk_in_pppp
+  );
+  
+  ---------------------------------------
+  -- create address from the source data 
+  check_adr <= TO_UINT( st_histogram_snk_in_ppp.data(g_data_w-1 DOWNTO c_adr_low) );
+--  dbg_check_adr <= st_histogram_snk_in_ppp.data(g_data_w -1 DOWNTO c_adr_low);
+  
+  p_prev_check_adr : PROCESS (dp_rst, dp_clk, check_adr)
+  BEGIN
+    IF dp_rst='1' THEN
+      prev_check_adr <= 0;
+    ELSIF rising_edge(dp_clk) THEN
+      prev_check_adr <= check_adr;
+    END IF;
+  END PROCESS;
+  
+  -----------------------------
+  -- when valid increase array based on address 
+  nxt_check_arr_cnt <= data_check_arr(check_adr) + 1 WHEN st_histogram_snk_in_ppp.valid = '1' ELSE data_check_arr(check_adr);
+  
+  
+  --------------------
+  -- filling the array
+  p_cumulate_testdata : PROCESS (dp_rst, dp_clk, nxt_check_arr_cnt, check_adr, st_histogram_snk_in_ppp.sync) --misses prev_check_adr
+  BEGIN 
+    --PROCESS
+    --c_data_check_arr(check_adr) <= nxt_check_arr_cnt;
+    IF dp_rst='1' THEN
+    data_check_arr(0 TO g_nof_bins) <= (OTHERS => 0);
+    ELSIF rising_edge(dp_clk) THEN
+      --data_check_arr(prev_check_adr) <= nxt_check_arr_cnt;
+      data_check_arr(check_adr) <= nxt_check_arr_cnt; --old timing
+      IF st_histogram_snk_in_ppp.sync='1' THEN
+        data_check_arr(0 TO g_nof_bins) <= (check_adr => 1, OTHERS => 0 );  -- null except check_adr
+        --
+      END IF;
+    END IF; 
+  END PROCESS;
+  
+  ---------------------
+  -- extra dbg signals 
+  dbg_int_data_miso <= TO_UINT(st_histogram_dbg_ram_miso.rddata);
+  dbg_int_data_arr <= data_check_arr(prev_check_adr);
+  
+  ---------------------
+  -- selftest
+--  p_selfcheck : PROCESS (dp_rst, dp_clk, data_check_arr, prev_check_adr, st_histogram_dbg_ram_miso.rddata)
+--  BEGIN 
+--    --PROCESS
+--    -- compare cumulated testdata with ram_mosi
+--    
+--    --dbg_int_data_miso <= TO_UINT(st_histogram_dbg_ram_miso.rddata);
+--    --dbg_int_data_arr <= data_check_arr(check_adr);
+--    IF rising_edge(dp_clk) THEN
+--      --dbg_error_location <= '0';
+--      --dbg_int_data_miso <= TO_UINT(st_histogram_dbg_ram_miso.rddata);
+--      --dbg_int_data_arr <= data_check_arr(check_adr);
+--      IF data_check_arr(prev_check_adr) /= TO_UINT(st_histogram_dbg_ram_miso.rddata) AND st_histogram_snk_in_pppp.valid='1' THEN
+--        dbg_error_location <= '1';
+--        REPORT "The value written to the RAM is not what it should be. See signal 'dbg_int_data_arr'. The failure concerns the bin (and array) address: " &integer'image(prev_check_adr) SEVERITY ERROR;
+--        error_cnt <= error_cnt + 1;
+--      ELSE
+--        dbg_error_location <= '0';
+--      END IF;
+--    END IF;
+--
+----    IF dp_rst='1' THEN
+----    data_check_arr(0 TO g_nof_bins) <= (OTHERS => 0);
+----    ELSIF rising_edge(dp_clk) THEN
+----      data_check_arr(check_adr) <= nxt_check_arr_cnt;
+----    END IF; 
+--  END PROCESS;
+
+  
+  -- show the location of an error after a small delay (to prevent spikes) when the data written is not the same as the reference and only when the data was initially valid. Do not allow to be triggered at the testbench end.
+  dbg_error_location <= '1' AFTER c_dp_clk_period/5 WHEN ( (data_check_arr(prev_check_adr) /= TO_UINT(st_histogram_dbg_ram_miso.rddata) ) AND st_histogram_snk_in_pppp.valid='1' AND tb_end='0' ) ELSE '0';
+  ASSERT dbg_error_location='0' REPORT "The value written to the RAM is not what it should be. Comparison failed on (bin and array) address: " &integer'image(prev_check_adr) SEVERITY ERROR;
+  
+
+  --error count
+  p_count_total_error_cnt : PROCESS (dp_clk, dbg_error_location)
+  BEGIN
+    IF dp_rst='1' THEN
+      error_cnt <= 0;
+    ELSIF dbg_error_location='1' AND tb_end='0' AND rising_edge(dp_clk) THEN
+      error_cnt <= error_cnt + 1;
+    END IF;
+  END PROCESS;
+
+  p_view_total_error_cnt : PROCESS (tb_end, error_cnt)
+  BEGIN
+    IF tb_end='1' AND error_cnt>0 THEN
+      REPORT "When comparing there were " &integer'image(error_cnt) &" cycles where the value in the RAM address was not the value expected" SEVERITY ERROR;
+    END IF;
+  END PROCESS;
+  
 END tb;
diff --git a/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..15c4f2fddae29e9d2f00dd172de76c904ecff142
--- /dev/null
+++ b/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd
@@ -0,0 +1,63 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+-- 
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+-- 
+--     http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- 
+-- Author: J.W.E. Oudman
+-- Purpose:
+-- Description: 
+-- .
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY tb_tb_st_histogram IS 
+END tb_tb_st_histogram;
+
+ARCHITECTURE tb OF tb_tb_st_histogram IS
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+BEGIN
+
+-- Usage
+--   > as 8
+--   > run -all 
+--   > Testbenches are self-checking
+
+--    
+--  g_sync_length          : NATURAL := 200;
+--  g_nof_sync             : NATURAL := 3;
+--  g_data_w               : NATURAL := 4;
+--  g_nof_bins             : NATURAL := 8;
+--  g_nof_data             : NATURAL := 200;
+--  --g_str                  : STRING  := "freq.density";
+--  g_valid_gap            : STRING  := "custom";  -- "false" or "true" or "custom"
+--  g_snk_in_data_sim_type : STRING  := "same rw"  -- "counter" or "toggle" or "same rw" or "mix"
+--
+
+-- do test for different number of bins 
+u_tb_st_histogram_counter_nof_2 : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 1, 2, 200, "true"  , "counter" );
+u_tb_st_histogram_counter_nof_4 : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 2, 4, 200, "true"  , "counter" );
+u_tb_st_histogram_counter       : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 4, 8, 200, "true"  , "counter" );
+
+-- do tests for RAM delay issues
+u_tb_st_histogram_toggle        : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 4, 8, 200, "true"  , "toggle"  );
+u_tb_st_histogram_same_rw       : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 4, 8, 200, "custom", "same rw" );
+
+END tb;
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..602606e9ca5886c113d77eed0b4d81cd77b7df6d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl
@@ -0,0 +1,42 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_jesd204_180           ./work/
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx/sim"
+  vcom         "$IP_DIR/../altera_jesd204_180/sim/ip_arria10_e1sg_jesd204b_rx_altera_jesd204_180_3rumeui.vhd"   -work altera_jesd204_180
+
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+  vcom         "$IP_DIR/../altera_jesd204_180/sim/ip_arria10_e1sg_jesd204b_tx_altera_jesd204_180_too2kia.vhd"   -work altera_jesd204_180 
+
+
+ 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..fe8c51f3ddffcde0b3e41eb6d6496cc67ae77d01
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e1sg_altera_jesd204_180
+hdl_library_clause_name = altera_jesd204_180
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_jesd204_phy_180
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..dfe1bc251d98d548ed2631bbce45fe4290deab43
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl
@@ -0,0 +1,40 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_jesd204_phy_180           ./work/
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx/sim"
+  vcom         "$IP_DIR/../altera_jesd204_phy_180/sim/ip_arria10_e1sg_jesd204b_rx_altera_jesd204_phy_180_wv3zwea.vhd"   -work altera_jesd204_phy_180
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+  vcom         "$IP_DIR/../altera_jesd204_phy_180/sim/ip_arria10_e1sg_jesd204b_tx_altera_jesd204_phy_180_s336zrq.vhd"   -work altera_jesd204_phy_180
+
+
+ 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..fccfb8daffbc53e40d49e78a63fb1b15514a0dde
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e1sg_altera_jesd204_phy_180
+hdl_library_clause_name = altera_jesd204_phy_180
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_jesd204_rx_180 ip_arria10_e1sg_altera_jesd204_tx_180 ip_arria10_e1sg_altera_jesd204_phy_adapter_xs_180
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b79cb4af76f6c069a45770339109ad21610aed98
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl
@@ -0,0 +1,36 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_jesd204_phy_adapter_xs_180           ./work/
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx/sim"
+
+  vlog         "$IP_DIR/../altera_jesd204_phy_adapter_xs_180/sim/mentor/altera_jesd204_phy_adapter_xs.v"          -work altera_jesd204_phy_adapter_xs_180  
+ 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..703a6aa2e01ff24a116c47118c470aa51ef06bea
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e1sg_altera_jesd204_phy_adapter_xs_180
+hdl_library_clause_name = altera_jesd204_phy_adapter_xs_180
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f2de81ed2004834e2f781578113ce3ce24e6340e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl
@@ -0,0 +1,50 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_jesd204_rx_180           ./work/
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx/sim"
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_base.v"                -work altera_jesd204_rx_180   
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_csr.v"                 -work altera_jesd204_rx_180   
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_ctl.v"                 -work altera_jesd204_rx_180   
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_descrambler.v"         -work altera_jesd204_rx_180   
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_char_val.v"        -work altera_jesd204_rx_180   
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_cs.v"              -work altera_jesd204_rx_180   
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_data_store.v"      -work altera_jesd204_rx_180   
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_ecc_dec.v"         -work altera_jesd204_rx_180   
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_ecc_enc.v"         -work altera_jesd204_rx_180   
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_ecc_fifo.v"        -work altera_jesd204_rx_180   
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_frame_align.v"     -work altera_jesd204_rx_180   
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_fs_char_replace.v" -work altera_jesd204_rx_180   
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_lane_align.v"      -work altera_jesd204_rx_180   
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll.v"                 -work altera_jesd204_rx_180   
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_dll_wo_ecc_fifo.v"     -work altera_jesd204_rx_180   
+  vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_regmap.v"              -work altera_jesd204_rx_180   
+ 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..c780bea06580973990e2e1b303a4fdc298fbfe2e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e1sg_altera_jesd204_rx_180
+hdl_library_clause_name = altera_jesd204_rx_180
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180 ip_arria10_e1sg_altera_jesd204_rx_mlpcs_180 
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..8f3b05caff702dddd03c4895140f9ab2f6375d6d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl
@@ -0,0 +1,43 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_jesd204_rx_mlpcs_180           ./work/
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx/sim"
+
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_8b10b_dec.v"          -work altera_jesd204_rx_mlpcs_180  
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_mixed_width_dcfifo.v" -work altera_jesd204_rx_mlpcs_180  
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_pcfifo.v"             -work altera_jesd204_rx_mlpcs_180  
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_rx_mlpcs.v"           -work altera_jesd204_rx_mlpcs_180  
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_rx_pcs.v"             -work altera_jesd204_rx_mlpcs_180  
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_wa.v"                 -work altera_jesd204_rx_mlpcs_180  
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_wys_lut.v"            -work altera_jesd204_rx_mlpcs_180  
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_xn_8b10b_dec.v"       -work altera_jesd204_rx_mlpcs_180  
+ 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..14bea6845303cee00d39f819b4b1798eaeae0de8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e1sg_altera_jesd204_rx_mlpcs_180
+hdl_library_clause_name = altera_jesd204_rx_mlpcs_180
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..6886f04bce27b4e594faa0a43b734c51aad4de93
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl
@@ -0,0 +1,45 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_jesd204_tx_180           ./work/
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+
+
+  vlog         "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_base.v"          -work altera_jesd204_tx_180 
+  vlog         "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_csr.v"           -work altera_jesd204_tx_180 
+  vlog         "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_ctl.v"           -work altera_jesd204_tx_180 
+  vlog         "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_dll.v"           -work altera_jesd204_tx_180 
+  vlog         "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_regmap_opt.v"    -work altera_jesd204_tx_180 
+  vlog         "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_regmap.v"        -work altera_jesd204_tx_180 
+  vlog         "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_scrambler.v"     -work altera_jesd204_tx_180 
+
+ 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..427108eab82ca9f44e552a0771b752f5e74e7086
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e1sg_altera_jesd204_tx_180
+hdl_library_clause_name = altera_jesd204_tx_180
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180 ip_arria10_e1sg_altera_jesd204_tx_mlpcs_180 
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..95fa227480c611f04cb84ba53b1ce8af0ba06a69
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl
@@ -0,0 +1,42 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_jesd204_tx_mlpcs_180           ./work/
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+  vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_8b10b_enc.v"          -work altera_jesd204_tx_mlpcs_180  
+  vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_mixed_width_dcfifo.v" -work altera_jesd204_tx_mlpcs_180  
+  vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_pcfifo.v"             -work altera_jesd204_tx_mlpcs_180  
+  vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_tx_mlpcs.v"           -work altera_jesd204_tx_mlpcs_180  
+  vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_tx_pcs.v"             -work altera_jesd204_tx_mlpcs_180  
+  vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_wys_lut.v"            -work altera_jesd204_tx_mlpcs_180  
+  vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_xn_8b10b_enc.v"       -work altera_jesd204_tx_mlpcs_180  
+ 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..cf8d72f457987196322df731e3642000a0fddc3b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e1sg_altera_jesd204_tx_mlpcs_180
+hdl_library_clause_name = altera_jesd204_tx_mlpcs_180
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1353d920fcc1f2d3afac96c67688b5fbc0a8fc76
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl
@@ -0,0 +1,44 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+vmap  altera_reset_sequencer_180         ./work/
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/sim"
+ 
+
+  vlog     "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_controller.v"                -work altera_reset_sequencer_180 
+  vlog -sv "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_sequencer_av_csr.sv"         -work altera_reset_sequencer_180 
+  vlog -sv "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_sequencer_deglitch_main.sv"  -work altera_reset_sequencer_180 
+  vlog -sv "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_sequencer_deglitch.sv"       -work altera_reset_sequencer_180 
+  vlog -sv "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_sequencer_dlycntr.sv"        -work altera_reset_sequencer_180 
+  vlog -sv "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_sequencer_main.sv"           -work altera_reset_sequencer_180 
+  vlog -sv "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_sequencer_seq.sv"            -work altera_reset_sequencer_180 
+  vlog -sv "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_sequencer.sv"                -work altera_reset_sequencer_180 
+  vlog     "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_synchronizer.v"              -work altera_reset_sequencer_180 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..9efd3399747fde2a163f95b811613fb7b535e7d4
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e1sg_altera_reset_sequencer_180
+hdl_library_clause_name = altera_reset_sequencer_180
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
index 3de92111d3a77ab97db8a7b966c2a42b09119285..f65bebd26358236e542192a4438a76f0cd0401a0 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
@@ -2,8 +2,7 @@
 hdl_lib_name = ip_arria10_e1sg_jesd204b
 hdl_library_clause_name = ip_arria10_e1sg_jesd204b_lib
 hdl_lib_uses_synth = technology tech_pll common dp
-# hdl_lib_uses_sim = ip_arria10_e1sg_altera_jesd204_180 ip_arria10_e1sg_altera_xcvr_reset_control_180
-hdl_lib_uses_sim =
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_jesd204_180 ip_arria10_e1sg_altera_xcvr_reset_control_180 ip_arria10_e1sg_altera_iopll_180 ip_arria10_e1sg_altera_reset_sequencer_180
 hdl_lib_technology = ip_arria10_e1sg 
 
 synth_files =