diff --git a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
index 2c87641ca55b5a52ce9c4437f4849274ac674de3..567a97eff3cac97ff165a74a897ea77ec4fa7e11 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
@@ -7,7 +7,7 @@ hdl_lib_technology = ip_stratixiv
 synth_files =
     # Commented unb1_bn_capture.vhd and SOPC because only the node is reused.
     # The SOPC causes a simulation error if it not there, because it is instantiated as an entity
-    #$HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.vhd
+    #$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.vhd
     src/vhdl/unb1_bn_capture_pkg.vhd
     src/vhdl/unb1_bn_capture_input.vhd
     src/vhdl/node_unb1_bn_capture.vhd
@@ -41,7 +41,7 @@ quartus_qsf_files =
 quartus_tcl_files =
     quartus/unb1_bn_capture_pins.tcl
     
-quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.qip
+quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.qip
 
 quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
index 9368e22ad325e4676b993d61512b0b9fd1f7b785..db644b06b44f6bcd17363e2e983e7fc2f36e9148 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.vhd
     src/vhdl/node_unb1_bn_terminal_bg.vhd
     src/vhdl/unb1_bn_terminal_bg.vhd
     
@@ -31,7 +31,7 @@ quartus_qsf_files =
 quartus_tcl_files =
     quartus/unb1_bn_terminal_bg_pins.tcl
     
-quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.qip
+quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.qip
 
 quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
index 89321855be5b9591595b7b3c57d742d82ba8f64f..05d368e3ebc99d39a4bf6b963926fffe32ddb6ce 100644
--- a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
     src/vhdl/node_unb1_ddr3.vhd
     src/vhdl/mmm_unb1_ddr3.vhd
     src/vhdl/unb1_ddr3.vhd
@@ -31,7 +31,7 @@ quartus_qsf_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
 
 quartus_tcl_files =
     quartus/unb1_ddr3_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
index 5274dbde5038d22a985445aa564845bc71fbf204..8d92055e78e0a50b1ff6eb8e4c7463199d13ae1b 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =   
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.vhd
     ../../src/vhdl/node_unb1_ddr3_reorder.vhd
     ../../src/vhdl/mmm_unb1_ddr3_reorder.vhd
     ../../src/vhdl/unb1_ddr3_reorder.vhd
@@ -42,7 +42,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
     $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
     
 
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
index a9fe01c6998deaad4a2dae2b42b3fbc42d3e04fe..a995636301fc5c0a3f4b3bf534d98e5ec25d8fbc 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
 
 synth_files =   
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.vhd
     ../../src/vhdl/node_unb1_ddr3_reorder.vhd
     ../../src/vhdl/mmm_unb1_ddr3_reorder.vhd
     ../../src/vhdl/unb1_ddr3_reorder.vhd
@@ -42,7 +42,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
     $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
     
 
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
index 3deda821337e0d7909ffb96b8dc5c75c6f716e43..3c859fd55b86d0a317c5c1fcbe9d3dbec58e4b1b 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
     src/vhdl/mmm_unb1_ddr3_transpose.vhd
     src/vhdl/unb1_ddr3_transpose.vhd
     
@@ -38,8 +38,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
 
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
index 908c0f97085a4bdaa5d9fb02a1ce8d20162e681d..449b3d56363644be28435e243a124b71a3851b3e 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =   
-    $HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd
     src/vhdl/mmm_unb1_fn_terminal_db.vhd
     src/vhdl/unb1_fn_terminal_db.vhd
     
@@ -30,7 +30,7 @@ quartus_tcl_files =
     quartus/unb1_fn_terminal_db_pins.tcl
     
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_heater/hdllib.cfg b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
index 3124faa9b5ec78cd53c1007ea48847f895d0d4ee..b142a97e96336039816c7864f34c156d0c395d34 100644
--- a/boards/uniboard1/designs/unb1_heater/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_heater/qsys_unb1_heater/synthesis/qsys_unb1_heater.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_heater/qsys_unb1_heater/synthesis/qsys_unb1_heater.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt b/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt
index 7e1166a1613c72d24e1511912ce527632e674545..883ec70f72c66a37c07d1692f961fe8e4417ae53 100644
--- a/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt
+++ b/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt
@@ -37,7 +37,7 @@ run: rm -rf ~/svn/UniBoard_FP7/RadioHDL/trunk/build/*
         ../../quartus/qsys_unb1_minimal.qsys .
 
     quartus_qip_files =
-        $HDL_BUILD_DIR/quartus/unb1_minimal/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
+        $RADIOHDL_BUILD_DIR/quartus/unb1_minimal/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
 
 11. For future compilations the file qsys_unb1_minimal.qsys
     (after SOPC->QSYS it is this file: ~/RadioHDL/trunk/build/quartus/unb1_minimal/sopc_unb1_minimal.qsys)
diff --git a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
index f78ab28d3cb8808fe0e41c5887748c3b6deec7ab..83c59ab9e86d6957a7803866bc9f0a9caddf590b 100644
--- a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.vhd
     src/vhdl/qsys_unb1_minimal_pkg.vhd
     src/vhdl/mmm_unb1_minimal.vhd
     src/vhdl/unb1_minimal.vhd
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
index deb47a3d479505985aeda879aa9429b3f4affa6e..13fa7738f7019913ee5fa4b8f3ef809b8acf8f70 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
@@ -32,7 +32,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_mm_arbiter/qsys_unb1_minimal_mm_arbiter/synthesis/qsys_unb1_minimal_mm_arbiter.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_mm_arbiter/qsys_unb1_minimal_mm_arbiter/synthesis/qsys_unb1_minimal_mm_arbiter.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
index fe15d426ddfcafe3c9476aa1a7fbee75533c0bee..0cb052797c19454015e07816390d3709c3ad9125 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
index c338c16de20ea62f1a58bd30c10ea1106194e8a4..ba9098f82fc57660fba7e660a29cf2b050b0ac74 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
@@ -34,7 +34,7 @@ quartus_tcl_files =
 quartus_vhdl_files =
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal/synthesis/qsys_wo_pll_unb1_minimal.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal/synthesis/qsys_wo_pll_unb1_minimal.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
index 9bc3748356d2625dae7d81a1463fbd4ea622a099..872744005aab2a2fbfdaa602f407c791f7ab6d81 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
@@ -32,7 +32,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
 
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml
index 8680311ad77aaa9d4780b1c214c85239d87bc9d3..d9a98410b65d0737ed0dbf622a1490561b028af8 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml
@@ -9,54 +9,52 @@ fpga_description: |
         "unb1_minimal system for sopc"
 
 peripherals:
-  - peripheral_name: rom_system_info
+  - peripheral_name: unb1_board/rom_system
     slave_port_names:
         - rom_system_info
-    parameters:
-      - { name: lock_base_address,  value: 0x1000 }    
+    lock_base_address: 0x1000    
     
-  - peripheral_name: reg_system_info
+  - peripheral_name: unb1_board/system
     slave_port_names:
         - pio_system_info
-    parameters:
-      - { name: lock_base_address, value: 0x0 }    
+    lock_base_address: 0x0    
 
-  - peripheral_name: ctrl_unb1_board
+  - peripheral_name: unb1_board/ctrl_unb1_board
     slave_port_names:
         - pio_wdi
 
-  - peripheral_name: unb1_board_wdi_reg
+  - peripheral_name: unb1_board/unb1_board_wdi_reg
     slave_port_names:
         - reg_wdi
   
-  - peripheral_name: eth1g
+  - peripheral_name: eth/eth1g
     slave_port_names:
         - avs_eth_0_mms_tse
         - avs_eth_0_mms_reg
         - avs_eth_0_mms_ram
     
-  - peripheral_name: ppsh
+  - peripheral_name: ppsh/ppsh
     slave_port_names:
         - pio_pps
 
-  - peripheral_name: epcs_reg
+  - peripheral_name: epcs/epcs_reg
     slave_port_names:
         - reg_epcs
         - reg_mmdp_ctrl
         - reg_mmdp_data
         - reg_dpmm_ctrl
         - reg_dpmm_data
-    parameters:
+    parameter_overrides:
       - { name : g_sim_flash_model, value: FALSE }
 
-  - peripheral_name: remu_reg
+  - peripheral_name: remu/remu_reg
     slave_port_names:
         - reg_remu
 
-  - peripheral_name: unb1_board_sens_reg
+  - peripheral_name: unb1_board/unb1_board_sens_reg
     slave_port_names:
         - reg_unb_sens
-    parameters:
+    parameter_overrides:
       - { name : g_sim,       value: FALSE }
       - { name : g_clk_freq,  value: 125E6 }
       - { name : g_temp_high, value: 85 }
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
index f7db8733bd9c89611f906dfd740d56ecf1524ef2..0179234f75cf6f9636149ecf3334e126abf1e5d2 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v
     src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
     src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
     src/vhdl/unb1_terminal_bg_mesh_db.vhd
@@ -33,7 +33,7 @@ quartus_tcl_files =
     quartus/unb1_terminal_bg_mesh_db_pins.tcl
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.qip
 
 quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/boards/uniboard1/designs/unb1_test/doc/README b/boards/uniboard1/designs/unb1_test/doc/README
index e2fdce714481f03d9ec2e3d12e35af559ed25dd8..9939ae7eeb01e10d89cb2d4e8f644b991e6eb1d0 100644
--- a/boards/uniboard1/designs/unb1_test/doc/README
+++ b/boards/uniboard1/designs/unb1_test/doc/README
@@ -121,7 +121,7 @@ The 2nd tcl file can be created with Quartus. Here are the steps:
 - generate the IP's by running: $RADIOHDL_WORK/libraries/technology/ip_stratixiv/generate-all-ip.sh
 - Start synthesis in the Quartus GUI. Only the Analysis step!!
 - Then in Quartus click: Tools/TclScripts. 
-  Open the Tcl file: $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
+  Open the Tcl file: $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
   Click Run.
 - Then Continue synthesis with Fitter, or restart with Analysis.
 - Copy the generated build/unb1_test_ddr_MB_I_II.qsf file to ./designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_MB_I_II_pins_constraints.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
index 6cd3f1ca727cd5d7e10a62b620790d008150b61c..cd2f29bacfc8c8cb2c18b66b74074c865ca33dca 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
index 6a8245325ddcec9eb168109d0b005e22817e41a4..78d24bed859fe4c9ea2a3e876cc0430f885c0fc5 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE_tx_only/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE_tx_only/qsys_unb1_test/synthesis/qsys_unb1_test.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
index b1a6665e016758d1b7601d358415d06df72768bb..aca536d5a71877e379626af55c4ed1fd76df1160 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_1GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_1GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
index 9c83f47a8dd7256d547aaa95a00b8bc5b9a38fb8..1640cf177a84738ed038c0dd10f9740d4ed5fd6c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
@@ -40,9 +40,9 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_all/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
-    #$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_all/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    #$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
index 14de6969547a38e650fe61774ee632b2e747c5c6..64c9950b5d56a1dd6efba9ba7e6bed4281667c3c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
@@ -40,9 +40,9 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
-    #$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    #$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
index 64451014bed47872dd3176a43c4662a0b2dc3fcd..45d53b348e9277fc93173ca4a042858dc4abde73 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
@@ -41,8 +41,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
index 48f3e6132c2271b31a7f22854a61ca3f39dbfe6c..e6ab3a6e1e53b21e04aec1a6e9a7174d5fef4f69 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
@@ -40,8 +40,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
index 87fbbf48a8a68f94e071d36b8d90e392ab569ec5..c686e3dc316267ab5b53890ceccfae883da4e143 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
@@ -40,8 +40,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
index 92dd925a6646d7477110ba86703149522eaa8ccb..a82fc8400e3c133a771a001a9fb094a7ea87c32f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
@@ -40,8 +40,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
index ffb6a7e81a155d9b9c578d7bed411c916d28acf2..02712a8aa2a01190b75c7ac80886cbcb30bea360 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
@@ -40,8 +40,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
index 76ca23e4b7d50df2e4aca15005d2b06a73f53d97..e299f486007a5d3f5b81d89048b2e2f43e4a8e83 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
@@ -39,8 +39,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
index 5e10bf15e3c51ad17bf3c4ebfd9ca25b5ae84c84..2fdbe5db8cf17a85abf711380108686fdff7d491 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.v
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.v
     src/vhdl/mmm_unb1_tr_10GbE.vhd
     src/vhdl/unb1_tr_10GbE.vhd
     
@@ -36,7 +36,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.qip
 
 quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc    
diff --git a/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
index 11f2c20a13e45ae19836b57e91da128f4a3b9579..1f54bec7be4d942edf0f1e800ecdf02c42888876 100644
--- a/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
+++ b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
@@ -5,14 +5,16 @@ schema_type   : peripheral
 hdl_library_name       : unb1_board
 hdl_library_description: " This is the description for the unb1_board package "
 
+# <peripheral_group>_<peripheral_name>_<slave_name>_<slave_type>
+
 peripherals:
-  - peripheral_name: rom_system_info
+  - peripheral_name: rom_system
     slave_ports:
         # rom_system_info
-      - slave_name   : ROM_SYSTEM_INFO_REG  
+      - slave_name   : info  
         slave_type   : REG
         fields:
-          - - field_name    : field_rom_info
+          - - field_name    : info
               access_mode   : RO
               address_offset: 0x0
               number_of_fields: 1024
@@ -23,13 +25,13 @@ peripherals:
     peripheral_description: |
         " settings for rom_system_info register "
   
-  - peripheral_name: reg_system_info
+  - peripheral_name: system
     slave_ports:
         # reg_system_info
-      - slave_name   : REG_SYSTEM_INFO_REG  
+      - slave_name   : info  
         slave_type   : REG
         fields:
-          - - field_name    : field_reg_info
+          - - field_name    : info
               access_mode   : RO
               address_offset: 0x0
               number_of_fields: 32
diff --git a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
index baf6be9c0fda52ee72fe1e7846fd3228eb915c80..93e521fbb0eb01f56f60c93e98316de8c28a1e8c 100644
--- a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
@@ -34,7 +34,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2/quartus/unb2_minimal/qsys_unb2_minimal/synthesis/qsys_unb2_minimal.qip
+    $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_minimal/qsys_unb2_minimal/synthesis/qsys_unb2_minimal.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
index 11d333fa4a8db05cc7fb60edf295302958d89ec6..94a1d7a4b5dc81519f691645119e391a112bd0a6 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
@@ -56,7 +56,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2/quartus/unb2_test_10GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+    $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_10GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
index 29426ebaefb735a48310cc43360a7cd29c7fba0f..71f2e12e3d263d1c5694968f434eae78e10aaec4 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2/quartus/unb2_test_1GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+    $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_1GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
index 49cb72afe5e583f8097524505ed2cb450f1c78fd..980805831d7e154500d89e17e353eca603cb1ff6 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
@@ -61,7 +61,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2/quartus/unb2_test_all/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+    $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_all/qsys_unb2_test/synthesis/qsys_unb2_test.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
index 32d7e2b66d0d2947e519ff5b7a56a9aff8f834f3..0e60dc6cc014f1f1c2b984b2e25f322851d903a0 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
@@ -36,7 +36,7 @@ quartus_qsf_files =
     $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+    $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I/qsys_unb2_test/synthesis/qsys_unb2_test.qip
 
 quartus_tcl_files =
     quartus/unb2_test_ddr_MB_I_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
index e7f73d38757f87d359b30281b3212b11ac8f9a33..2d80edfff0b5a8c85243997e0a3afb648702ba4f 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
@@ -36,7 +36,7 @@ quartus_qsf_files =
     $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+    $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
 
 quartus_tcl_files =
     quartus/unb2_test_ddr_MB_II_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
index 4c2b30eb68315146bf192916426ea47681cfaced..69ccd15818216ce41350817cb15f3085964681e2 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
@@ -36,7 +36,7 @@ quartus_qsf_files =
     $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+    $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
 
 quartus_tcl_files =
     quartus/unb2_test_ddr_MB_I_II_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
index 93adc2818af06c42526e4a54afdf0765fa6c4239..606ea20f76bfe81095761ae13c27bce1653b5027 100644
--- a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
@@ -34,7 +34,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2a/quartus/unb2a_heater/qsys_unb2a_heater/synthesis/qsys_unb2a_heater.qip
+    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_heater/qsys_unb2a_heater/synthesis/qsys_unb2a_heater.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
index 5fdd289221b68399510cec10cc970efa064c89b8..d06919a710843ba166221d78b5ce75b37da04d48 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
@@ -34,7 +34,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2a/quartus/unb2a_minimal/qsys_unb2a_minimal/synthesis/qsys_unb2a_minimal.qip
+    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_minimal/qsys_unb2a_minimal/synthesis/qsys_unb2a_minimal.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
index 8529b7eb5db2adf22b31c8623beaa068165f4d88..22976e6d86bea2e9b8fe53ef5d166601ae00d822 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
@@ -59,7 +59,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_10GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_10GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
index 22de500f6e73eafba43ccdf186250ea7cccbb503..2baa5dd51a0ad479ea5cc15519f5bd702740f8e3 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_1GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_1GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
index bc11b4b0367248efe478d2a0c0adc26b74332445..c0fe8620de3c10a9e101470d6829d8d73ed8aff2 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
@@ -62,7 +62,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_all/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_all/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
index 79cbeb53282b4d69aaa07577b49feb5a095ce93b..5886fa177c2ae9fa67c24c3f81e271a094f9a3cc 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
@@ -37,7 +37,7 @@ quartus_qsf_files =
     $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
 
 quartus_tcl_files =
     quartus/unb2a_test_ddr_MB_I_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
index ff9a3d4b7a62ce2410a18bfc89d680a43f717bbd..e15377b23d0e850669dfedb634769c2ab1640e00 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
@@ -37,7 +37,7 @@ quartus_qsf_files =
     $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
 
 quartus_tcl_files =
     quartus/unb2a_test_ddr_MB_II_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
index 2b8b063d7e0a47e390f5ff875de6dda4b745a0ef..fd9199ad99711573ad4fd40353e70e67f06ec4ff 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
@@ -37,7 +37,7 @@ quartus_qsf_files =
     $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
 
 quartus_tcl_files =
     quartus/unb2a_test_ddr_MB_I_II_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
index cad8b1c16ab141d979202f288102f8b79ebb9e16..9d8ad666907f428c808f9f26c63ddfb733b227c9 100644
--- a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
@@ -34,31 +34,31 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/qsys_unb2b_heater/qsys_unb2b_heater.qip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/qsys_unb2b_heater/qsys_unb2b_heater.qip
 
 quartus_ip_files =
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_avs_eth_0.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_clk_0.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_cpu_0.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_jtag_uart_0.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_onchip_memory2_0.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_pps.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_system_info.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_wdi.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_ctrl.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_data.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_epcs.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_temp_sens.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_voltage_sens.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_heater.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_ctrl.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_data.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_remu.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_pmbus.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_sens.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_wdi.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_rom_system_info.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_avs_eth_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_clk_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_cpu_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_jtag_uart_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_onchip_memory2_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_pps.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_data.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_epcs.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_temp_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_voltage_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_heater.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_data.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_remu.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_pmbus.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_rom_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_timer_0.ip
     
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg b/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
index dc01f1470182e33f393473bf917dc96820c9928c..72f15b0a7355071c4a5a74cf6d1de598c7acb6b3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
@@ -34,6 +34,6 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_jesd/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_jesd/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
 
 
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg
index a357b0ac5c8ffa6ef1463cbd2ebe4368caff8858..de64e7f039857c34c7c167c537c039e51f63e04c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg
@@ -31,6 +31,6 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node0/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node0/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
 
 
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg
index d4b0c462fc557de1074c6a6147c62b7b61267b45..324205ffa195e1ea2ed9d019b1b02b9e267c5834 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg
@@ -31,6 +31,6 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node3/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node3/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
 
 
diff --git a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
index c14007d56250625c914f10559a915a752fbea450..d5eb95c53e926a6f7869e38d3a9cab1ed7b510a4 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
@@ -34,30 +34,30 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
 
 quartus_ip_files =
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
index 02c44bf134a4b7bef4135f0391c3b9bb8699f00b..cdaa8c7e78ccaf4d769d221ef8e076539d9866b4 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
@@ -60,7 +60,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_10GbE/qsys_unb2b_test/qsys_unb2b_test.qip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_10GbE/qsys_unb2b_test/qsys_unb2b_test.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg b/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg
index 385dbb59a6925d92e91c658378d1c501adf4af57..50492e0e239604b017999e3119e2f17d79d94b47 100644
--- a/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg
@@ -34,31 +34,31 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/qsys_unb2c_heater/qsys_unb2c_heater.qip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/qsys_unb2c_heater/qsys_unb2c_heater.qip
 
 quartus_ip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_avs_eth_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_clk_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_cpu_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_jtag_uart_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_onchip_memory2_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_pio_pps.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_pio_system_info.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_pio_wdi.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_dpmm_ctrl.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_dpmm_data.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_epcs.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_fpga_temp_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_fpga_voltage_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_heater.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_mmdp_ctrl.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_mmdp_data.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_remu.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_unb_pmbus.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_unb_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_wdi.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_rom_system_info.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_avs_eth_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_clk_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_cpu_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_jtag_uart_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_onchip_memory2_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_pio_pps.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_pio_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_pio_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_dpmm_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_dpmm_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_epcs.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_fpga_temp_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_fpga_voltage_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_heater.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_mmdp_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_mmdp_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_remu.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_unb_pmbus.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_unb_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_reg_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_rom_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_heater/ip/qsys_unb2c_heater/qsys_unb2c_heater_timer_0.ip
     
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg b/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg
index 74dd04a7b4c72bce1921dac14bf648ecf7da05e4..9165660bb7cad98c6d59a3d8f6560d8c565dc522 100644
--- a/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg
@@ -35,6 +35,6 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_jesd/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_jesd/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
 
 
diff --git a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg
index e580c1600a3dc583d8c5cebea32f2a9b3dfe9c2b..0030745ae318921676899b75bec3251c883b4a94 100644
--- a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg
@@ -31,6 +31,6 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_jesd_node0/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_jesd_node0/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
 
 
diff --git a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg
index 7a59e62d82807f96856aeb647449f417d9ade20e..b797e647cf1f405ec799d10f20a398cf28986c54 100644
--- a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg
@@ -31,6 +31,6 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_jesd_node3/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_jesd_node3/qsys_unb2c_jesd/qsys_unb2c_jesd.qip
 
 
diff --git a/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg b/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
index 56e214f2466ed59c77fd93296955e7e8b0818829..b41f722c594cb055c2f8b2ac85db2eb965fcb60f 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
@@ -34,30 +34,30 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/qsys_unb2c_minimal/qsys_unb2c_minimal.qip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/qsys_unb2c_minimal/qsys_unb2c_minimal.qip
 
 quartus_ip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_avs_eth_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_clk_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_cpu_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_jtag_uart_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_onchip_memory2_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_pps.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_system_info.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_wdi.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_pmbus.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_wdi.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_rom_system_info.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_avs_eth_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_clk_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_cpu_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_jtag_uart_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_onchip_memory2_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_pps.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_pmbus.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_rom_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2c/designs/unb2c_test/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/hdllib.cfg
index 9266a69e766f00034d3575f9a93c2209023eafd2..c65e272fba978549709873593eb195d3c3631ef1 100644
--- a/boards/uniboard2c/designs/unb2c_test/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/hdllib.cfg
@@ -37,63 +37,63 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/qsys_unb2c_test/qsys_unb2c_test.qip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/qsys_unb2c_test/qsys_unb2c_test.qip
 
 quartus_ip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_avs_eth_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_avs_eth_1.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_cpu_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_pmbus.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/reg_10gbase_r_24.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_avs_eth_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_avs_eth_1.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_cpu_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_pmbus.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test/ip/qsys_unb2c_test/reg_10gbase_r_24.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
index 57a240cbb1d5412bdd38aa9dba1830827c0e1fd2..62374dd103db70c4ec4d020305b77f4d5451e46c 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
@@ -57,62 +57,62 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/qsys_unb2c_test/qsys_unb2c_test.qip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/qsys_unb2c_test/qsys_unb2c_test.qip
 
 quartus_ip_files =
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_avs_eth_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_avs_eth_1.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_clk_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_cpu_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_jtag_uart_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_onchip_memory2_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_pps.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_system_info.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_wdi.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_bg_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_bg_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_bg_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_bg_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_dpmm_ctrl.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_dpmm_data.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_epcs.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_back0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_back1.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_fpga_temp_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_fpga_voltage_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_io_ddr_MB_I.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_io_ddr_MB_II.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_mmdp_ctrl.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_mmdp_data.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_remu.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_back0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_back1.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_unb_pmbus.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_unb_sens.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_wdi.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_rom_system_info.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_timer_0.ip
-    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/reg_10gbase_r_24.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_avs_eth_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_avs_eth_1.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_clk_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_cpu_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_jtag_uart_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_onchip_memory2_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_pps.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_pio_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_bg_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_bg_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_dpmm_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_dpmm_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_epcs.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_back0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_back1.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_fpga_temp_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_mmdp_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_mmdp_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_remu.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_unb_pmbus.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_unb_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_reg_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_rom_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/qsys_unb2c_test_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test_10GbE/reg_10gbase_r_24.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/init_hdl.sh b/init_hdl.sh
index 802e18c9a342001cf42f2ec80599adbd056249df..0231de181211e40e93643a5bb28c3f6b968984c1 100644
--- a/init_hdl.sh
+++ b/init_hdl.sh
@@ -48,10 +48,10 @@ echo "HDL environment will be setup for" $RADIOHDL_WORK
 
 # setup paths to build and config dir if not already defined by the user.
 export ARGS_WORK=${ARGS_WORK:-${RADIOHDL_WORK}}
-export HDL_BUILD_DIR=${HDL_BUILD_DIR:-${RADIOHDL_WORK}/build}
+export RADIOHDL_BUILD_DIR=${RADIOHDL_BUILD_DIR:-${RADIOHDL_WORK}/build}
 
 # modelsim uses this sim dir for testing
-export HDL_IOFILE_SIM_DIR=${HDL_IOFILE_SIM_DIR:-${HDL_BUILD_DIR}/sim}
+export HDL_IOFILE_SIM_DIR=${HDL_IOFILE_SIM_DIR:-${RADIOHDL_BUILD_DIR}/sim}
 if [[ ! -d "${HDL_IOFILE_SIM_DIR}" ]]; then
     echo "make sim dir"
     mkdir "${HDL_IOFILE_SIM_DIR}"
diff --git a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
index 0ac4f1ca44488f9f88f660c43fc7e67482662d23..cca9e1d6c59f63fdec3a256a14aac90d4d87515c 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
+++ b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.vhd
     src/vhdl/mmm_unb1_dp_offload.vhd
     src/vhdl/unb1_dp_offload.vhd
 
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
 
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
index 53b8ab7f7fbe2086c666d0c3b531de8fce09c795..e424ea9d5ff2530cbdd61574854fe100f054329f 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =   
-    $HDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.vhd
     src/vhdl/mmm_unb1_fn_bf.vhd
     src/vhdl/node_unb1_fn_bf.vhd    
     src/vhdl/unb1_fn_bf.vhd
@@ -31,7 +31,7 @@ quartus_tcl_files =
     quartus/unb1_fn_bf_pins.tcl
     
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
index 8850bc6d00096625d5260686a5d31d045338a5bf..04101e79bec296013ae70c6fb821b98e4a5babff 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
+++ b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.v
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.v
     src/vhdl/mmm_unb1_correlator.vhd
     src/vhdl/unb1_correlator.vhd
     
@@ -31,7 +31,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 
diff --git a/libraries/io/ddr3/hdllib.cfg b/libraries/io/ddr3/hdllib.cfg
index 6b8dd8ebd11710ed5df9e7d90a190639bd2cfc45..970529be4267e1d121cd77c32cbca7ff8485c82c 100644
--- a/libraries/io/ddr3/hdllib.cfg
+++ b/libraries/io/ddr3/hdllib.cfg
@@ -28,9 +28,9 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files =
-    $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
-    $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
-    $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
+    $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
+    $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
+    $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
 
 modelsim_compile_ip_files =
      $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
index a45392e234e98478c7c185e2fdab4c8b6252cb18..aaca3d6c3c297d021b996ec3ac83b6c7d366c6be 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
@@ -121,7 +121,7 @@ PACKAGE ddr3_pkg IS
 
   CONSTANT c_ddr3_seq : t_ddr3_seq := (64, 1, 16, 4, 0, 5);  
   
-  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
   PORT (
     pll_ref_clk                : IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -173,7 +173,7 @@ PACKAGE ddr3_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
   -- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
   PORT (
diff --git a/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg b/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
index c8bef4e2c3ba35ac5dcd190f8a40047279d5ff7e..a090ba6f04d48dfe58337b270c1ba2f97924e5e1 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
+++ b/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
@@ -26,7 +26,7 @@ quartus_qsf_files =
 quartus_tcl_files =
     quartus/unb1_eth_10g_pins.tcl
     
-quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_eth_10g/qsys_unb1_eth_10g/synthesis/qsys_unb1_eth_10g.qip
+quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_eth_10g/qsys_unb1_eth_10g/synthesis/qsys_unb1_eth_10g.qip
 
 quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/libraries/io/eth/hdllib.cfg b/libraries/io/eth/hdllib.cfg
index a9c17c9c3bbbf81bc2fed71ffd2886dce1691fe7..5c3fb5fb6901a606b031a2c9f80e7f44f51ffc10 100644
--- a/libraries/io/eth/hdllib.cfg
+++ b/libraries/io/eth/hdllib.cfg
@@ -45,10 +45,10 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files = 
-    #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
+    #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
     src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
 
 [quartus_project_file]
 quartus_copy_files =
-    #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
+    #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
     src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
\ No newline at end of file
diff --git a/libraries/technology/ddr/tech_ddr_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
index 011b01a5c1ddf503099ccd1ad3faf9d610c260c8..2284612023138e43eac50447b5d0bf100d3c70f5 100644
--- a/libraries/technology/ddr/tech_ddr_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
@@ -31,7 +31,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_stratixiv
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
   PORT (
     pll_ref_clk                : IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -83,7 +83,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
   
-  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
   -- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
   PORT (
@@ -134,7 +134,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
   COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_master IS
   PORT (
     pll_ref_clk                	: IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -186,7 +186,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
   -- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
   COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave IS
   PORT (
@@ -237,7 +237,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
   COMPONENT ip_stratixiv_ddr3_uphy_16g_dual_rank_800 IS
   PORT (
     pll_ref_clk                : IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -293,7 +293,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_arria10
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_1600.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_1600.vhd
   COMPONENT ip_arria10_ddr4_4g_1600 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -331,7 +331,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_2000.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_2000.vhd
   COMPONENT ip_arria10_ddr4_4g_2000 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -373,7 +373,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_arria10_e3sge3
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
   COMPONENT ip_arria10_e3sge3_ddr4_4g_1600 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -449,7 +449,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
   COMPONENT ip_arria10_e3sge3_ddr4_4g_2000 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -491,7 +491,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_arria10_e1sg
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
   COMPONENT ip_arria10_e1sg_ddr4_4g_1600 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -567,7 +567,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
   COMPONENT ip_arria10_e1sg_ddr4_4g_2000 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
diff --git a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
index e0b73443cc0be208405596661a9760e4b338ea98..ebbb325b5f1d9bcd5e6c1e9d2a636582b02596b6 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
@@ -32,7 +32,7 @@ PACKAGE tech_ddr_mem_model_component_pkg IS
   ------------------------------------------------------------------------------
   
   -- Manually derived VHDL entity from Verilog module alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv in:
-  -- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
+  -- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
  
   COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en IS
   GENERIC (
diff --git a/libraries/technology/hdllib.cfg b/libraries/technology/hdllib.cfg
index 02e4adb554aec475da941a60d7c76bd2fd9e58b9..09ec26b81ae0122136ebdc626accce7595a535c4 100644
--- a/libraries/technology/hdllib.cfg
+++ b/libraries/technology/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology =
 
 synth_files =
     technology_pkg.vhd
-    $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+    $RADIOHDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
 
 test_bench_files =
 
@@ -16,10 +16,10 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files = 
-    technology_select_pkg_<buildset_name>.vhd $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+    technology_select_pkg_<buildset_name>.vhd $RADIOHDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
 
 
 
 [quartus_project_file]
 quartus_copy_files =
-    technology_select_pkg_<buildset_name>.vhd $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+    technology_select_pkg_<buildset_name>.vhd $RADIOHDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
diff --git a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
index 5e5795ffacb7327cc1fb4ee1c912613d8e7685ea..44f305f0b19f6ef32390f5eeb7759da1d56089b6 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
index 43acb41dbef0fb27a4faaabf1a7ba7b8f4b8cab6..55e6320c95cadb8c1e631eb0410f1f2a1e1a8c01 100644
--- a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/ddio/compile_ip.tcl b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
index 64aba5490a1ac644abeabe6b9924bdfe195d15fa..ea28f210cf233f23315cc1a15bb5e51d5a893a41 100644
--- a/libraries/technology/ip_arria10/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
 if {$IPMODEL=="PHY"} {
 
     # This file is based on Qsys-generated file msim_setup.tcl.
-    set IP_DIR "$env(HDL_BUILD_DIR)/"
+    set IP_DIR "$env(RADIOHDL_BUILD_DIR)/"
         
     #vlib ./work/         ;# Assume library work already exists
     vmap ip_arria10_ddio_in_1_altera_gpio_core_150  ./work/
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
index 92b736708c5f397f2669fcabf33f23930c10c4fb..3e5f93390f573a7c8bd58ac855451a4e7b25d748 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
index fca54fa81397d5fe2fed6c83f43174c445ec9dc3..b83177faa5b1cb8f7914cb1aa5a44381e85bac22 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
index ec106dc119f0b937632a4dc67aff6a1c8d679b91..fb90cea0b32e3e6c69cbfa4a139c5aedb996f4ba 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
index e0de434cf68a2b36abac305aa1295db9bf676ed6..0126c5c44fc2f14013aa65c8faba90359ffef766 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
index 748f3779e18a424294a431e7b32a6f6b27d11bf9..297be0f53261b7a31f47ff06a12584e606729f1c 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
index dca56d5c3c797d693a1497ee635df4ba72270577..7987c4b82e1ccf4ae922a03fb5720433a2e5a129 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
index 7ad84ee07bff1ab5473c734fc53609797e73dec8..32237451dc2c302dfa68b638e5fb4c47de711e66 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 vmap ip_arria10_asmi_parallel_altera_asmi_parallel_150 ./work/
 
diff --git a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
index 46836c839335b0c1a9a26c7f65d7bd45452a9657..bd002e349294ad0e46ca0d6166e1e395cb9f5213 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 vmap ip_arria10_remote_update_altera_remote_update_core_150  ./work/
 vmap ip_arria10_remote_update_altera_remote_update_150       ./work/
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
index 80a62c66728cbf85d97b24a84daed153673028b7..851350a43c6ceabe3919511133fe33ecbaa440b8 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
index 8d2f641fcc8860bd127d95f956d2d36c11d49292..48d30f0d8919ce779bf57581ade5ba02a20a5242 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
index 1865ab2bb04acaf84406cb094a18d831a8c38a89..a8883cc13242d13d7bc792f260482f06265a8b70 100644
--- a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
-set IP_TBDIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_TBDIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
index 4a0011ee35ba95992d898a467858dea8cbbdcf18..6a1b1dd972a06c768520590e73255fa3830b7b84 100644
--- a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$HDL_BUILD_DIR/sim/ip_arria10_mac_10g_tb.vhd
+    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
index 05fdc5ebb71331a4d596bfed14fbfb75e1abe958..794ca94e334b853ceac9fcdbd9c00627f740e324 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
index 4df7738bdcbbb9259a5ad46048c80e97ed3fa5b6..f40fb259020f09cd98abb04e913637bf5dcc2099 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
index 5ef95c261f33071aa5333527bd61316d970b3c45..182a93de25363bf55ff70897678dabe73007b3e8 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
index 4df2e0bdecb96b8ef473082f28af7a7b09c5bf41..740989b1157c49f8004d0af278671c8d27f7e628 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
index 53e06e4de13144c7d5f04c48b2a3668b4b0b3ab3..2cf8040b19ec0dd8b4cbc9453bec69898deaa865 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
index ca650eea03c441dd28c7d1db95fe5858d2e1b2b9..e66921e0b330ede9a74a01ad878abc7446256f22 100644
--- a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
index 88558ac77859eb3864cb9657e3f8c21539db39b1..9a1b5855e11f4642ceeaf023fb66cd9a8e04fb01 100644
--- a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
index 65f55bd48db30500ebe48bf5dc93e019d032d020..58312af4c266a64f2cd82253ff649fd40604440c 100644
--- a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
index 20e438b4c19e1e7c1aca450ab6bc3e439f4c0d49..d31c8671a798c3899e189cbc4f0d354d1543cd3f 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
index e24b47eab8f26f11b277087e52befb7ed06a3160..6404a59d660ea18074ae67b68286650006d74aa0 100644
--- a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
index 0ca0862832784bf6d305b2a30503b0e76fd964ee..950a6849abb5d59accb772d44b93e8a962de330c 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
index ede7525a7c82aea577cfeb7fb9f0a8aba1d026b8..0b48cda572c2a91c92702b6908cd6530a72d1d3a 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
index 7e487453a1f8d57295d9203d6868e04cc2895739..0b9fd32f8156d0df118951b96bc7c0681f8740de 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
index 4b2d7cd58b179c78354392060a21f5d418fd7e4f..a98ab3b9500f226f4dadf17ce07fd14fe87ca004 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
index 2adc9e61a6b8385bc9d5604eeaa9ec630c71e2ef..8f4d76ddf3b165426aa469b62198d437460441a8 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
index 89dc59e26a28cf196eee9369a1512982901dc64f..a4a6db128f22937079b2c51574d5f89130519edf 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
index 97a8f992de1d36397fcd1fb8d80bbec7c3e8806a..3f4f14a00e3d83e3c7df35ee5d745895e54b6f4e 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
 # - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
index a9062836f7bbd80f60938f94448f21f763016b54..a22e115699c0346b81882fc18f14b319b1de139f 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
 # - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
index 03e7c495f2853b87e59a0b396d86a7b86da4b0db..fd90e1ac9c90092e50f26c10a30467166ed8cad4 100644
--- a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
index d2c1cac94d7a915467598e00158b226912f78133..ffa123ac217c86efde7d6de9ab386fa0714560c8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
 
 vmap alt_em10g32_180 ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg
index 0f16ed2ea08563b84db2c26831acc2ee8ce5c4ea..62619e221dc75d4ca1d7cb15e2757190ce02eba6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
index 48b8eadb18ffe222be00011f1a9d45c2e88cd8a9..564cbf1d9c3f4b62d7fadea5308fa980386646df 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 vmap  alt_mem_if_jtag_master_180            ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
index 0fdc6a880e087a7f252a0ffa7071d286d0bdc84f..b8ff2a3d814ebf9bb58af5ffc17637361cd6eae9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
 
 vmap altclkctrl_180 ./work/
   vcom  "$IP_DIR/../altclkctrl_180/sim/ip_arria10_e1sg_clkbuf_global_altclkctrl_180_uuznxiq.vhd" -work altclkctrl_180                                           
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
index d6b2ba13b801ab542ffb812499cd045bcd976b4a..e1847b95f20bbae0aeccb8b696cbc90929c3e893 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
 
 vmap altera_asmi_parallel_180 ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
index af0c7159fd9aeb9898dd708d829011e65639f3e7..eafa959867e1a4c01ae8e165643abd814f48bbb5 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
 
 vmap  altera_avalon_mm_bridge_180         ./work/                       
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
index edf94714dd03299d19c6edb8b7e661399c6246a8..25d72fb06ab3e3840de87530222a59396bf54d70 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
@@ -30,16 +30,16 @@
 #
 vmap  altera_avalon_onchip_memory2_180    ./work/
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
                       
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
index db85d837ed13d5ed34522941592c314fd4cd9a4c..f9b6566b8737158a23387418ddcfaa01f06b9103 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
                 
 vmap  altera_avalon_packets_to_master_180   ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
index ee66c060b0e7e1ca395e7dae50698d29a8bd7cdb..3f67e1b1cea65400bf28774c3e96a3d3fdffc38c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 vmap  altera_avalon_sc_fifo_180  ./work/
   vlog      "$IP_DIR/../altera_avalon_sc_fifo_180/sim/altera_avalon_sc_fifo.v"  -work altera_avalon_sc_fifo_180            
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
index 1a6e4e1ee4bb0e5a2c60a0180f457e2140ab51eb..a2defb493fec5579e0e6139e52298a412daade71 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 vmap  altera_avalon_st_bytes_to_packets_180  ./work/
                                                       
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
index 5399369f80dc9e53407739de92814c1c9cc6cd84..fa3ff32e9a3eae243226670d61ef1034926bd801 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR  "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR  "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 vmap  altera_avalon_st_packets_to_bytes_180 ./work/
    
   vlog  "$IP_DIR/../altera_avalon_st_packets_to_bytes_180/sim/altera_avalon_st_packets_to_bytes.v"  -work altera_avalon_st_packets_to_bytes_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
index 543fd5e973a9516aa61464633a21b1da9a5850c9..b28e1dcf6539c2b979be8c152b2efbc473553b95 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
@@ -29,42 +29,42 @@
 #vlib ./work/         ;# Assume library work already exist
 #
 vmap  altera_emif_180                     ./work/
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vlog      "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180_dzobyri.v"                                     -work altera_emif_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000sim"
   vlog      "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180_lwknerq.v"                                     -work altera_emif_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
   vlog      "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180_ebfu2ha.v"                                     -work altera_emif_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
   vlog      "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180_nz3mdxa.v"                                     -work altera_emif_180
 
 vmap altera_emif_arch_nf_180 ./work/
 # ddr4_4g_1600
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_io_aux.sv"             -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y.sv"                    -work altera_emif_arch_nf_180
 
 # ddr4_4g_2000
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_io_aux.sv"             -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy.sv"                    -work altera_emif_arch_nf_180
 
 # ddr4_8g_1600
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_io_aux.sv"             -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi.sv"                    -work altera_emif_arch_nf_180
 
 # ddr4_8g_2400
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_io_aux.sv"             -work altera_emif_arch_nf_180
@@ -110,52 +110,52 @@ set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_d
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/io_12_lane__nf5es_abphy.sv"                                                         -work altera_emif_arch_nf_180
 
 vmap  altera_emif_cal_slave_nf_180        ./work/
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_efslyyq.v"           -work altera_emif_cal_slave_nf_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_efslyyq.v"           -work altera_emif_cal_slave_nf_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_efslyyq.v"           -work altera_emif_cal_slave_nf_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_efslyyq.v"           -work altera_emif_cal_slave_nf_180
 
 vmap  altera_reset_controller_180         ./work/
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vlog      "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_controller.v"                                               -work altera_reset_controller_180
   vlog      "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_synchronizer.v"                                             -work altera_reset_controller_180
 
 vmap  altera_mm_interconnect_180          ./work/
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_ibrpcbq.vhd"             -work altera_mm_interconnect_180
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_mtvmp4i.vhd"             -work altera_mm_interconnect_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
 
 vmap  altera_avalon_onchip_memory2_180    ./work/
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
 
 
 vmap  altera_avalon_mm_bridge_180         ./work/
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vlog      "$IP_DIR/../altera_avalon_mm_bridge_180/sim/altera_avalon_mm_bridge.v"  -work altera_avalon_mm_bridge_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
index 15a326cec8dafbcca19edd4ae0e243717e06c3b6..64ca0f6eeadf453a5e77a3f6d7e01e05987ffac8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
@@ -30,28 +30,28 @@
 
 vmap altera_emif_arch_nf_180 ./work/
 # ddr4_4g_1600
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_io_aux.sv"             -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y.sv"                    -work altera_emif_arch_nf_180
 
 # ddr4_4g_2000
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_io_aux.sv"             -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy.sv"                    -work altera_emif_arch_nf_180
 
 # ddr4_8g_1600
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_io_aux.sv"             -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi.sv"                    -work altera_emif_arch_nf_180
 
 # ddr4_8g_2400
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_io_aux.sv"             -work altera_emif_arch_nf_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg
index b999c7f23026b67692ab403e47a1226f16a93b93..6a6fb2b5794a0f12129400737b18c42dc5fb34c1 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
index 385052319b67e2009b1716c5e17db4df155d65a6..096a6b31306261ef5d5bca80a5ac8ebdc7d9972c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
@@ -30,16 +30,16 @@
 #
 
 vmap  altera_emif_cal_slave_nf_180        ./work/
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_efslyyq.v"           -work altera_emif_cal_slave_nf_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_efslyyq.v"           -work altera_emif_cal_slave_nf_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_efslyyq.v"           -work altera_emif_cal_slave_nf_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
   vlog      "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_efslyyq.v"           -work altera_emif_cal_slave_nf_180
 
                                                       
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
index a5c3c36590b3094a82f565e9245dee42e7ecbd76..cff47b359f6891ed690a27c43d6451c3d446f064 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
@@ -31,10 +31,10 @@
 vmap  altera_eth_tse_180                     ./work/
 
 # tse_sgmii_gx
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
 vcom         "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180_dm7dxyq.vhd"            -work altera_eth_tse_180     
 
 # tse_sgmii_lvds
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
 vcom         "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180_zsww75y.vhd"          -work altera_eth_tse_180                   
             
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
index ebfe3676cb19cb08a431b9203e96a6590c0d6bfe..9f48b1b749250a738f695bb7ce7bc2c69f59118d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
@@ -28,6 +28,6 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
 vmap  altera_eth_tse_avalon_arbiter_180      ./work/
   vlog      "$IP_DIR/../altera_eth_tse_avalon_arbiter_180/sim/mentor/altera_eth_tse_avalon_arbiter.v"                                                   -work altera_eth_tse_avalon_arbiter_180  
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
index 358035beda539eb04f5474b0b081a44f89b8bf16..7253272d7084058511d59a5d0af08740a7b5bc40 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
 
 vmap  altera_eth_tse_mac_180                 ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
index 7bb7d7873ed59c1df6cc54ff92de5c988dd65190..325af551d7de32b53e49add90339e834acc14c18 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
 vmap  altera_eth_tse_nf_lvds_terminator_180 ./work/
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
index 01f18f57979d83e0f571442af961ae5312ee8a2a..15cf56df5c4669ec66a27e29622bdb5898b2b7bc 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
 
 vmap  altera_eth_tse_nf_phyip_terminator_180 ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
index 5f0cbdfbe7f9ec6e8e393ea20b8a4590cd96e6ea..490a07462d595096e527514d0faac94024bbd17b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
     
 vmap  altera_eth_tse_pcs_pma_nf_lvds_180    ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
index c5d8719befd1072ee3d2bd73432fe5b382afa189..55ca36b48bc56676a2f54a39c67217684a57ad27 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
 
               
 vmap  altera_eth_tse_pcs_pma_nf_phyip_180    ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
index 7d2db270093e09c09dc540b0c577063d6cc9a345..c55c9c297abf87133483b340a561c94f3edeeed9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
@@ -30,12 +30,12 @@
 
 vmap  altera_iopll_180           ./work/
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
   vlog  "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk25_altera_iopll_180_fp6fpla.vo"  -work altera_iopll_180         
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
   vlog  "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk125_altera_iopll_180_abkdtja.vo" -work altera_iopll_180          
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
   vlog  "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_180_qkytlfy.vo" -work altera_iopll_180          
                                          
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
index 8a6590e8bfa054ded07453f84d72a7fb3b49ad07..1edfa6f5a67aad9f9c735fd62445047dea10d33c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 vmap  altera_ip_col_if_180 ./work/
                                               
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
index 7855db26f8e5a63f80266935f967b88efec513a8..74c891aeba6bf0dd16b62025009fe212598b2216 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 vmap  altera_jtag_dc_streaming_180          ./work/
   vlog      "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_jtag_interface.v"                                             -work altera_jtag_dc_streaming_180         
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
index 0638a7a9520818a6dc10f6621e4bd549eee72d7a..27e323677c47e105f8741a7bb15a1a7ad2d90f2b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
@@ -27,7 +27,7 @@
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
 vmap altera_lvds_180                 ./work/
   vcom         "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_og2byry.vhd"                -work altera_lvds_180  
   vcom         "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_zfbfxeq.vhd"                -work altera_lvds_180  
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
index 763b27886008cbbb58ceef4c7af44f8475861e43..c349496c4228765340b65ce927357d1c8bc0e4b9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
@@ -27,7 +27,7 @@
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
 vmap  altera_lvds_core20_180                ./work/
 
   vlog -sv  "$IP_DIR/../altera_lvds_core20_180/sim/altera_lvds_core20.sv"                                       -work altera_lvds_core20_180               
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
index 80bd106da1914b57491732edf57ce30133229073..d94285a791912268da4ba249b191284fcff83aa5 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist      
 #
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
 
 vmap  altera_merlin_master_translator_180 ./work/
         
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
index abeccdc26435224da3598c2864522aa281d814b5..5556de9e14d841053e4568950bfa4c549a6a8395 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist      
 #
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
  
 vmap  altera_merlin_slave_translator_180  ./work/
                                                       
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
index 260516ca230f890a50041bc00838d86108f880ff..2b1c5214731b4c8bbb98b4887fe4705a3dcf24b0 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
@@ -30,16 +30,16 @@
 #
                                                       
 vmap  altera_mm_interconnect_180          ./work/
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_ibrpcbq.vhd"             -work altera_mm_interconnect_180
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_mtvmp4i.vhd"             -work altera_mm_interconnect_180
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
index 4923e9411fd1cb74b2162c30701fad84431b389b..d884da7788a187319b1370e4c7af6e946d9feca8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
 
 vmap  altera_remote_update_180      ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
index 27a2935517fe106c7374ae001c78310471dcb8ea..3f761c4a642e4aaf370045f295053240950688e9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
 
 
 vmap  altera_remote_update_core_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
index 56f7ad4cbbda4691a6b9506ad554fb48c9be9d4b..072c34aed34eda1c0bd9b4e1883a46904e422a28 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist      
 #
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
  
 vmap  altera_reset_controller_180         ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
index abf16a6330d3a5ff6fe320552e9448b3621d882f..0a291e94b1ffa4e695a43cd793fa1cf539edfab9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
 
 vmap  altera_common_sv_packages           ./work/
 vmap  altera_xcvr_atx_pll_a10_180         ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
index 278e32120b0b7699dc9134174091aababe1f8232..16078458ea96afd0cb2f880fd0ee92ce1ad0688c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
 
 vmap  altera_xcvr_fpll_a10_180             ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
index 55ea004c209d891beb081b060bb31ce7764c2f02..5c4256f75c2c011ebceced00007eb7acb7b27d6b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
@@ -32,7 +32,7 @@ vmap  altera_xcvr_native_a10_180       ./work/
 vmap  altera_common_sv_packages        ./work/
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
 
 # common dependencies
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_a10_functions_h.sv"                                                               -work altera_common_sv_packages       
@@ -68,31 +68,31 @@ set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_p
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_y6b7ffi.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
 
 # phy_10gbase_r_24
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180      
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_mhfwvwa.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
 
 # phy_10gbase_r_12
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180      
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_fs3onwi.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
 
 # phy_10gbase_r_4
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180_d2amdia.sv"  -L altera_common_sv_packages -work altera_xcvr_native_a10_180     
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_d2amdia.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
 
 # phy_10gbase_r_3
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180_skxmbpy.sv"  -L altera_common_sv_packages -work altera_xcvr_native_a10_180     
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_skxmbpy.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
 
 # phy_10gbase_r
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180_nbxifma.sv"    -L altera_common_sv_packages -work altera_xcvr_native_a10_180   
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_nbxifma.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180 
 
 # tse_sgmii_gx
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_180_k23srea.sv"     -L altera_common_sv_packages -work altera_xcvr_native_a10_180            
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_k23srea.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
index 687d9bf2eb56786c3ce70397b91a7cc46b65b486..c99889b4826946bc97e0ef6eda25f2e85b688849 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
 
 vmap  altera_xcvr_reset_control_180                  ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
index 79d78a02f240dca1c415e8d0655f644126eb3838..d1c2e5c5d8fb7766f9ccff03c03eb0f1f805d928 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 vmap  channel_adapter_180                   ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
index dd0ebe9a6983d3c418dc741ba141c5c6e0a65899..de74d47a27b7611fd6c31a50270f4365e6272498 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 vmap  timing_adapter_180   ./work/
                   
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
index 3d395b250cfca9e836d1b0c2b0e1ad56f47e5551..73fa9937b39cc9564aa048bfcfa3f8c1d74cd0b3 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
 
   vcom  "$IP_DIR/ip_arria10_e1sg_clkbuf_global.vhd"                                             
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
index e4bf3a3d8940c34b163531350cf77e5c6402bdb5..322c95752d30393b5c846493dbd185c391a9840d 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_clkbuf_global/ip_arria10_e1sg_clkbuf_global.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_clkbuf_global/ip_arria10_e1sg_clkbuf_global.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
index cf358c071bf54f072d98f0b63121a4f689d0a5ec..bf653f2f16a62adc67568a085aed6b01011333d3 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
 vmap altmult_complex_180 ./work/
   vlog "$IP_DIR/../altmult_complex_180/synth/ip_arria10_e1sg_complex_mult_altmult_complex_180_nkpx3mi.v" -work altmult_complex_180
   #vlog "$IP_DIR/ip_arria10_e1sg_complex_mult_bb.v"                                                        
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
index b261fdd280e2ea5bcfc866dfa8b35250bcb56ffe..2cb2598b2ff1d9391f1789b1a6255fc6bd739319 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
index b36839e7c83697574b720f848e19297be32b82d3..5e3fcefa5ebb64853c8ee2693f32028036218fc7 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
@@ -34,7 +34,7 @@ set IPMODEL "SIM";
 if {$IPMODEL=="PHY"} { 
     # OUTDATED AND NOT USED!!
     # This file is based on Qsys-generated file msim_setup.tcl.
-    set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_in_1/sim"
+    set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_in_1/sim"
         
     #vlib ./work/         ;# Assume library work already exists
     vmap ip_arria10_ddio_in_1_altera_gpio_core_180  ./work/
@@ -46,7 +46,7 @@ if {$IPMODEL=="PHY"} {
     vcom     "$IP_DIR/ip_arria10_ddio_in_1.vhd"                                                                                               
 
 
-    set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_out_1/sim"
+    set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_out_1/sim"
 
     #vlib ./work/         ;# Assume library work already exists
     vmap ip_arria10_ddio_out_1_altera_gpio_core_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
index 049a6ef228e39ed326022ff1f0d3a95b892dd12f..6fdd643351675e042111525e1af727a64e93267e 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
@@ -18,8 +18,8 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_in_1/ip_arria10_e1sg_ddio_in_1.qip
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_out_1/ip_arria10_e1sg_ddio_out_1.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_in_1/ip_arria10_e1sg_ddio_in_1.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_out_1/ip_arria10_e1sg_ddio_out_1.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
index 45e98a1c47c1cdb750252cbc8127c4b8c522e99b..7b57f32c77761658d8555f5a962322a97d802a08 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
                
   vcom         "$IP_DIR/ip_arria10_e1sg_ddr4_4g_1600.vhd"                                                                               
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
index f881b77a856ecf14cdd998a97aeb7f399009c6a1..807580094ddcfb2df77f38e645971cf32c47594a 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
index bb05a34afe0f020702ca784f11baa36adb2ed9a8..c6034f2bd565ec0f957a3fcce1d75dd18d786a8b 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
index 1650d44f51fa3f3044d92b4f95ef255c00257cbf..2b8a534222f35b96791c2559589a67326042e0fd 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
 
               
   vcom         "$IP_DIR/ip_arria10_e1sg_ddr4_4g_2000.vhd"                                                                                       
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
index 1394d1d34b471707e8a33267468f54f99bd6207a..d5f9fe639bda2c4810f83a2e88296a4425dd190b 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
index 8b021c649079174643f4865f00e51914a5d9c997..a22ea2e96a16c47ff1d501631aaa9a10d8346d67 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
index 2cfbbd059dcf6e3019c3a096a5a80134b437337d..fbbcfe7aac13c0e04a0262d21120cd98db2afbcc 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
                     
   vcom         "$IP_DIR/ip_arria10_e1sg_ddr4_8g_1600.vhd"                                                                              
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
index 63035b8e07cf7d4c2fab84dd72af2a901f992a48..14517ed7157af9b78e7146196bb7a59e7df8e75b 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
index d7825e3efccb1b18a4fbc75e91125692ee7ddfd1..bff7f43f6487d547b5ba08de983cc04b19c503ef 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
index 2638a04129dcefb3efba4a0a34592ae7cba6381d..6655a839f81d14880840d7b9b039a945e1d917ed 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
 
   vcom         "$IP_DIR/ip_arria10_e1sg_ddr4_8g_2400.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
index e1a1ada8b9df39c2a88790b9e7c2107a134d0cdf..104e49f90dbec112dc4a55c4ee227a1317926633 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
index 35a821a428baccf96d358096efd150f4fe3a0099..b203d90d95a6e4a324cdc2b1380fc5af116b6dce 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
index a708e8034288473042353c0399da5b1e911d2580..a4c21a5083b10e01b62e4451a94e5766422c8b79 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
@@ -29,7 +29,7 @@
 vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
 
 
   vcom  "$IP_DIR/ip_arria10_e1sg_asmi_parallel.vhd"                                                                
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
index cb20b751c9200f10605bc6a094fcf85c1741da75..802d7bc9b687d0c6d345be36d44179dff86f293f 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_asmi_parallel/ip_arria10_e1sg_asmi_parallel.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_asmi_parallel/ip_arria10_e1sg_asmi_parallel.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
index 1f003afd9b87762c816f1489a7b13e2a25cbca59..d721b04349295f70c6feb364690f5fa363d657e3 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
 
  
   vcom  "$IP_DIR/ip_arria10_e1sg_remote_update.vhd"                                                                 
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
index 88fb5e8af9c9b49f57f739f9f1582b281ca95fa2..64c28833bdbc85573cfff07c1d63f99545b94319 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_remote_update/ip_arria10_e1sg_remote_update.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_remote_update/ip_arria10_e1sg_remote_update.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
index f93c3aa93962977cf4ee463ef6f74334ac921081..1c55491d25b7e57b72491e61b9262f450aa97709 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/sim"
          
   vcom   "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk125.vhd"                           
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
index 0c3631101ad1539dbe263e445c8b1fcd5246f675..9ad42d42523220226ea426fbdd7e07e353e7fe58 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
index 7d453434694e4580eae0dce1ddcac777a90d8d72..d62136904bc45e1c2a440bd325bc8bcf125a8bf0 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/sim"
 
        
   vcom         "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk200.vhd"                            
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
index aecf94dba75fa49f6bfd0abaa96016f08bcea4d1..28bf7f6a7871285ce62baa8d8848b319ce4a19aa 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
index 1c211f6ce77eab1736f2cdb2293dc4304b866453..86cfa6cac3c69e353b5a784aca3cf3bd6a80312b 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
 
      
   vcom     "$IP_DIR/ip_arria10_e1sg_mac_10g.vhd"                                                                                        
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
index 8baf093d8acfa333d161d9bb74c5255017caa205..508bbebf1f01513b700caab82607c0759bd84917 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
@@ -19,7 +19,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_mac_10g/ip_arria10_e1sg_mac_10g.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_mac_10g/ip_arria10_e1sg_mac_10g.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
index 8d098b26ceb1370b059ca79aa43962b836ce3e2e..82202caa753d96f5ef579124ae82e43b3d062924 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mult_add4/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mult_add4/sim"
 
 vmap  ip_arria10_e1sg_mult_add4 ./work/
 vmap  altera_mult_add_180       ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
index ea8fcb393b6adc0ff7a367cbc523904718395e74..0aca429ea06daa64dbeee3b3526c124b987b3c21 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
 
 
   vcom         "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r.vhd"                                                                                                  
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
index 4914557dcbf6e8011aaaabd48f793397caf55446..9af7dc8bc851932be599d09748e903f5a873853a 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
index 2736172286780eef136f59560c695e36175ecae3..4aa3d0288ed14c3bce53ac2a3c11d3913d7e008b 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
 
     
   vcom         "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_12.vhd"   
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
index ba97097939ca4de7b4a7a139c604614f9f2b37eb..0d284db59b6114f7e109e7eb08c3ff3ec0d00d57 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
index 94616624b526848a0e4b0c8717d4689323dc6a03..fa35c21f357b100a23edbea6db7b1bcf373465c3 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
 
 
   vcom         "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_24.vhd"         
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
index 6a653bed8e598ff98f9d053f348709a2ff126639..f46a87107adc6133923eabbaaff96cd4b6239de7 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
index 3a060c4715c7aba668425aa5038bd97499e30e4f..81251469c69078e91f865c2c074261af7a3a9c51 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
 
    
   vcom         "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_3.vhd"                                                                                               
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
index f63bb14398415de260495a90bd9aa70900ea1aed..bae65c01609d3ae0bf94ac6bceb8de6dfa71c83b 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
index 31257d769e70a8d1dd370da0c2fa8117d34d8af6..e52b7142990360c4c48a38be38c05d0e0d1da9a6 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
 
    
   vcom         "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_4.vhd"                                                                                               
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
index 615c1c48fa0d844ea7845145659dfdf8ca3b48e1..05e6b863a664e8947477ad9bf568462b647b486d 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
index 1343afc3b59a5e9269152b2004812ae90625603b..555bdfed731f97884e1219dd24461a6d0819c5d0 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
 
     
   vcom      "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_48.vhd"                                                                    
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
index 39e0cd631e72644f1d203e6246b3e77b332265e8..ea4dd7440b6c716e40eb8d91e646aa46a2a11fec 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
index d18342e3f5b6c088b1bf6e2fd5d7c3c7c8052276..f6712cdd63d903940460fe8a517e0d37b48f0ff0 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
    
   vcom     "$IP_DIR/ip_arria10_e1sg_pll_clk125.vhd"                                              
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
index 1770bb5f7782fc68ff8f718df218d3203306034a..5bb0972c0c04b8179ff312a03df21d2736016582 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk125/ip_arria10_e1sg_pll_clk125.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk125/ip_arria10_e1sg_pll_clk125.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
index edfbbf4c076bd1b13d4585581613c7852b6f8a5c..f7f3cec7ac4e866c30234a7afc26b74bdb89557b 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
@@ -29,5 +29,5 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
   vcom  "$IP_DIR/ip_arria10_e1sg_pll_clk200.vhd"                                           
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
index be6b835b4b71ca53fe0866975eafc68a02e34b81..d745852618bbeee287e3b2689f96251f8d822716 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk200/ip_arria10_e1sg_pll_clk200.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk200/ip_arria10_e1sg_pll_clk200.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
index 40eb599bd5eeca7d2b25ad20a2ecbd476ff9b671..710e0dcc0043d4ed1605d5433ba0a1d176171d15 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
 
      
   vcom  "$IP_DIR/ip_arria10_e1sg_pll_clk25.vhd"                                        
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
index d270a6265bc624ef99883794931b78f88e83bd5b..c06945b319b0a50b94941c2d38e3bb90993fbbae 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk25/ip_arria10_e1sg_pll_clk25.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk25/ip_arria10_e1sg_pll_clk25.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
index 054104dc07c3b24b524a7788406455f2a9fb01f3..27231003981fb24e6f906b909c4bbb1aca3d5839 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
 
        
   vcom         "$IP_DIR/ip_arria10_e1sg_pll_xgmii_mac_clocks.vhd"                              
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
index 141472385b783d24ddbaeec56d95475194a95e27..fb2761f88131214772cd9868a54bcd1b000deb87 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
index f8fb076632d1d86a5d74b02e2955fba283668de2..77ca49010cf8cdb964e013ae3a0260553f0b0a6e 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_temp_sense/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_temp_sense/sim"
 
 vmap  altera_temp_sense_180      ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
index dc7c730a2a04dd8aeceebf329166991f094349d7..71ad52e9e476160785b73d430afb8c6854a29d31 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
@@ -16,7 +16,7 @@ test_bench_files =
 
 [quartus_project_file]
 quartus_qip_files = 
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_temp_sense/ip_arria10_e1sg_temp_sense.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_temp_sense/ip_arria10_e1sg_temp_sense.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
index e62b1ca32fe1b8a4193c2430560173f2a1683a2b..fcb30bbd9025a5c32590682c384e5a89cd0d75b8 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
 
   vcom       "$IP_DIR/ip_arria10_e1sg_transceiver_pll_10g.vhd"                                                                                                    
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
index dd46f8828c49145ff271bd4e5b14337efc84f590..30c1dbc1e5e3c7ae96ab91f8dfee2fc24cb3d439 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qip
 
 
 [generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
index 11105df2aa676cf5ba385c58df0d9d1baaf61c13..076177e1677f824bd02fea3cd99eee0e0b69df54 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
 
                
   vcom         "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_1.vhd"                    
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
index 845503837a5dfe9426d87ab1bb73b5b783452931..42274baf396d77d0428e286103dfd6f66c02f127 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
index a708530bf8c518ffe2fde52eb1429107c1e0e8bc..aba40145fdc83925800ffb409387d493c517079d 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/sim"
 
   vcom         "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_12.vhd"                      
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
index 773136b36096cea98d84092d774e3d25c1db2664..ae5ebcdb13bbf401b52c605b3d643e8222956c5d 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
index 87293d4a5f12876019d2b7d5d54a5d096f152139..70970628ba950e5063873ceefa755e70f4060e9b 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/sim"
 
                 
   vcom         "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_24.vhd"                    
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
index 701ee178494a83be2a135ec4af244aacdfcae21e..6e0d258dfbf6de1499e5e57ab45b86111ad2ad31 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
index a1f71285b5e64a3f00788fa4c6b41d89ff31c8bb..64f9f0b300fa79d4a20ef439e8b5ddd23d70d403 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/sim"
                 
   vcom         "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_3.vhd"                     
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
index cd49f3f7c3dd6915594bd1429e64fc2644586c81..8a9a5c4f5f71d953174b78c3422b507622e4d9b6 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
index d8cfa66c847d5e9da0d6eb5ed42b1ed9796760f3..f939d89ec657fa800c5cd20c6dcaaa3a8bd750d9 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/sim"
                 
   vcom         "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_4.vhd"                     
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
index 665debaad2883da7b3bdea3b76a9e8fdf91a87d6..6871a530371cefb160aaf96111960e1869182062 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
index cf074f0e1289216d80eb041de92b8aa70362d851..6450d4dd24dbb605c5b4bf3e2c3fcd7e06cac3f8 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/sim"
 
                  
   vcom      "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_48.vhd"                     
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
index 50f05c573ab1ddd8830edecdb15ff1edaeaf32e1..f24fde1a35d33190f400bbe21ef804f02a4f91b0 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
index 33ff4e89d52bf16f33c80575ded3d2fa8b12e1ca..f195da292399416ce68ae5dd5610297ddcc43e21 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
 
   vcom         "$IP_DIR/ip_arria10_e1sg_tse_sgmii_gx.vhd"        
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
index 407be614316506e93eb94c72fc9431b08a1adbea..6b6ad07b4ca2a22bbe83e592a3873fc0466af76b 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
index bb52a542f9bafa95f952930ec469aad1dd88f17f..3b2fffc3b6b66c1c07faa9935a77768f3bf02ce4 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
         
   vcom         "$IP_DIR/ip_arria10_e1sg_tse_sgmii_lvds.vhd"                                                                 
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
index f4641c545e4a779fd590c6e3a595b3222c5af0cb..0496ed8bd15cfc12b6dddc52c61f9b8fca70456e 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
@@ -18,7 +18,7 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qip
 
 
 [generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
index 0d545f56085d38f564ecf515fb55d4b47b39aab2..1be59a86e78fdeefbe27c6b3750c369389304f73 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_voltage_sense/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_voltage_sense/sim"
 
 vmap  ip_arria10_e1sg_voltage_sense          ./work/
 vmap  altera_voltage_sensor_180              ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
index 31f2ef1a72c10398288456b6229f87847570601a..a6cb5882e899f8467809c7c9057056237266fd4c 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
@@ -17,7 +17,7 @@ test_bench_files =
 
 [quartus_project_file]
 quartus_qip_files = 
-    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_voltage_sense/ip_arria10_e1sg_voltage_sense.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_voltage_sense/ip_arria10_e1sg_voltage_sense.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
index 7ae5ccdb0110507c116a5516c53b54a7644de291..bf8cd80c93a7860a1697ac526a57157b151b6842 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
index 57832897c9e03dacb771638be58eac6e5f950b5e..9d3d77809588700d590519cd1596b2ab44add79d 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
index aa2dd948bc10c19bcbf6eca5f43b580cc89e8c57..bf52569332beb12035486d9477909efde4f0d22e 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
 if {$IPMODEL=="PHY"} {
 
     # This file is based on Qsys-generated file msim_setup.tcl.
-    set IP_DIR "$env(HDL_BUILD_DIR)/"
+    set IP_DIR "$env(RADIOHDL_BUILD_DIR)/"
         
     #vlib ./work/         ;# Assume library work already exists
     vmap ip_arria10_e3sge3_ddio_in_1_altera_gpio_core_151  ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
index f9daedf909c3374e88c54a2db2a5788038997cdf..e62b5e5b0ec2ca57c94a7ab5b9d13a8a9f993b0c 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
index 960d695d93ac14ac14d9fca19cb02da3dde50874..ffac688997df0844310121f869edb099a0f7b893 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
index 4958df3351a1a1f8f3802460d8e7f0321d2f2917..5af54448735656b71c72ba70c8ea9abda0030c03 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
index 9ee3836145e3eeae78859b7d60f8325a0d8d0848..c7dc9753f6703576382161215eaf38894884de9b 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
index f1b453f200164d5d78459ead9a893ce00b1db24e..9235dd757d1c734c7100d95ab966a22837ab6b6d 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
index 04c2a8b4be31e4d5f5ef249a650466322d8b90f7..50bcddb253056ba6151939404cb7a8087772998d 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
index ce6a73617cf8953e1e92e06aed99720360d50beb..6ab71a395bb7b1e3e7d06d446983253e205c110e 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
index aae9b7d9c164ae06e67a2c7f461da36003ebce98..7017bd16807f790d696cdf8165fb677c09c390bc 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
index dca4f15724202af79962351ed84c4c74b7e698ff..bdfa521c2e6ecc238bbde399fb49198e91421278 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 vmap ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151 ./work/
 
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
index 74015b629d77fa5bb93635d791d424e2c431c3e4..3ce459025cc583a84317805d0d834f9a99f92364 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 vmap ip_arria10_e3sge3_remote_update_altera_remote_update_core_151  ./work/
 vmap ip_arria10_e3sge3_remote_update_altera_remote_update_151       ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
index 7e094e9376d12c2d669bd1f866df2cc8e050d012..644fcc2174cfdc4be4fb1a61a7a39c99ff51f2bd 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
index c0daa81c16aead7d28d9c9c4a02a89d671be52e7..c74c2287408f1056c710ee8f3f4919c6b978c3ae 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
index 5567b55fb3ecb22e5b70bf65468cff275cf57dd2..652e8572667600fc7ffe8d9af75e567441a6835e 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
-set IP_TBDIR "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_TBDIR "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
index 1388ee04dd3a148a41a25eb40a1a8bdbcc28a33b..2395b80019ba2a23b3ad696cc19a94fe3f2e5310 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$HDL_BUILD_DIR/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
+    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
index 9f2c5442d710666ca8ab4049d336979fdafc104c..f4812de719ae2432daf1b2136321bbf4c5c830af 100644
--- a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
index e27cf86d7f2e8c9c5aff9ebccdeb94f396559222..bac46a302542d23df2b48e95b334e174592073bb 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
index 4d2d833dae507da920d09319c4b44fda9d976d05..845c5bc4dc96a15673a1beae9442e550c2ce0461 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
index 26ba984cb5036540586ece8045005736f2841a36..52b235c6fcc56d01e23f600b679f612c623e2a13 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
index 76743709b4c09aebff7c4cdf62d95de2aa1f831b..a1a50b1517e457f5de611dfafda1d454f0098099 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
index f80ddb5a8f5ef750d79362407a6fa7c6a1f50805..55c73ea9afa9b28c71305785104bf7c394b6fbfc 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
index cdad30ae363b2c7919319f57edf6f9ae3c05282e..0f450fb1fb2068e521e2419cf34ac571b826bce8 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
index 1e38e5900f4698bdf951883342899bdf381249e4..4596b44c787b38044a3ce96587702fc3ea42c746 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
index fed8a5ff9a11c0fb8a76aa9943bfdec3ab112af2..6b08a6749e9ad8aec693df93ea7fd05f06ae8475 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
index 10417d22caf3d49fad2250b27a92af6e1c837bd4..b165f8ec1162f64706d063d64920cf8eb4111265 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
index 350a3674c84ac54768168ceb712b6ff2a8ddb292..5453478c58970fb5e877ab1e2b8a7c492aa9725d 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
index e16ab1bb84c6316da9dfc49018ba573bc2b95a77..fb2a92dad8ae293a93969f9f5aed73cdcbe2d9b9 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
index 824d03bc0cb687920db589d5f8ea78d4f8560d98..54b0b19176acc00bc244f13a55b8f1df88066d77 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
index b674c73aa85fa7158f0b197728d48ec5b4e03671..ad26deea9322f9d42db7aa499771b957a181fabe 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
index d9cbccb13916af9d956f2cfd4599dffd5adb1e36..a1afcf294250b25a461c3a81bb59f97dd6d38eb3 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
index f2d0fa88e704a22ac8413b19035bcbfa706dfabd..fb291b27e4d4d9f54eb8a0c5e6e3635510b451f8 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
index 84ad7eb84803cc22e84de6f2107d5db4a3761297..41414481897ae78573b47195fa70475fdca94790 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
index 216ad6395efaab77b402e3772713ca874f202a96..124ced04c46847a261fd34787276c34cc47f597a 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
 # - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
index add9457301889430396ec523be3c6a3948e1ff19..f6ae1988b3bb03f0f934553df7c61505a06a108e 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
 # - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
index 090df9c5c970cda1729a1d4f14a1ad3d2b96691d..2e88d7082a8dee592125afd2206cf5ae9f94e951 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
index 59ee3539ca85a400014442074aca2f02d6ba97e3..aa484a4ee70ee2594db2f55febaeaaf99cc3d3ba 100644
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
@@ -24,7 +24,7 @@
 
 # Get the memory model fro the uphy_4g_* from the ip_stratixiv_ddr3_uphy_4g_800_master example design
 #set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design"
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_example_design
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_example_design
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
index 0cba85661da782f1018dac1256b37ce01128a5e7..0cd94954d84f08aaaa3e6f3d4fa7413a56eb60cc 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
index c62e33e6542d97c0afd5710ed102b21c46b996fb..d73de176a4e4528412132468a9617fd9acf0ba43 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
index 0130afea23dfba3cd3857bdb6b6ce45204bc2f89..182467d01b17a56aeea08094f341d59925e91b01 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
index aae001963a1666ede237e7d4a4f3879f8747cab9..f3f0232211be40a411b8f9051d31dcbc5a580d31 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
index 100507af6ac9d66860d3515cce14de9b0d6d6018..b248f5b52c5effb708991a84367db7047b3c3a13 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
index 96244d1526a14cce781676867953c8e7a7a4b5e3..16afa271530c6722b7ded9fa3a890288ece0e45e 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
index 84678948ceb14c7d67f200944ea17387669da202..3941d3de8cca0ca760403391bd31e6056403d596 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
index 6a06571581b76225f3950e55aad925a7bb8b8a8c..0e72fc7b5348808fb86070e500f3b80681c38022 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
index ca5ef73e8666aba7af7ecc6b4bb7a8088ae62929..59118cab74016c69aff32a1edb2d96647ed21cce 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
index 755278c8493e3aee82e075c5c9c660581ef38ef7..3f69d05466561abe71d506c79a3d6952a6be20b0 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
index 8133ccc7f4a321a55c1e08d79c23843be17a72b9..1a23512475600b3c92c9993885b2f546701c009a 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
@@ -24,7 +24,7 @@
 # file msim_setup.tcl.
 # tr_xaui is the first module I did this for.
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_mac_10g_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_mac_10g_sim"
 
 #vlib ./work/         ;# Assume library work already exists
 #vmap work ./work/
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
index 3318814203f8331a9e088a57d8fec68ae9cc9284..72ba6432812883235936295c64978558c0268fe9 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
@@ -27,7 +27,7 @@
 # correct compile order).
 # EK: The model files in phy_xaui_0_sim/ are suitable for all hard xaui IP variants.
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_0_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_0_sim"
 
 #vlib ./work/       ;# EK: Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
index 7e223040ac5a77da850fcf76c456371f295e9dbd..fb8eca101ffc7543a7edc6b661298de98dd06531 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
@@ -27,7 +27,7 @@
 # correct compile order). Bonus of this is also that there will be no errors
 # when making all_mod without having run the XAUI megawizard first.
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_soft_sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_soft_sim"
 
 #vlib ./work/       ;# EK: Assume library work already exists
 
diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
index fccd070a5056e9397d604d567d9f6ccb20e1d5a3..f88b2836c2344b2f226f9206d77fe4a5600ef8a1 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
@@ -52,7 +52,7 @@ PACKAGE tech_mac_10g_component_pkg IS
   -- ip_stratixiv
   ------------------------------------------------------------------------------
   
-  -- Copied from entity $HDL_BUILD_DIR/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
+  -- Copied from entity $RADIOHDL_BUILD_DIR/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
   COMPONENT ip_stratixiv_mac_10g IS
   PORT (
     csr_clk_clk                     : in  std_logic                     := '0';             --                    csr_clk.clk
diff --git a/libraries/technology/tse/tech_tse_component_pkg.vhd b/libraries/technology/tse/tech_tse_component_pkg.vhd
index 456d59f72b2b42d0e402caedd7bb3a4fc091f0fe..64cac8c994213b141addda3a35238437cc8be30b 100644
--- a/libraries/technology/tse/tech_tse_component_pkg.vhd
+++ b/libraries/technology/tse/tech_tse_component_pkg.vhd
@@ -147,7 +147,7 @@ PACKAGE tech_tse_component_pkg IS
   -- ip_arria10
   ------------------------------------------------------------------------------
   
-  -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_lvds.vhd
+  -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_lvds.vhd
   COMPONENT ip_arria10_tse_sgmii_lvds IS
   PORT (
     clk            : in  std_logic                     := '0';             -- control_port_clock_connection.clk
@@ -198,7 +198,7 @@ PACKAGE tech_tse_component_pkg IS
   END COMPONENT;
 
 
-  -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_gx.vhd
+  -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_gx.vhd
   COMPONENT ip_arria10_tse_sgmii_gx IS
   PORT (
     clk                : in  std_logic                     := '0';             -- control_port_clock_connection.clk
@@ -265,7 +265,7 @@ PACKAGE tech_tse_component_pkg IS
   -- ip_arria10_e3sge3
   ------------------------------------------------------------------------------
 
-  -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
+  -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
   COMPONENT ip_arria10_e3sge3_tse_sgmii_lvds IS
   PORT (
     reg_data_out   : out std_logic_vector(31 downto 0);                    --                  control_port.readdata
@@ -316,7 +316,7 @@ PACKAGE tech_tse_component_pkg IS
   END COMPONENT;
 
 
-  -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
+  -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
   COMPONENT ip_arria10_e3sge3_tse_sgmii_gx IS
   PORT (
     reg_data_out       : out std_logic_vector(31 downto 0);                    --                  control_port.readdata
@@ -383,7 +383,7 @@ PACKAGE tech_tse_component_pkg IS
   -- ip_arria10_e1sg
   ------------------------------------------------------------------------------
 
-  -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
+  -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
   COMPONENT ip_arria10_e1sg_tse_sgmii_lvds IS
   PORT (
     reg_data_out   : out std_logic_vector(31 downto 0);                    --                  control_port.readdata
@@ -434,7 +434,7 @@ PACKAGE tech_tse_component_pkg IS
   END COMPONENT;
 
 
-  -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
+  -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
   COMPONENT ip_arria10_e1sg_tse_sgmii_gx IS
   PORT (
     reg_data_out       : out std_logic_vector(31 downto 0);                    --                  control_port.readdata