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Commit 7f5fe56b authored by Eric Kooistra's avatar Eric Kooistra
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Added Arria10 RAM IP from ip_arria10_ram library to the tech_memory library.

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libraries/technology/memory/hdllib.cfg
+ 1
− 1
View file @ 7f5fe56b
hdl_lib_name = tech_memory
hdl_library_clause_name = tech_memory_lib
hdl_lib_uses = technology ip_stratixiv ip_arria10 ip_virtex4
hdl_lib_uses = technology ip_stratixiv ip_arria10_ram
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
......
libraries/technology/memory/tech_memory_component_pkg.vhd
+ 75
− 11
View file @ 7f5fe56b
......@@ -139,30 +139,54 @@ PACKAGE tech_memory_component_pkg IS
);
END COMPONENT;
-----------------------------------------------------------------------------
-- ip_arria10
-----------------------------------------------------------------------------
COMPONENT ip_arria10_ram_crwk_crw IS
GENERIC (
g_adr_a_w : NATURAL := 5;
g_dat_a_w : NATURAL := 32;
g_adr_b_w : NATURAL := 4;
g_dat_b_w : NATURAL := 64;
g_nof_words_a : NATURAL := 2**5;
g_nof_words_b : NATURAL := 2**4;
g_rd_latency : NATURAL := 1; -- choose 1 or 2
g_init_file : STRING := "UNUSED"
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
clk_a : IN STD_LOGIC := '1';
clk_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT ip_arria10_ram_crw_crw IS
GENERIC (
g_inferred : BOOLEAN := FALSE;
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
g_nof_words : NATURAL := 2**5;
g_rd_latency : NATURAL := 2; -- choose 1 or 2
g_rd_latency : NATURAL := 1; -- choose 1 or 2
g_init_file : STRING := "UNUSED"
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
clk_a : IN STD_LOGIC := '1';
clk_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
......@@ -170,4 +194,44 @@ PACKAGE tech_memory_component_pkg IS
);
END COMPONENT;
COMPONENT ip_arria10_ram_cr_cw IS
GENERIC (
g_inferred : BOOLEAN := FALSE;
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
g_nof_words : NATURAL := 2**5;
g_rd_latency : NATURAL := 1; -- choose 1 or 2
g_init_file : STRING := "UNUSED"
);
PORT
(
data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
rdclk : IN STD_LOGIC ;
wraddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
wrclk : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT ip_arria10_ram_r_w IS
GENERIC (
g_inferred : BOOLEAN := FALSE;
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
g_nof_words : NATURAL := 2**5;
g_rd_latency : NATURAL := 1; -- choose 1 or 2
g_init_file : STRING := "UNUSED"
);
PORT (
clk : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
rdaddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
wraddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
);
END COMPONENT;
END tech_memory_component_pkg;
libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+ 7
− 1
View file @ 7f5fe56b
......@@ -27,7 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_lib;
LIBRARY ip_virtex4_lib;
LIBRARY ip_arria10_ram_lib;
ENTITY tech_memory_ram_cr_cw IS
GENERIC (
......@@ -61,4 +61,10 @@ BEGIN
PORT MAP (data, rdaddress, rdclock, rdclocken, wraddress, wrclock, wrclocken, wren, q);
END GENERATE;
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
u0 : ip_arria10_ram_cr_cw
GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
END GENERATE;
END ARCHITECTURE;
\ No newline at end of file
libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+ 3
− 4
View file @ 7f5fe56b
......@@ -27,8 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_lib;
LIBRARY ip_arria10_lib;
LIBRARY ip_virtex4_lib;
LIBRARY ip_arria10_ram_lib;
ENTITY tech_memory_ram_crw_crw IS
GENERIC (
......@@ -71,8 +70,8 @@ BEGIN
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
u0 : ip_arria10_ram_crw_crw
GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
END ARCHITECTURE;
libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
+ 8
− 2
View file @ 7f5fe56b
......@@ -27,7 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_lib;
LIBRARY ip_virtex4_lib;
LIBRARY ip_arria10_ram_lib;
ENTITY tech_memory_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
GENERIC (
......@@ -70,4 +70,10 @@ BEGIN
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
u0 : ip_arria10_ram_crwk_crw
GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
END ARCHITECTURE;
libraries/technology/memory/tech_memory_ram_r_w.vhd
+ 9
− 3
View file @ 7f5fe56b
......@@ -27,7 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_lib;
LIBRARY ip_virtex4_lib;
LIBRARY ip_arria10_ram_lib;
ENTITY tech_memory_ram_r_w IS
GENERIC (
......@@ -58,4 +58,10 @@ BEGIN
PORT MAP (clock, enable, data, rdaddress, wraddress, wren, q);
END GENERATE;
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
u0 : ip_arria10_ram_r_w
GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
PORT MAP (clock, data, rdaddress, wraddress, wren, q);
END GENERATE;
END ARCHITECTURE;
libraries/technology/memory/tech_memory_rom_r.vhd
+ 16
− 2
View file @ 7f5fe56b
......@@ -27,7 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_lib;
LIBRARY ip_virtex4_lib;
LIBRARY ip_arria10_ram_lib;
ENTITY tech_memory_rom_r IS
GENERIC (
......@@ -54,4 +54,18 @@ BEGIN
PORT MAP (address, clock, clken, q);
END GENERATE;
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
-- use ip_arria10_ram_r_w as ROM
u0 : ip_arria10_ram_r_w
GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
PORT MAP (
clk => clock,
--data => ,
rdaddress => address,
--wraddress => ,
--wren => ,
q => q
);
END GENERATE;
END ARCHITECTURE;
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