Added global clock buffer IP

libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl

+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/clkbuf_global/generated/sim"
+
+#vlib ./work/         ;# Assume library work already exists
+
+vmap ip_arria10_clkbuf_global_altclkctrl_150 ./work/
+
+  vlog "$IP_DIR/../altclkctrl_150/sim/ip_arria10_clkbuf_global_altclkctrl_150_n6s35la.v" -work ip_arria10_clkbuf_global_altclkctrl_150
+  vcom "$IP_DIR/ip_arria10_clkbuf_global.vhd"                                                                                         

libraries/technology/ip_arria10/clkbuf_global/generate_ip.sh

+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014                                                        
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>           
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands                             
+#                                                                           
+# This program is free software: you can redistribute it and/or modify      
+# it under the terms of the GNU General Public License as published by      
+# the Free Software Foundation, either version 3 of the License, or         
+# (at your option) any later version.                                       
+#                                                                           
+# This program is distributed in the hope that it will be useful,           
+# but WITHOUT ANY WARRANTY; without even the implied warranty of            
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             
+# GNU General Public License for more details.                              
+#                                                                           
+# You should have received a copy of the GNU General Public License         
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.     
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+#   Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+#   ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_clkbuf_global.qsys \
+              --synthesis=VHDL \
+              --simulation=VHDL \
+              --output-directory=generated \
+              --allow-mixed-language-simulation

libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg

+hdl_lib_name = ip_arria10_clkbuf_global 
+hdl_library_clause_name = ip_arria10_clkbuf_global_altclkctrl_150
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+
+hdl_lib_technology = ip_arria10
+
+modelsim_compile_ip_files =
+    $RADIOHDL/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
+
+synth_files =
+    
+test_bench_files = 
+
+quartus_qip_files =
+    generated/ip_arria10_clkbuf_global.qip

libraries/technology/ip_arria10/clkbuf_global/ip_arria10_clkbuf_global.qsys

+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags="INTERNAL_COMPONENT=true"
+   categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+   }
+   element altclkctrl_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="3" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="altclkctrl_input"
+   internal="altclkctrl_0.altclkctrl_input"
+   type="conduit"
+   dir="end">
+  <port name="inclk" internal="inclk" />
+ </interface>
+ <interface
+   name="altclkctrl_output"
+   internal="altclkctrl_0.altclkctrl_output"
+   type="conduit"
+   dir="end">
+  <port name="outclk" internal="outclk" />
+ </interface>
+ <module
+   name="altclkctrl_0"
+   kind="altclkctrl"
+   version="15.0"
+   enabled="1"
+   autoexport="1">
+  <parameter name="CLOCK_TYPE" value="1" />
+  <parameter name="DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="ENA_REGISTER_MODE" value="1" />
+  <parameter name="GUI_USE_ENA" value="false" />
+  <parameter name="NUMBER_OF_CLOCKS" value="1" />
+  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>