this (temporary) debug version has epcs,remu,plls removed and tse,mm_clk

using ETH_CLK directly

boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd

@@ -304,21 +304,21 @@ BEGIN
     END GENERATE;
 
     gen_pll_dp_clk_pll: IF g_sim = FALSE GENERATE
-      u_unb2_board_clk200_pll : ENTITY work.unb2_board_clk200_pll
-      GENERIC MAP (
-        g_technology          => g_technology,
-        g_clk200_phase_shift  => g_dp_clk_phase
-      )
-      PORT MAP (
-        arst       => i_mm_rst,
-        clk200     => ext_clk200,
-        st_clk200  => dp_clk,  -- = c0
-        st_rst200  => dp_rst
-      );
+      --u_unb2_board_clk200_pll : ENTITY work.unb2_board_clk200_pll
+      --GENERIC MAP (
+      --  g_technology          => g_technology,
+      --  g_clk200_phase_shift  => g_dp_clk_phase
+      --)
+      --PORT MAP (
+      --  arst       => i_mm_rst,
+      --  clk200     => ext_clk200,
+      --  st_clk200  => dp_clk,  -- = c0
+      --  st_rst200  => dp_rst
+      --);
       
       -- Debug: uncomment these line and comment the PLL
-      --dp_clk <= ext_clk200;
-      --dp_rst <= i_mm_rst;
+      dp_clk <= ext_clk200;
+      dp_rst <= i_mm_rst;
     END GENERATE;
   END GENERATE;
 
@@ -345,26 +345,26 @@ BEGIN
   END GENERATE;
 
   gen_pll_mm_clk_pll: IF g_sim = FALSE GENERATE
-    u_unb2_board_clk125_pll : ENTITY work.unb2_board_clk125_pll
-    GENERIC MAP (
-      g_technology => g_technology
-    )
-    PORT MAP (
-      arst       => i_xo_rst,
-      clk125     => i_xo_ethclk,
-      c0_clk20   => epcs_clk,
-      c1_clk50   => clk50,
-      c2_clk100  => clk100,
-      c3_clk125  => clk125,
-      pll_locked => mm_locked
-    );
+    --u_unb2_board_clk125_pll : ENTITY work.unb2_board_clk125_pll
+    --GENERIC MAP (
+    --  g_technology => g_technology
+    --)
+    --PORT MAP (
+    --  arst       => i_xo_rst,
+    --  clk125     => i_xo_ethclk,
+    --  c0_clk20   => epcs_clk,
+    --  c1_clk50   => clk50,
+    --  c2_clk100  => clk100,
+    --  c3_clk125  => clk125,
+    --  pll_locked => mm_locked
+    --);
     
     -- Debug: uncomment these line and comment the PLL
-    --epcs_clk <= NOT epcs_clk WHEN rising_edge(clk50);
-    --clk50    <= NOT clk50    WHEN rising_edge(clk100);
-    --clk100   <= i_xo_ethclk;
-    --clk125   <= i_xo_ethclk;
-    --mm_locked <= '1';
+    epcs_clk <= NOT epcs_clk WHEN rising_edge(clk50);
+    clk50    <= NOT clk50    WHEN rising_edge(clk100);
+    clk100   <= i_xo_ethclk;
+    clk125   <= i_xo_ethclk;
+    mm_locked <= '1';
   END GENERATE;
   
   --i_tse_clk <= clk125;         -- Debug: cannot use PLL output as reference for TSE, because that does not fit
@@ -496,48 +496,48 @@ BEGIN
   -- Every design instantiates an mms_remu instance + MM status & control ports.
   -- So there is full control over the memory mapped registers to set start address of the flash 
   -- and reconfigure from that address.
-  u_mms_remu: ENTITY remu_lib.mms_remu
-  GENERIC MAP ( 
-    g_technology       => g_technology
-  )
-  PORT MAP (
-    mm_rst             => i_mm_rst,
-    mm_clk             => i_mm_clk,
-
-    epcs_clk           => epcs_clk,
-
-    remu_mosi          => reg_remu_mosi,
-    remu_miso          => reg_remu_miso
-  );
-
-  -----------------------------------------------------------------------------
-  -- EPCS
-  -----------------------------------------------------------------------------
-  u_mms_epcs: ENTITY epcs_lib.mms_epcs
-  GENERIC MAP ( 
-    g_technology       => g_technology
-  )
-  PORT MAP (
-    mm_rst             => i_mm_rst,
-    mm_clk             => i_mm_clk,
-
-    epcs_clk           => epcs_clk,
-
-    epcs_mosi          => reg_epcs_mosi,
-    epcs_miso          => reg_epcs_miso,
-
-    dpmm_ctrl_mosi     => reg_dpmm_ctrl_mosi,
-    dpmm_ctrl_miso     => reg_dpmm_ctrl_miso,
-
-    dpmm_data_mosi     => reg_dpmm_data_mosi,
-    dpmm_data_miso     => reg_dpmm_data_miso,
-
-    mmdp_ctrl_mosi     => reg_mmdp_ctrl_mosi,
-    mmdp_ctrl_miso     => reg_mmdp_ctrl_miso,
-
-    mmdp_data_mosi     => reg_mmdp_data_mosi,
-    mmdp_data_miso     => reg_mmdp_data_miso
-  );
+  --u_mms_remu: ENTITY remu_lib.mms_remu
+  --GENERIC MAP ( 
+  --  g_technology       => g_technology
+  --)
+  --PORT MAP (
+  --  mm_rst             => i_mm_rst,
+  --  mm_clk             => i_mm_clk,
+
+  --  epcs_clk           => epcs_clk,
+
+  --  remu_mosi          => reg_remu_mosi,
+  --  remu_miso          => reg_remu_miso
+  --);
+
+  -------------------------------------------------------------------------------
+  ---- EPCS
+  -------------------------------------------------------------------------------
+  --u_mms_epcs: ENTITY epcs_lib.mms_epcs
+  --GENERIC MAP ( 
+  --  g_technology       => g_technology
+  --)
+  --PORT MAP (
+  --  mm_rst             => i_mm_rst,
+  --  mm_clk             => i_mm_clk,
+
+  --  epcs_clk           => epcs_clk,
+
+  --  epcs_mosi          => reg_epcs_mosi,
+  --  epcs_miso          => reg_epcs_miso,
+
+  --  dpmm_ctrl_mosi     => reg_dpmm_ctrl_mosi,
+  --  dpmm_ctrl_miso     => reg_dpmm_ctrl_miso,
+
+  --  dpmm_data_mosi     => reg_dpmm_data_mosi,
+  --  dpmm_data_miso     => reg_dpmm_data_miso,
+
+  --  mmdp_ctrl_mosi     => reg_mmdp_ctrl_mosi,
+  --  mmdp_ctrl_miso     => reg_mmdp_ctrl_miso,
+
+  --  mmdp_data_mosi     => reg_mmdp_data_mosi,
+  --  mmdp_data_miso     => reg_mmdp_data_miso
+  --);
   
   ------------------------------------------------------------------------------
   -- PPS input