Corrected wait for /4; instead of /4 ns; Modelsim did accept it but synthesis failed on it.

libraries/technology/transceiver/sim_transceiver_gx.vhd

@@ -146,7 +146,7 @@ BEGIN
     -- detect whether tr_clk has stopped by continuously checking the toggling (cannot use WAIT UNTIL
     -- rising_edge(tr_clk) because tr_clk is the item that is checked).
     WAIT UNTIL rising_edge(tr_clk);
-    WAIT FOR c_tr_clk_period/4 ns;  -- to be sure that tr_clk='1' before starting the while TRUE loop
+    WAIT FOR c_tr_clk_period/4;  -- to be sure that tr_clk='1' before starting the while TRUE loop
     WHILE TRUE LOOP
       IF tr_clk/='1' THEN  -- level of tr_clk after rising_edge()
         EXIT;