From 7d8bbfbb498b391121a712dd1015a21b2a6de67f Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 25 Jul 2017 14:38:05 +0000
Subject: [PATCH] Corrected wait for /4; instead of /4 ns; Modelsim did accept
it but synthesis failed on it.
---
libraries/technology/transceiver/sim_transceiver_gx.vhd | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libraries/technology/transceiver/sim_transceiver_gx.vhd b/libraries/technology/transceiver/sim_transceiver_gx.vhd
index 8d70a9920e..4cc9010c40 100644
--- a/libraries/technology/transceiver/sim_transceiver_gx.vhd
+++ b/libraries/technology/transceiver/sim_transceiver_gx.vhd
@@ -146,7 +146,7 @@ BEGIN
-- detect whether tr_clk has stopped by continuously checking the toggling (cannot use WAIT UNTIL
-- rising_edge(tr_clk) because tr_clk is the item that is checked).
WAIT UNTIL rising_edge(tr_clk);
- WAIT FOR c_tr_clk_period/4 ns; -- to be sure that tr_clk='1' before starting the while TRUE loop
+ WAIT FOR c_tr_clk_period/4; -- to be sure that tr_clk='1' before starting the while TRUE loop
WHILE TRUE LOOP
IF tr_clk/='1' THEN -- level of tr_clk after rising_edge()
EXIT;
--
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