Added usage comment.

libraries/base/common/tb/vhdl/tb_common_shiftram.vhd

@@ -25,6 +25,9 @@
 -- . The DUT output counter stream is verified
 -- . Correct shift and counter values at the output with respect to the input 
 --   counter values are verified
+-- Usage:
+-- > as 10
+-- > run -all  -- signal tb_end will stop the simulation by stopping the clk
 
 LIBRARY IEEE, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;