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Commit 7b495c5a authored by Eric Kooistra's avatar Eric Kooistra
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Use user_word_order = big endian for the 36 bit counters.

parent faa5bd45
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2 merge requests!100Removed text for XSub that is now written in Confluence Subband correlator...,!76Resolve L2SDP-248
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libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
+ 113
− 113
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......@@ -85,66 +85,66 @@ peripherals:
- - {field_name: tx_frame_maxlength, mm_width: 16, access_mode: RW, address_offset: 0x6004 } # = 0x1801
- - {field_name: rx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x3000 } # = 0x0C00
- - {field_name: tx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x7000 } # = 0x1C00
- - {field_name: rx_stats_framesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3008 } # = 0x0C02
- - {field_name: tx_stats_framesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7008 } # = 0x1C02
- - {field_name: rx_stats_framesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3010 } # = 0x0C04
- - {field_name: tx_stats_framesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7010 } # = 0x1C04
- - {field_name: rx_stats_framesCRCErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3018 } # = 0x0C06
- - {field_name: tx_stats_framesCRCErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7018 } # = 0x1C06
- - {field_name: rx_stats_octetsOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3020 } # = 0x0C08
- - {field_name: tx_stats_octetsOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7020 } # = 0x1C08
- - {field_name: rx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3028 } # = 0x0C0A
- - {field_name: tx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7028 } # = 0x1C0A
- - {field_name: rx_stats_ifErrors, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3030 } # = 0x0C0C
- - {field_name: tx_stats_ifErrors, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7030 } # = 0x1C0C
- - {field_name: rx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3038 } # = 0x0C0E
- - {field_name: tx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7038 } # = 0x1C0E
- - {field_name: rx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3040 } # = 0x0C10
- - {field_name: tx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7040 } # = 0x1C10
- - {field_name: rx_stats_multicastFramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3048 } # = 0x0C12
- - {field_name: tx_stats_multicastFramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7048 } # = 0x1C12
- - {field_name: rx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3050 } # = 0x0C14
- - {field_name: tx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7050 } # = 0x1C14
- - {field_name: rx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3058 } # = 0x0C16
- - {field_name: tx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7058 } # = 0x1C16
- - {field_name: rx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3060 } # = 0x0C18
- - {field_name: tx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7060 } # = 0x1C18
- - {field_name: rx_stats_etherStatsOctets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3068 } # = 0x0C1A
- - {field_name: tx_stats_etherStatsOctets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7068 } # = 0x1C1A
- - {field_name: rx_stats_etherStatsPkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3070 } # = 0x0C1C
- - {field_name: tx_stats_etherStatsPkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7070 } # = 0x1C1C
- - {field_name: rx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3078 } # = 0x0C1E
- - {field_name: tx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7078 } # = 0x1C1E
- - {field_name: rx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3080 } # = 0x0C20
- - {field_name: tx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7080 } # = 0x1C20
- - {field_name: rx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3088 } # = 0x0C22
- - {field_name: tx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7088 } # = 0x1C22
- - {field_name: rx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3090 } # = 0x0C24
- - {field_name: tx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7090 } # = 0x1C24
- - {field_name: rx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3098 } # = 0x0C26
- - {field_name: tx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7098 } # = 0x1C26
- - {field_name: rx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30a0 } # = 0x0C28
- - {field_name: tx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70a0 } # = 0x1C28
- - {field_name: rx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30a8 } # = 0x0C2A
- - {field_name: tx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70a8 } # = 0x1C2A
- - {field_name: rx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30b0 } # = 0x0C2C
- - {field_name: tx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70b0 } # = 0x1C2C
- - {field_name: rx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30b8 } # = 0x0C2E
- - {field_name: tx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70b8 } # = 0x1C2E
- - {field_name: rx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30c0 } # = 0x0C30
- - {field_name: tx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70c0 } # = 0x1C30
- - {field_name: rx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30c8 } # = 0x0C32
- - {field_name: tx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70c8 } # = 0x1C32
- - {field_name: rx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30d0 } # = 0x0C34
- - {field_name: tx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70d0 } # = 0x1C34
- - {field_name: rx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30d8 } # = 0x0C36
- - {field_name: tx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70d8 } # = 0x1C36
- - {field_name: rx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30e0 } # = 0x0C38
- - {field_name: tx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70e0 } # = 0x1C38
- - {field_name: rx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30e8 } # = 0x0C3A
- - {field_name: tx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70e8 } # = 0x1C3A
- - {field_name: rx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30f0 } # = 0x0C3C
- - {field_name: tx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70f0 } # = 0x1C3C
- - {field_name: rx_stats_framesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3008 } # = 0x0C02
- - {field_name: tx_stats_framesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7008 } # = 0x1C02
- - {field_name: rx_stats_framesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3010 } # = 0x0C04
- - {field_name: tx_stats_framesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7010 } # = 0x1C04
- - {field_name: rx_stats_framesCRCErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3018 } # = 0x0C06
- - {field_name: tx_stats_framesCRCErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7018 } # = 0x1C06
- - {field_name: rx_stats_octetsOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3020 } # = 0x0C08
- - {field_name: tx_stats_octetsOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7020 } # = 0x1C08
- - {field_name: rx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3028 } # = 0x0C0A
- - {field_name: tx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7028 } # = 0x1C0A
- - {field_name: rx_stats_ifErrors, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3030 } # = 0x0C0C
- - {field_name: tx_stats_ifErrors, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7030 } # = 0x1C0C
- - {field_name: rx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3038 } # = 0x0C0E
- - {field_name: tx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7038 } # = 0x1C0E
- - {field_name: rx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3040 } # = 0x0C10
- - {field_name: tx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7040 } # = 0x1C10
- - {field_name: rx_stats_multicastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3048 } # = 0x0C12
- - {field_name: tx_stats_multicastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7048 } # = 0x1C12
- - {field_name: rx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3050 } # = 0x0C14
- - {field_name: tx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7050 } # = 0x1C14
- - {field_name: rx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3058 } # = 0x0C16
- - {field_name: tx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7058 } # = 0x1C16
- - {field_name: rx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3060 } # = 0x0C18
- - {field_name: tx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7060 } # = 0x1C18
- - {field_name: rx_stats_etherStatsOctets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3068 } # = 0x0C1A
- - {field_name: tx_stats_etherStatsOctets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7068 } # = 0x1C1A
- - {field_name: rx_stats_etherStatsPkts, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3070 } # = 0x0C1C
- - {field_name: tx_stats_etherStatsPkts, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7070 } # = 0x1C1C
- - {field_name: rx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3078 } # = 0x0C1E
- - {field_name: tx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7078 } # = 0x1C1E
- - {field_name: rx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3080 } # = 0x0C20
- - {field_name: tx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7080 } # = 0x1C20
- - {field_name: rx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3088 } # = 0x0C22
- - {field_name: tx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7088 } # = 0x1C22
- - {field_name: rx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3090 } # = 0x0C24
- - {field_name: tx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7090 } # = 0x1C24
- - {field_name: rx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3098 } # = 0x0C26
- - {field_name: tx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7098 } # = 0x1C26
- - {field_name: rx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30a0 } # = 0x0C28
- - {field_name: tx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70a0 } # = 0x1C28
- - {field_name: rx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30a8 } # = 0x0C2A
- - {field_name: tx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70a8 } # = 0x1C2A
- - {field_name: rx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30b0 } # = 0x0C2C
- - {field_name: tx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70b0 } # = 0x1C2C
- - {field_name: rx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30b8 } # = 0x0C2E
- - {field_name: tx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70b8 } # = 0x1C2E
- - {field_name: rx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30c0 } # = 0x0C30
- - {field_name: tx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70c0 } # = 0x1C30
- - {field_name: rx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30c8 } # = 0x0C32
- - {field_name: tx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70c8 } # = 0x1C32
- - {field_name: rx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30d0 } # = 0x0C34
- - {field_name: tx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70d0 } # = 0x1C34
- - {field_name: rx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30d8 } # = 0x0C36
- - {field_name: tx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70d8 } # = 0x1C36
- - {field_name: rx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30e0 } # = 0x0C38
- - {field_name: tx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70e0 } # = 0x1C38
- - {field_name: rx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30e8 } # = 0x0C3A
- - {field_name: tx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70e8 } # = 0x1C3A
- - {field_name: rx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30f0 } # = 0x0C3C
- - {field_name: tx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70f0 } # = 0x1C3C
- peripheral_name: nw_10GbE_eth10g # pi_nw_10GbE_eth10g.py / pi_10GbE.py
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