diff --git a/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml b/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
index 768fc28810ecf90f9c87c1f2fc03047f1c905048..170d70c599fa5b87058c27355064f5507ead6c4e 100644
--- a/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
+++ b/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
@@ -31,120 +31,120 @@ peripherals:
mm_port_description: "MAC registers"
number_of_mm_ports: g_nof_macs
fields:
- - - {field_name: rx_transfer_control, mm_width: 1, access_mode: RW, address_offset: 0x0000 } # = 0x0000
- - - {field_name: rx_transfer_status, mm_width: 1, access_mode: RO, address_offset: 0x0004 } # = 0x0001
- - - {field_name: rx_padcrc_control, mm_width: 2, access_mode: RW, address_offset: 0x0100 } # = 0x0040
- - - {field_name: rx_crccheck_control, mm_width: 2, access_mode: RW, address_offset: 0x0200 } # = 0x0080
- - - {field_name: rx_pktovrflow_error, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x0300 } # = 0x00C0
- - - {field_name: rx_pktovrflow_etherStatsDropEvents, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x0308 } # = 0x00C2
- - - {field_name: rx_lane_decoder_preamble_control, mm_width: 1, access_mode: RW, address_offset: 0x0400 } # = 0x0100
- - - {field_name: rx_preamble_inserter_control, mm_width: 1, access_mode: RW, address_offset: 0x0500 } # = 0x0140
- - - {field_name: rx_frame_control, mm_width: 20, access_mode: RW, address_offset: 0x2000 } # = 0x0800
- - - {field_name: rx_frame_maxlength, mm_width: 16, access_mode: RW, address_offset: 0x2004 } # = 0x0801
- - - {field_name: rx_frame_addr0, mm_width: 16, access_mode: RW, address_offset: 0x2008 } # = 0x0802
- - - {field_name: rx_frame_addr1, mm_width: 16, access_mode: RW, address_offset: 0x200c } # = 0x0803
- - - {field_name: rx_frame_spaddr0_0, mm_width: 16, access_mode: RW, address_offset: 0x2010 } # = 0x0804
- - - {field_name: rx_frame_spaddr0_1, mm_width: 16, access_mode: RW, address_offset: 0x2014 } # = 0x0805
- - - {field_name: rx_frame_spaddr1_0, mm_width: 16, access_mode: RW, address_offset: 0x2018 } # = 0x0806
- - - {field_name: rx_frame_spaddr1_1, mm_width: 16, access_mode: RW, address_offset: 0x201c } # = 0x0807
- - - {field_name: rx_frame_spaddr2_0, mm_width: 16, access_mode: RW, address_offset: 0x2020 } # = 0x0808
- - - {field_name: rx_frame_spaddr2_1, mm_width: 16, access_mode: RW, address_offset: 0x2024 } # = 0x0809
- - - {field_name: rx_frame_spaddr3_0, mm_width: 16, access_mode: RW, address_offset: 0x2028 } # = 0x080A
- - - {field_name: rx_frame_spaddr3_1, mm_width: 16, access_mode: RW, address_offset: 0x202c } # = 0x080B
- - - {field_name: rx_pfc_control, mm_width: 17, access_mode: RW, address_offset: 0x2060 } # = 0x0818
- - - {field_name: tx_transfer_control, mm_width: 1, access_mode: RW, address_offset: 0x4000 } # = 0x1000
- - - {field_name: tx_transfer_status, mm_width: 1, access_mode: RO, address_offset: 0x4004 } # = 0x1001
- - - {field_name: tx_padins_control, mm_width: 1, access_mode: RW, address_offset: 0x4100 } # = 0x1040
- - - {field_name: tx_crcins_control, mm_width: 2, access_mode: RW, address_offset: 0x4200 } # = 0x1080
- - - {field_name: tx_pktunderflow_error, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x4300 } # = 0x10C0
- - - {field_name: tx_preamble_control, mm_width: 1, access_mode: RW, address_offset: 0x4400 } # = 0x1100
- - - {field_name: tx_pauseframe_control, mm_width: 2, access_mode: RW, address_offset: 0x4500 } # = 0x1140
- - - {field_name: tx_pauseframe_quanta, mm_width: 16, access_mode: RW, address_offset: 0x4504 } # = 0x1141
- - - {field_name: tx_pauseframe_enable, mm_width: 1, access_mode: RW, address_offset: 0x4508 } # = 0x1142
+ - - {field_name: rx_transfer_control, mm_width: 1, access_mode: RW, address_offset: 0x0000 } # = 0x0000
+ - - {field_name: rx_transfer_status, mm_width: 1, access_mode: RO, address_offset: 0x0004 } # = 0x0001
+ - - {field_name: rx_padcrc_control, mm_width: 2, access_mode: RW, address_offset: 0x0100 } # = 0x0040
+ - - {field_name: rx_crccheck_control, mm_width: 2, access_mode: RW, address_offset: 0x0200 } # = 0x0080
+ - - {field_name: rx_pktovrflow_error, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x0300 } # = 0x00C0
+ - - {field_name: rx_pktovrflow_etherStatsDropEvents, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x0308 } # = 0x00C2
+ - - {field_name: rx_lane_decoder_preamble_control, mm_width: 1, access_mode: RW, address_offset: 0x0400 } # = 0x0100
+ - - {field_name: rx_preamble_inserter_control, mm_width: 1, access_mode: RW, address_offset: 0x0500 } # = 0x0140
+ - - {field_name: rx_frame_control, mm_width: 20, access_mode: RW, address_offset: 0x2000 } # = 0x0800
+ - - {field_name: rx_frame_maxlength, mm_width: 16, access_mode: RW, address_offset: 0x2004 } # = 0x0801
+ - - {field_name: rx_frame_addr0, mm_width: 16, access_mode: RW, address_offset: 0x2008 } # = 0x0802
+ - - {field_name: rx_frame_addr1, mm_width: 16, access_mode: RW, address_offset: 0x200c } # = 0x0803
+ - - {field_name: rx_frame_spaddr0_0, mm_width: 16, access_mode: RW, address_offset: 0x2010 } # = 0x0804
+ - - {field_name: rx_frame_spaddr0_1, mm_width: 16, access_mode: RW, address_offset: 0x2014 } # = 0x0805
+ - - {field_name: rx_frame_spaddr1_0, mm_width: 16, access_mode: RW, address_offset: 0x2018 } # = 0x0806
+ - - {field_name: rx_frame_spaddr1_1, mm_width: 16, access_mode: RW, address_offset: 0x201c } # = 0x0807
+ - - {field_name: rx_frame_spaddr2_0, mm_width: 16, access_mode: RW, address_offset: 0x2020 } # = 0x0808
+ - - {field_name: rx_frame_spaddr2_1, mm_width: 16, access_mode: RW, address_offset: 0x2024 } # = 0x0809
+ - - {field_name: rx_frame_spaddr3_0, mm_width: 16, access_mode: RW, address_offset: 0x2028 } # = 0x080A
+ - - {field_name: rx_frame_spaddr3_1, mm_width: 16, access_mode: RW, address_offset: 0x202c } # = 0x080B
+ - - {field_name: rx_pfc_control, mm_width: 17, access_mode: RW, address_offset: 0x2060 } # = 0x0818
+ - - {field_name: tx_transfer_control, mm_width: 1, access_mode: RW, address_offset: 0x4000 } # = 0x1000
+ - - {field_name: tx_transfer_status, mm_width: 1, access_mode: RO, address_offset: 0x4004 } # = 0x1001
+ - - {field_name: tx_padins_control, mm_width: 1, access_mode: RW, address_offset: 0x4100 } # = 0x1040
+ - - {field_name: tx_crcins_control, mm_width: 2, access_mode: RW, address_offset: 0x4200 } # = 0x1080
+ - - {field_name: tx_pktunderflow_error, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x4300 } # = 0x10C0
+ - - {field_name: tx_preamble_control, mm_width: 1, access_mode: RW, address_offset: 0x4400 } # = 0x1100
+ - - {field_name: tx_pauseframe_control, mm_width: 2, access_mode: RW, address_offset: 0x4500 } # = 0x1140
+ - - {field_name: tx_pauseframe_quanta, mm_width: 16, access_mode: RW, address_offset: 0x4504 } # = 0x1141
+ - - {field_name: tx_pauseframe_enable, mm_width: 1, access_mode: RW, address_offset: 0x4508 } # = 0x1142
# Altera is unclear about the width of the quanta registers. Assuming 32 bits, where bits 16:31 are reserved:
- - - {field_name: pfc_pause_quanta_0, mm_width: 32, access_mode: RW, address_offset: 0x4600 } # = 0x1180
- - - {field_name: pfc_pause_quanta_1, mm_width: 32, access_mode: RW, address_offset: 0x4604 } # = 0x1181
- - - {field_name: pfc_pause_quanta_2, mm_width: 32, access_mode: RW, address_offset: 0x4608 } # = 0x1182
- - - {field_name: pfc_pause_quanta_3, mm_width: 32, access_mode: RW, address_offset: 0x460c } # = 0x1183
- - - {field_name: pfc_pause_quanta_4, mm_width: 32, access_mode: RW, address_offset: 0x4610 } # = 0x1184
- - - {field_name: pfc_pause_quanta_5, mm_width: 32, access_mode: RW, address_offset: 0x4614 } # = 0x1185
- - - {field_name: pfc_pause_quanta_6, mm_width: 32, access_mode: RW, address_offset: 0x4618 } # = 0x1186
- - - {field_name: pfc_pause_quanta_7, mm_width: 32, access_mode: RW, address_offset: 0x461c } # = 0x1187
- - - {field_name: pfc_holdoff_quanta_0, mm_width: 32, access_mode: RW, address_offset: 0x4640 } # = 0x1190
- - - {field_name: pfc_holdoff_quanta_1, mm_width: 32, access_mode: RW, address_offset: 0x4644 } # = 0x1191
- - - {field_name: pfc_holdoff_quanta_2, mm_width: 32, access_mode: RW, address_offset: 0x4648 } # = 0x1192
- - - {field_name: pfc_holdoff_quanta_3, mm_width: 32, access_mode: RW, address_offset: 0x464c } # = 0x1193
- - - {field_name: pfc_holdoff_quanta_4, mm_width: 32, access_mode: RW, address_offset: 0x4650 } # = 0x1194
- - - {field_name: pfc_holdoff_quanta_5, mm_width: 32, access_mode: RW, address_offset: 0x4654 } # = 0x1195
- - - {field_name: pfc_holdoff_quanta_6, mm_width: 32, access_mode: RW, address_offset: 0x4658 } # = 0x1196
- - - {field_name: pfc_holdoff_quanta_7, mm_width: 32, access_mode: RW, address_offset: 0x465c } # = 0x1197
- - - {field_name: tx_pfc_priority_enable, mm_width: 8, access_mode: RW, address_offset: 0x4680 } # = 0x11A0
- - - {field_name: tx_addrins_control, mm_width: 1, access_mode: RW, address_offset: 0x4800 } # = 0x1200
- - - {field_name: tx_addrins_macaddr0, mm_width: 32, access_mode: RW, address_offset: 0x4804 } # = 0x1201
- - - {field_name: tx_addrins_macaddr1, mm_width: 16, access_mode: RW, address_offset: 0x4808 } # = 0x1202
- - - {field_name: tx_frame_maxlength, mm_width: 16, access_mode: RW, address_offset: 0x6004 } # = 0x1801
- - - {field_name: rx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x3000 } # = 0x0C00
- - - {field_name: tx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x7000 } # = 0x1C00
- - - {field_name: rx_stats_framesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3008 } # = 0x0C02
- - - {field_name: tx_stats_framesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7008 } # = 0x1C02
- - - {field_name: rx_stats_framesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3010 } # = 0x0C04
- - - {field_name: tx_stats_framesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7010 } # = 0x1C04
- - - {field_name: rx_stats_framesCRCErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3018 } # = 0x0C06
- - - {field_name: tx_stats_framesCRCErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7018 } # = 0x1C06
- - - {field_name: rx_stats_octetsOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3020 } # = 0x0C08
- - - {field_name: tx_stats_octetsOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7020 } # = 0x1C08
- - - {field_name: rx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3028 } # = 0x0C0A
- - - {field_name: tx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7028 } # = 0x1C0A
- - - {field_name: rx_stats_ifErrors, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3030 } # = 0x0C0C
- - - {field_name: tx_stats_ifErrors, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7030 } # = 0x1C0C
- - - {field_name: rx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3038 } # = 0x0C0E
- - - {field_name: tx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7038 } # = 0x1C0E
- - - {field_name: rx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3040 } # = 0x0C10
- - - {field_name: tx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7040 } # = 0x1C10
- - - {field_name: rx_stats_multicastFramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3048 } # = 0x0C12
- - - {field_name: tx_stats_multicastFramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7048 } # = 0x1C12
- - - {field_name: rx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3050 } # = 0x0C14
- - - {field_name: tx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7050 } # = 0x1C14
- - - {field_name: rx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3058 } # = 0x0C16
- - - {field_name: tx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7058 } # = 0x1C16
- - - {field_name: rx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3060 } # = 0x0C18
- - - {field_name: tx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7060 } # = 0x1C18
- - - {field_name: rx_stats_etherStatsOctets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3068 } # = 0x0C1A
- - - {field_name: tx_stats_etherStatsOctets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7068 } # = 0x1C1A
- - - {field_name: rx_stats_etherStatsPkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3070 } # = 0x0C1C
- - - {field_name: tx_stats_etherStatsPkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7070 } # = 0x1C1C
- - - {field_name: rx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3078 } # = 0x0C1E
- - - {field_name: tx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7078 } # = 0x1C1E
- - - {field_name: rx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3080 } # = 0x0C20
- - - {field_name: tx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7080 } # = 0x1C20
- - - {field_name: rx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3088 } # = 0x0C22
- - - {field_name: tx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7088 } # = 0x1C22
- - - {field_name: rx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3090 } # = 0x0C24
- - - {field_name: tx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7090 } # = 0x1C24
- - - {field_name: rx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3098 } # = 0x0C26
- - - {field_name: tx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7098 } # = 0x1C26
- - - {field_name: rx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30a0 } # = 0x0C28
- - - {field_name: tx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70a0 } # = 0x1C28
- - - {field_name: rx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30a8 } # = 0x0C2A
- - - {field_name: tx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70a8 } # = 0x1C2A
- - - {field_name: rx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30b0 } # = 0x0C2C
- - - {field_name: tx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70b0 } # = 0x1C2C
- - - {field_name: rx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30b8 } # = 0x0C2E
- - - {field_name: tx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70b8 } # = 0x1C2E
- - - {field_name: rx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30c0 } # = 0x0C30
- - - {field_name: tx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70c0 } # = 0x1C30
- - - {field_name: rx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30c8 } # = 0x0C32
- - - {field_name: tx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70c8 } # = 0x1C32
- - - {field_name: rx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30d0 } # = 0x0C34
- - - {field_name: tx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70d0 } # = 0x1C34
- - - {field_name: rx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30d8 } # = 0x0C36
- - - {field_name: tx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70d8 } # = 0x1C36
- - - {field_name: rx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30e0 } # = 0x0C38
- - - {field_name: tx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70e0 } # = 0x1C38
- - - {field_name: rx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30e8 } # = 0x0C3A
- - - {field_name: tx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70e8 } # = 0x1C3A
- - - {field_name: rx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30f0 } # = 0x0C3C
- - - {field_name: tx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70f0 } # = 0x1C3C
+ - - {field_name: pfc_pause_quanta_0, mm_width: 32, access_mode: RW, address_offset: 0x4600 } # = 0x1180
+ - - {field_name: pfc_pause_quanta_1, mm_width: 32, access_mode: RW, address_offset: 0x4604 } # = 0x1181
+ - - {field_name: pfc_pause_quanta_2, mm_width: 32, access_mode: RW, address_offset: 0x4608 } # = 0x1182
+ - - {field_name: pfc_pause_quanta_3, mm_width: 32, access_mode: RW, address_offset: 0x460c } # = 0x1183
+ - - {field_name: pfc_pause_quanta_4, mm_width: 32, access_mode: RW, address_offset: 0x4610 } # = 0x1184
+ - - {field_name: pfc_pause_quanta_5, mm_width: 32, access_mode: RW, address_offset: 0x4614 } # = 0x1185
+ - - {field_name: pfc_pause_quanta_6, mm_width: 32, access_mode: RW, address_offset: 0x4618 } # = 0x1186
+ - - {field_name: pfc_pause_quanta_7, mm_width: 32, access_mode: RW, address_offset: 0x461c } # = 0x1187
+ - - {field_name: pfc_holdoff_quanta_0, mm_width: 32, access_mode: RW, address_offset: 0x4640 } # = 0x1190
+ - - {field_name: pfc_holdoff_quanta_1, mm_width: 32, access_mode: RW, address_offset: 0x4644 } # = 0x1191
+ - - {field_name: pfc_holdoff_quanta_2, mm_width: 32, access_mode: RW, address_offset: 0x4648 } # = 0x1192
+ - - {field_name: pfc_holdoff_quanta_3, mm_width: 32, access_mode: RW, address_offset: 0x464c } # = 0x1193
+ - - {field_name: pfc_holdoff_quanta_4, mm_width: 32, access_mode: RW, address_offset: 0x4650 } # = 0x1194
+ - - {field_name: pfc_holdoff_quanta_5, mm_width: 32, access_mode: RW, address_offset: 0x4654 } # = 0x1195
+ - - {field_name: pfc_holdoff_quanta_6, mm_width: 32, access_mode: RW, address_offset: 0x4658 } # = 0x1196
+ - - {field_name: pfc_holdoff_quanta_7, mm_width: 32, access_mode: RW, address_offset: 0x465c } # = 0x1197
+ - - {field_name: tx_pfc_priority_enable, mm_width: 8, access_mode: RW, address_offset: 0x4680 } # = 0x11A0
+ - - {field_name: tx_addrins_control, mm_width: 1, access_mode: RW, address_offset: 0x4800 } # = 0x1200
+ - - {field_name: tx_addrins_macaddr0, mm_width: 32, access_mode: RW, address_offset: 0x4804 } # = 0x1201
+ - - {field_name: tx_addrins_macaddr1, mm_width: 16, access_mode: RW, address_offset: 0x4808 } # = 0x1202
+ - - {field_name: tx_frame_maxlength, mm_width: 16, access_mode: RW, address_offset: 0x6004 } # = 0x1801
+ - - {field_name: rx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x3000 } # = 0x0C00
+ - - {field_name: tx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x7000 } # = 0x1C00
+ - - {field_name: rx_stats_framesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3008 } # = 0x0C02
+ - - {field_name: tx_stats_framesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7008 } # = 0x1C02
+ - - {field_name: rx_stats_framesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3010 } # = 0x0C04
+ - - {field_name: tx_stats_framesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7010 } # = 0x1C04
+ - - {field_name: rx_stats_framesCRCErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3018 } # = 0x0C06
+ - - {field_name: tx_stats_framesCRCErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7018 } # = 0x1C06
+ - - {field_name: rx_stats_octetsOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3020 } # = 0x0C08
+ - - {field_name: tx_stats_octetsOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7020 } # = 0x1C08
+ - - {field_name: rx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3028 } # = 0x0C0A
+ - - {field_name: tx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7028 } # = 0x1C0A
+ - - {field_name: rx_stats_ifErrors, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3030 } # = 0x0C0C
+ - - {field_name: tx_stats_ifErrors, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7030 } # = 0x1C0C
+ - - {field_name: rx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3038 } # = 0x0C0E
+ - - {field_name: tx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7038 } # = 0x1C0E
+ - - {field_name: rx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3040 } # = 0x0C10
+ - - {field_name: tx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7040 } # = 0x1C10
+ - - {field_name: rx_stats_multicastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3048 } # = 0x0C12
+ - - {field_name: tx_stats_multicastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7048 } # = 0x1C12
+ - - {field_name: rx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3050 } # = 0x0C14
+ - - {field_name: tx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7050 } # = 0x1C14
+ - - {field_name: rx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3058 } # = 0x0C16
+ - - {field_name: tx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7058 } # = 0x1C16
+ - - {field_name: rx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3060 } # = 0x0C18
+ - - {field_name: tx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7060 } # = 0x1C18
+ - - {field_name: rx_stats_etherStatsOctets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3068 } # = 0x0C1A
+ - - {field_name: tx_stats_etherStatsOctets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7068 } # = 0x1C1A
+ - - {field_name: rx_stats_etherStatsPkts, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3070 } # = 0x0C1C
+ - - {field_name: tx_stats_etherStatsPkts, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7070 } # = 0x1C1C
+ - - {field_name: rx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3078 } # = 0x0C1E
+ - - {field_name: tx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7078 } # = 0x1C1E
+ - - {field_name: rx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3080 } # = 0x0C20
+ - - {field_name: tx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7080 } # = 0x1C20
+ - - {field_name: rx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3088 } # = 0x0C22
+ - - {field_name: tx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7088 } # = 0x1C22
+ - - {field_name: rx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3090 } # = 0x0C24
+ - - {field_name: tx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7090 } # = 0x1C24
+ - - {field_name: rx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x3098 } # = 0x0C26
+ - - {field_name: tx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x7098 } # = 0x1C26
+ - - {field_name: rx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30a0 } # = 0x0C28
+ - - {field_name: tx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70a0 } # = 0x1C28
+ - - {field_name: rx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30a8 } # = 0x0C2A
+ - - {field_name: tx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70a8 } # = 0x1C2A
+ - - {field_name: rx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30b0 } # = 0x0C2C
+ - - {field_name: tx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70b0 } # = 0x1C2C
+ - - {field_name: rx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30b8 } # = 0x0C2E
+ - - {field_name: tx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70b8 } # = 0x1C2E
+ - - {field_name: rx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30c0 } # = 0x0C30
+ - - {field_name: tx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70c0 } # = 0x1C30
+ - - {field_name: rx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30c8 } # = 0x0C32
+ - - {field_name: tx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70c8 } # = 0x1C32
+ - - {field_name: rx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30d0 } # = 0x0C34
+ - - {field_name: tx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70d0 } # = 0x1C34
+ - - {field_name: rx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30d8 } # = 0x0C36
+ - - {field_name: tx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70d8 } # = 0x1C36
+ - - {field_name: rx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30e0 } # = 0x0C38
+ - - {field_name: tx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70e0 } # = 0x1C38
+ - - {field_name: rx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30e8 } # = 0x0C3A
+ - - {field_name: tx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70e8 } # = 0x1C3A
+ - - {field_name: rx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x30f0 } # = 0x0C3C
+ - - {field_name: tx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, access_mode: RO, address_offset: 0x70f0 } # = 0x1C3C
- peripheral_name: nw_10GbE_eth10g # pi_nw_10GbE_eth10g.py / pi_10GbE.py