Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
H
HDL
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Container Registry
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
RTSD
HDL
Commits
7a4371be
Commit
7a4371be
authored
9 years ago
by
Zanting
Browse files
Options
Downloads
Patches
Plain Diff
Updated registers for Block Generator and Data Buffer
parent
e71d9d7a
No related branches found
No related tags found
No related merge requests found
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
applications/unb1_reorder/quartus/sopc_unb1_reorder.sopc
+113
-121
113 additions, 121 deletions
applications/unb1_reorder/quartus/sopc_unb1_reorder.sopc
with
113 additions
and
121 deletions
applications/unb1_reorder/quartus/sopc_unb1_reorder.sopc
+
113
−
121
View file @
7a4371be
...
...
@@ -14,7 +14,7 @@
{
datum baseAddress
{
value = "1
12
0";
value = "1
04
0";
type = "long";
}
}
...
...
@@ -22,7 +22,7 @@
{
datum _sortIndex
{
value = "
2
1";
value = "1
3
";
type = "int";
}
}
...
...
@@ -84,32 +84,27 @@
type = "String";
}
}
element
ram_diag_data_buffer_re
.mem
element
pio_pps
.mem
{
datum baseAddress
{
value = "
393216
";
value = "
1048
";
type = "long";
}
}
element r
am_diag_bg
.mem
element r
eg_io_ddr
.mem
{
datum baseAddress
{
value = "
524288
";
value = "
496
";
type = "long";
}
}
element reg_
wdi
.mem
element reg_
unb_sens
.mem
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "
12288
";
value = "
352
";
type = "long";
}
}
...
...
@@ -134,67 +129,72 @@
type = "long";
}
}
element r
eg
_diag_
bg
.mem
element r
am
_diag_
data_buffer
.mem
{
datum baseAddress
{
value = "
102
4";
value = "
26214
4";
type = "long";
}
}
element reg_
unb
_se
ns
.mem
element reg_
diag_tx
_se
q
.mem
{
datum baseAddress
{
value = "
480
";
value = "
1024
";
type = "long";
}
}
element
pio_pps
.mem
element
reg_bsn_monitor
.mem
{
datum baseAddress
{
value = "
1
12
8
";
value = "
5
12";
type = "long";
}
}
element reg_diag_
data_buffer_re
.mem
element reg_diag_
rx_seq
.mem
{
datum baseAddress
{
value = "
25
6";
value = "
41
6";
type = "long";
}
}
element reg_
bsn_monitor
.mem
element reg_
diag_bg
.mem
{
datum baseAddress
{
value = "
512
";
value = "
384
";
type = "long";
}
}
element reg_
io_dd
r.mem
element reg_
diag_data_buffe
r.mem
{
datum baseAddress
{
value = "1
104
";
value = "1
28
";
type = "long";
}
}
element ram_diag_
data_buffer_im
.mem
element ram_diag_
bg
.mem
{
datum baseAddress
{
value = "
262144
";
value = "
393216
";
type = "long";
}
}
element reg_di
ag_data_buffer_im
.mem
element reg_
w
di.mem
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "128";
value = "12
28
8";
type = "long";
}
}
...
...
@@ -223,7 +223,7 @@
{
datum baseAddress
{
value = "
384
";
value = "
256
";
type = "long";
}
}
...
...
@@ -294,7 +294,7 @@
}
datum baseAddress
{
value = "
1056
";
value = "
448
";
type = "long";
}
}
...
...
@@ -306,59 +306,59 @@
type = "int";
}
}
element ram_diag_data_buffer
_im
element ram_diag_data_buffer
{
datum _sortIndex
{
value = "1
6
";
value = "
2
1";
type = "int";
}
}
element ram_
diag_data_buffer_r
e
element ram_
ss_ss_wid
e
{
datum _sortIndex
{
value = "1
7
";
value = "1
4
";
type = "int";
}
}
element r
am_ss_ss_wide
element r
eg_bsn_monitor
{
datum _sortIndex
{
value = "1
9
";
value = "1
5
";
type = "int";
}
}
element reg_
bsn_monitor
element reg_
diag_bg
{
datum _sortIndex
{
value = "
20
";
value = "
17
";
type = "int";
}
}
element reg_diag_
bg
element reg_diag_
data_buffer
{
datum _sortIndex
{
value = "
13
";
value = "
20
";
type = "int";
}
}
element reg_diag_
data_buffer_im
element reg_diag_
rx_seq
{
datum _sortIndex
{
value = "
14
";
value = "
22
";
type = "int";
}
}
element reg_diag_
data_buffer_re
element reg_diag_
tx_seq
{
datum _sortIndex
{
value = "1
5
";
value = "1
9
";
type = "int";
}
}
...
...
@@ -366,7 +366,7 @@
{
datum _sortIndex
{
value = "
22
";
value = "
16
";
type = "int";
}
}
...
...
@@ -394,14 +394,6 @@
type = "int";
}
}
element pio_wdi.s1
{
datum baseAddress
{
value = "1088";
type = "long";
}
}
element onchip_memory2_0.s1
{
datum _lockedAddress
...
...
@@ -419,7 +411,7 @@
{
datum baseAddress
{
value = "
448
";
value = "
320
";
type = "long";
}
}
...
...
@@ -427,7 +419,15 @@
{
datum baseAddress
{
value = "1072";
value = "464";
type = "long";
}
}
element pio_wdi.s1
{
datum baseAddress
{
value = "480";
type = "long";
}
}
...
...
@@ -456,8 +456,8 @@
<parameter
name=
"maxAdditionalLatency"
value=
"0"
/>
<parameter
name=
"projectName"
value=
"unb1_reorder.qpf"
/>
<parameter
name=
"sopcBorderPoints"
value=
"true"
/>
<parameter
name=
"systemHash"
value=
"-4
045026275
2"
/>
<parameter
name=
"timeStamp"
value=
"14
27720908319
"
/>
<parameter
name=
"systemHash"
value=
"-4
132294436
2"
/>
<parameter
name=
"timeStamp"
value=
"14
35140961677
"
/>
<parameter
name=
"useTestBenchNamingPattern"
value=
"false"
/>
<module
kind=
"clock_source"
version=
"11.1"
enabled=
"1"
name=
"clk_0"
>
<parameter
name=
"clockFrequency"
value=
"25000000"
/>
...
...
@@ -558,8 +558,8 @@
<parameter
name=
"dcache_numTCDM"
value=
"_0"
/>
<parameter
name=
"dcache_lineSize"
value=
"_32"
/>
<parameter
name=
"dcache_bursts"
value=
"false"
/>
<parameter
name=
"dataSlaveMapParam"
>
<![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer
_im
.mem' start='0x80' end='0x100' /><slave
name='reg_diag_data_buffer_re.mem' start='0x100' end='0x180' /><slave
name='avs_eth_0.mms_reg' start='0x1
8
0' end='0x1
C
0' /><slave name='timer_0.s1' start='0x1
C
0' end='0x1
E
0' /><slave name='reg_unb_sens.mem' start='0x1
E
0' end='0x
20
0' /><slave name='reg_
bsn_monitor
.mem' start='0x
20
0' end='0x
40
0' /><slave name='reg_diag_
bg
.mem' start='0x
40
0' end='0x
42
0' /><slave name='altpll_0.pll_slave' start='0x
42
0' end='0x
43
0' /><slave name='pio_debug_wave.s1' start='0x
43
0' end='0x
44
0' /><slave name='pio_wdi.s1' start='0x
44
0' end='0x
45
0' /><slave name='reg_io_ddr.mem' start='0x
450' end='0x46
0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x4
6
0' end='0x4
6
8' /><slave name='pio_pps.mem' start='0x4
6
8' end='0x4
7
0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='ram_ss_ss_wide.mem' start='0x8000' end='0x10000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_data_buffer
_im
.mem' start='0x40000' end='0x60000' /><slave name='ram_diag_
data_buffer_re
.mem' start='0x60000' end='0x80000'
/><slave name='ram_diag_bg.mem' start='0x80000' end='0xA0000'
/></address-map>]]>
</parameter>
<parameter
name=
"dataAddrWidth"
value=
"
20
"
/>
<parameter
name=
"dataSlaveMapParam"
>
<![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='avs_eth_0.mms_reg' start='0x1
0
0' end='0x1
4
0' /><slave name='timer_0.s1' start='0x1
4
0' end='0x1
6
0' /><slave name='reg_unb_sens.mem' start='0x1
6
0' end='0x
18
0' /><slave name='reg_
diag_bg
.mem' start='0x
18
0' end='0x
1A
0' /><slave name='reg_diag_
rx_seq
.mem' start='0x
1A
0' end='0x
1C
0' /><slave name='altpll_0.pll_slave' start='0x
1C
0' end='0x
1D
0' /><slave name='pio_debug_wave.s1' start='0x
1D
0' end='0x
1E
0' /><slave name='pio_wdi.s1' start='0x
1E
0' end='0x
1F
0' /><slave name='reg_io_ddr.mem' start='0x
1F0' end='0x200' /><slave name='reg_bsn_monitor.mem' start='0x200' end='0x400' /><slave name='reg_diag_tx_seq.mem' start='0x400' end='0x41
0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x4
1
0' end='0x4
1
8' /><slave name='pio_pps.mem' start='0x4
1
8' end='0x4
2
0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='ram_ss_ss_wide.mem' start='0x8000' end='0x10000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_data_buffer.mem' start='0x40000' end='0x60000' /><slave name='ram_diag_
bg
.mem' start='0x60000' end='0x80000' /></address-map>]]>
</parameter>
<parameter
name=
"dataAddrWidth"
value=
"
19
"
/>
<parameter
name=
"customInstSlavesSystemInfo"
value=
"<info/>"
/>
<parameter
name=
"cpuReset"
value=
"false"
/>
<parameter
name=
"cpuID"
value=
"0"
/>
...
...
@@ -855,16 +855,7 @@ q]]></parameter>
kind=
"avs_common_mm"
version=
"1.0"
enabled=
"1"
name=
"reg_diag_data_buffer_im"
>
<parameter
name=
"g_adr_w"
value=
"5"
/>
<parameter
name=
"g_dat_w"
value=
"32"
/>
<parameter
name=
"AUTO_SYSTEM_CLOCK_RATE"
value=
"50000000"
/>
</module>
<module
kind=
"avs_common_mm"
version=
"1.0"
enabled=
"1"
name=
"reg_diag_data_buffer_re"
>
name=
"reg_diag_data_buffer"
>
<parameter
name=
"g_adr_w"
value=
"5"
/>
<parameter
name=
"g_dat_w"
value=
"32"
/>
<parameter
name=
"AUTO_SYSTEM_CLOCK_RATE"
value=
"50000000"
/>
...
...
@@ -873,16 +864,7 @@ q]]></parameter>
kind=
"avs_common_mm"
version=
"1.0"
enabled=
"1"
name=
"ram_diag_data_buffer_im"
>
<parameter
name=
"g_adr_w"
value=
"15"
/>
<parameter
name=
"g_dat_w"
value=
"32"
/>
<parameter
name=
"AUTO_SYSTEM_CLOCK_RATE"
value=
"50000000"
/>
</module>
<module
kind=
"avs_common_mm"
version=
"1.0"
enabled=
"1"
name=
"ram_diag_data_buffer_re"
>
name=
"ram_diag_data_buffer"
>
<parameter
name=
"g_adr_w"
value=
"15"
/>
<parameter
name=
"g_dat_w"
value=
"32"
/>
<parameter
name=
"AUTO_SYSTEM_CLOCK_RATE"
value=
"50000000"
/>
...
...
@@ -910,6 +892,16 @@ q]]></parameter>
<parameter
name=
"g_dat_w"
value=
"32"
/>
<parameter
name=
"AUTO_SYSTEM_CLOCK_RATE"
value=
"50000000"
/>
</module>
<module
kind=
"avs_common_mm"
version=
"1.0"
enabled=
"1"
name=
"reg_diag_tx_seq"
>
<parameter
name=
"g_adr_w"
value=
"2"
/>
<parameter
name=
"g_dat_w"
value=
"32"
/>
<parameter
name=
"AUTO_SYSTEM_CLOCK_RATE"
value=
"50000000"
/>
</module>
<module
kind=
"avs_common_mm"
version=
"1.0"
enabled=
"1"
name=
"reg_diag_rx_seq"
>
<parameter
name=
"g_adr_w"
value=
"3"
/>
<parameter
name=
"g_dat_w"
value=
"32"
/>
<parameter
name=
"AUTO_SYSTEM_CLOCK_RATE"
value=
"50000000"
/>
</module>
<connection
kind=
"avalon"
version=
"11.1"
...
...
@@ -948,7 +940,7 @@ q]]></parameter>
start=
"cpu_0.data_master"
end=
"jtag_uart_0.avalon_jtag_slave"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x04
6
0"
/>
<parameter
name=
"baseAddress"
value=
"0x04
1
0"
/>
</connection>
<connection
kind=
"interrupt"
...
...
@@ -963,7 +955,7 @@ q]]></parameter>
start=
"cpu_0.data_master"
end=
"altpll_0.pll_slave"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x0
42
0"
/>
<parameter
name=
"baseAddress"
value=
"0x0
1c
0"
/>
</connection>
<connection
kind=
"clock"
version=
"11.1"
start=
"altpll_0.c0"
end=
"cpu_0.clk"
/>
<connection
...
...
@@ -988,7 +980,7 @@ q]]></parameter>
start=
"cpu_0.data_master"
end=
"pio_debug_wave.s1"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x0
43
0"
/>
<parameter
name=
"baseAddress"
value=
"0x0
1d
0"
/>
</connection>
<connection
kind=
"clock"
version=
"11.1"
start=
"altpll_0.c0"
end=
"pio_wdi.clk"
/>
<connection
...
...
@@ -997,7 +989,7 @@ q]]></parameter>
start=
"cpu_0.data_master"
end=
"pio_wdi.s1"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x0
44
0"
/>
<parameter
name=
"baseAddress"
value=
"0x0
1e
0"
/>
</connection>
<connection
kind=
"clock"
version=
"11.1"
start=
"altpll_0.c0"
end=
"timer_0.clk"
/>
<connection
...
...
@@ -1006,7 +998,7 @@ q]]></parameter>
start=
"cpu_0.data_master"
end=
"timer_0.s1"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x01
c
0"
/>
<parameter
name=
"baseAddress"
value=
"0x01
4
0"
/>
</connection>
<connection
kind=
"interrupt"
version=
"11.1"
start=
"cpu_0.d_irq"
end=
"timer_0.irq"
>
<parameter
name=
"irqNumber"
value=
"1"
/>
...
...
@@ -1022,7 +1014,7 @@ q]]></parameter>
start=
"cpu_0.data_master"
end=
"reg_unb_sens.mem"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x01
e
0"
/>
<parameter
name=
"baseAddress"
value=
"0x01
6
0"
/>
</connection>
<connection
kind=
"clock"
...
...
@@ -1057,7 +1049,7 @@ q]]></parameter>
start=
"cpu_0.data_master"
end=
"pio_pps.mem"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x04
6
8"
/>
<parameter
name=
"baseAddress"
value=
"0x04
1
8"
/>
</connection>
<connection
kind=
"clock"
version=
"11.1"
start=
"altpll_0.c0"
end=
"reg_wdi.system"
/>
<connection
...
...
@@ -1079,18 +1071,18 @@ q]]></parameter>
start=
"cpu_0.data_master"
end=
"reg_diag_bg.mem"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x0
40
0"
/>
<parameter
name=
"baseAddress"
value=
"0x0
18
0"
/>
</connection>
<connection
kind=
"clock"
version=
"11.1"
start=
"altpll_0.c0"
end=
"reg_diag_data_buffer
_im
.system"
/>
end=
"reg_diag_data_buffer.system"
/>
<connection
kind=
"avalon"
version=
"11.1"
start=
"cpu_0.data_master"
end=
"reg_diag_data_buffer
_im
.mem"
>
end=
"reg_diag_data_buffer.mem"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x0080"
/>
</connection>
...
...
@@ -1098,41 +1090,15 @@ q]]></parameter>
kind=
"clock"
version=
"11.1"
start=
"altpll_0.c0"
end=
"r
eg
_diag_data_buffer
_re
.system"
/>
end=
"r
am
_diag_data_buffer.system"
/>
<connection
kind=
"avalon"
version=
"11.1"
start=
"cpu_0.data_master"
end=
"reg_diag_data_buffer_re.mem"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x0100"
/>
</connection>
<connection
kind=
"clock"
version=
"11.1"
start=
"altpll_0.c0"
end=
"ram_diag_data_buffer_im.system"
/>
<connection
kind=
"avalon"
version=
"11.1"
start=
"cpu_0.data_master"
end=
"ram_diag_data_buffer_im.mem"
>
end=
"ram_diag_data_buffer.mem"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x00040000"
/>
</connection>
<connection
kind=
"clock"
version=
"11.1"
start=
"altpll_0.c0"
end=
"ram_diag_data_buffer_re.system"
/>
<connection
kind=
"avalon"
version=
"11.1"
start=
"cpu_0.data_master"
end=
"ram_diag_data_buffer_re.mem"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x00060000"
/>
</connection>
<connection
kind=
"clock"
version=
"11.1"
...
...
@@ -1144,7 +1110,7 @@ q]]></parameter>
start=
"cpu_0.data_master"
end=
"ram_diag_bg.mem"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x000
8
0000"
/>
<parameter
name=
"baseAddress"
value=
"0x000
6
0000"
/>
</connection>
<connection
kind=
"clock"
...
...
@@ -1187,7 +1153,7 @@ q]]></parameter>
start=
"cpu_0.data_master"
end=
"avs_eth_0.mms_reg"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x01
8
0"
/>
<parameter
name=
"baseAddress"
value=
"0x01
0
0"
/>
</connection>
<connection
kind=
"avalon"
...
...
@@ -1215,6 +1181,32 @@ q]]></parameter>
start=
"cpu_0.data_master"
end=
"reg_io_ddr.mem"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x0450"
/>
<parameter
name=
"baseAddress"
value=
"0x01f0"
/>
</connection>
<connection
kind=
"clock"
version=
"11.1"
start=
"altpll_0.c0"
end=
"reg_diag_tx_seq.system"
/>
<connection
kind=
"avalon"
version=
"11.1"
start=
"cpu_0.data_master"
end=
"reg_diag_tx_seq.mem"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x0400"
/>
</connection>
<connection
kind=
"clock"
version=
"11.1"
start=
"altpll_0.c0"
end=
"reg_diag_rx_seq.system"
/>
<connection
kind=
"avalon"
version=
"11.1"
start=
"cpu_0.data_master"
end=
"reg_diag_rx_seq.mem"
>
<parameter
name=
"arbitrationPriority"
value=
"1"
/>
<parameter
name=
"baseAddress"
value=
"0x01a0"
/>
</connection>
</system>
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment