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Commit 79612cac authored by Pepping's avatar Pepping
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removed mm interfaces of the reorder blocks

parent 0c4f338c
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applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/mmm_apertif_unb1_cor_mesh_ref.vhd
+ 78
− 90
View file @ 79612cac
...@@ -62,11 +62,7 @@ ...@@ -62,11 +62,7 @@
-- reg_diagnostics_mosi => reg_diagnostics_mosi, -- reg_diagnostics_mosi => reg_diagnostics_mosi,
-- reg_diagnostics_miso => reg_diagnostics_miso, -- reg_diagnostics_miso => reg_diagnostics_miso,
-- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi, -- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
-- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso, -- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso
-- ram_reorder_row_input_mosi => ram_reorder_row_input_mosi,
-- ram_reorder_row_input_miso => ram_reorder_row_input_miso,
-- ram_reorder_row_mesh_mosi => ram_reorder_row_mesh_mosi,
-- ram_reorder_row_mesh_miso => ram_reorder_row_mesh_miso
-- ); -- );
-- --
LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib; LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
...@@ -131,11 +127,7 @@ ENTITY mmm_apertif_unb1_cor_mesh_ref IS ...@@ -131,11 +127,7 @@ ENTITY mmm_apertif_unb1_cor_mesh_ref IS
reg_diagnostics_mosi : OUT t_mem_mosi; reg_diagnostics_mosi : OUT t_mem_mosi;
reg_diagnostics_miso : IN t_mem_miso := c_mem_miso_rst; reg_diagnostics_miso : IN t_mem_miso := c_mem_miso_rst;
reg_tr_nonbonded_mosi : OUT t_mem_mosi; reg_tr_nonbonded_mosi : OUT t_mem_mosi;
reg_tr_nonbonded_miso : IN t_mem_miso := c_mem_miso_rst; reg_tr_nonbonded_miso : IN t_mem_miso := c_mem_miso_rst
ram_reorder_row_input_mosi : OUT t_mem_mosi;
ram_reorder_row_input_miso : IN t_mem_miso := c_mem_miso_rst;
ram_reorder_row_mesh_mosi : OUT t_mem_mosi;
ram_reorder_row_mesh_miso : IN t_mem_miso := c_mem_miso_rst
); );
END ENTITY mmm_apertif_unb1_cor_mesh_ref; END ENTITY mmm_apertif_unb1_cor_mesh_ref;
...@@ -310,13 +302,13 @@ BEGIN ...@@ -310,13 +302,13 @@ BEGIN
PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso ); PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_eth1g_tse : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_TSE") u_mm_file_eth1g_tse : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_TSE")
PORT MAP(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso ); PORT MAP(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
u_mm_file_reg_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_RE") u_mm_file_reg_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_RE")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso ); PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso );
u_mm_file_ram_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_RE") u_mm_file_ram_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_RE")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso ); PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso );
u_mm_file_reg_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_IM") u_mm_file_reg_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_IM")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso ); PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso );
u_mm_file_ram_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_IM") u_mm_file_ram_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_IM")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso ); PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso );
u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG") u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso ); PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
...@@ -326,10 +318,6 @@ BEGIN ...@@ -326,10 +318,6 @@ BEGIN
PORT MAP(mm_rst, mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso ); PORT MAP(mm_rst, mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
u_mm_file_reg_tr_nonbonded : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED") u_mm_file_reg_tr_nonbonded : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
PORT MAP(mm_rst, mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso ); PORT MAP(mm_rst, mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
u_mm_file_ram_reorder_row_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_REORDER_ROW_INPUT")
PORT MAP(mm_rst, mm_clk, ram_reorder_row_input_mosi, ram_reorder_row_input_miso );
u_mm_file_ram_reorder_row_mesh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_REORDER_ROW_MESH")
PORT MAP(mm_rst, mm_clk, ram_reorder_row_mesh_mosi, ram_reorder_row_mesh_miso );
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS -- 1GbE setup sequence normally performed by unb_os@NIOS
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
......
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