diff --git a/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/mmm_apertif_unb1_cor_mesh_ref.vhd b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/mmm_apertif_unb1_cor_mesh_ref.vhd
index 03cd3d74e1ee4e58ac24f4ae20d624f0d3eb449f..83f89f9f3bbe80f5f487944227d8a02fc12e8a16 100644
--- a/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/mmm_apertif_unb1_cor_mesh_ref.vhd
+++ b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/mmm_apertif_unb1_cor_mesh_ref.vhd
@@ -26,47 +26,43 @@
-- g_sim_node_nr => g_sim_node_nr
-- )
-- PORT MAP(
--- mm_clk => mm_clk,
--- mm_rst => mm_rst,
--- pout_wdi => pout_wdi,
--- reg_wdi_mosi => reg_wdi_mosi,
--- reg_wdi_miso => reg_wdi_miso,
--- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
--- reg_unb_system_info_miso => reg_unb_system_info_miso,
--- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
--- rom_unb_system_info_miso => rom_unb_system_info_miso,
--- reg_unb_sens_mosi => reg_unb_sens_mosi,
--- reg_unb_sens_miso => reg_unb_sens_miso,
--- reg_ppsh_mosi => reg_ppsh_mosi,
--- reg_ppsh_miso => reg_ppsh_miso,
--- eth1g_mm_rst => eth1g_mm_rst,
--- eth1g_reg_interrupt => eth1g_reg_interrupt,
--- eth1g_ram_mosi => eth1g_ram_mosi,
--- eth1g_ram_miso => eth1g_ram_miso,
--- eth1g_reg_mosi => eth1g_reg_mosi,
--- eth1g_reg_miso => eth1g_reg_miso,
--- eth1g_tse_mosi => eth1g_tse_mosi,
--- eth1g_tse_miso => eth1g_tse_miso,
--- reg_diag_data_buf_re_mosi => reg_diag_data_buf_re_mosi,
--- reg_diag_data_buf_re_miso => reg_diag_data_buf_re_miso,
--- ram_diag_data_buf_re_mosi => ram_diag_data_buf_re_mosi,
--- ram_diag_data_buf_re_miso => ram_diag_data_buf_re_miso,
--- reg_diag_data_buf_im_mosi => reg_diag_data_buf_im_mosi,
--- reg_diag_data_buf_im_miso => reg_diag_data_buf_im_miso,
--- ram_diag_data_buf_im_mosi => ram_diag_data_buf_im_mosi,
--- ram_diag_data_buf_im_miso => ram_diag_data_buf_im_miso,
--- reg_diag_bg_mosi => reg_diag_bg_mosi,
--- reg_diag_bg_miso => reg_diag_bg_miso,
--- ram_diag_bg_mosi => ram_diag_bg_mosi,
--- ram_diag_bg_miso => ram_diag_bg_miso,
--- reg_diagnostics_mosi => reg_diagnostics_mosi,
--- reg_diagnostics_miso => reg_diagnostics_miso,
--- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
--- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
--- ram_reorder_row_input_mosi => ram_reorder_row_input_mosi,
--- ram_reorder_row_input_miso => ram_reorder_row_input_miso,
--- ram_reorder_row_mesh_mosi => ram_reorder_row_mesh_mosi,
--- ram_reorder_row_mesh_miso => ram_reorder_row_mesh_miso
+-- mm_clk => mm_clk,
+-- mm_rst => mm_rst,
+-- pout_wdi => pout_wdi,
+-- reg_wdi_mosi => reg_wdi_mosi,
+-- reg_wdi_miso => reg_wdi_miso,
+-- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+-- reg_unb_system_info_miso => reg_unb_system_info_miso,
+-- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+-- rom_unb_system_info_miso => rom_unb_system_info_miso,
+-- reg_unb_sens_mosi => reg_unb_sens_mosi,
+-- reg_unb_sens_miso => reg_unb_sens_miso,
+-- reg_ppsh_mosi => reg_ppsh_mosi,
+-- reg_ppsh_miso => reg_ppsh_miso,
+-- eth1g_mm_rst => eth1g_mm_rst,
+-- eth1g_reg_interrupt => eth1g_reg_interrupt,
+-- eth1g_ram_mosi => eth1g_ram_mosi,
+-- eth1g_ram_miso => eth1g_ram_miso,
+-- eth1g_reg_mosi => eth1g_reg_mosi,
+-- eth1g_reg_miso => eth1g_reg_miso,
+-- eth1g_tse_mosi => eth1g_tse_mosi,
+-- eth1g_tse_miso => eth1g_tse_miso,
+-- reg_diag_data_buf_re_mosi => reg_diag_data_buf_re_mosi,
+-- reg_diag_data_buf_re_miso => reg_diag_data_buf_re_miso,
+-- ram_diag_data_buf_re_mosi => ram_diag_data_buf_re_mosi,
+-- ram_diag_data_buf_re_miso => ram_diag_data_buf_re_miso,
+-- reg_diag_data_buf_im_mosi => reg_diag_data_buf_im_mosi,
+-- reg_diag_data_buf_im_miso => reg_diag_data_buf_im_miso,
+-- ram_diag_data_buf_im_mosi => ram_diag_data_buf_im_mosi,
+-- ram_diag_data_buf_im_miso => ram_diag_data_buf_im_miso,
+-- reg_diag_bg_mosi => reg_diag_bg_mosi,
+-- reg_diag_bg_miso => reg_diag_bg_miso,
+-- ram_diag_bg_mosi => ram_diag_bg_mosi,
+-- ram_diag_bg_miso => ram_diag_bg_miso,
+-- reg_diagnostics_mosi => reg_diagnostics_mosi,
+-- reg_diagnostics_miso => reg_diagnostics_miso,
+-- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+-- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso
-- );
--
LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
@@ -95,47 +91,43 @@ ENTITY mmm_apertif_unb1_cor_mesh_ref IS
g_sim_node_nr : NATURAL := 0
);
PORT (
- mm_clk : IN STD_LOGIC := '1';
- mm_rst : IN STD_LOGIC := '1';
- pout_wdi : OUT STD_LOGIC := '1';
- reg_wdi_mosi : OUT t_mem_mosi;
- reg_wdi_miso : IN t_mem_miso := c_mem_miso_rst;
- reg_unb_system_info_mosi : OUT t_mem_mosi;
- reg_unb_system_info_miso : IN t_mem_miso := c_mem_miso_rst;
- rom_unb_system_info_mosi : OUT t_mem_mosi;
- rom_unb_system_info_miso : IN t_mem_miso := c_mem_miso_rst;
- reg_unb_sens_mosi : OUT t_mem_mosi;
- reg_unb_sens_miso : IN t_mem_miso := c_mem_miso_rst;
- reg_ppsh_mosi : OUT t_mem_mosi;
- reg_ppsh_miso : IN t_mem_miso := c_mem_miso_rst;
- eth1g_mm_rst : OUT STD_LOGIC;
- eth1g_reg_interrupt : IN STD_LOGIC;
- eth1g_ram_mosi : OUT t_mem_mosi;
- eth1g_ram_miso : IN t_mem_miso := c_mem_miso_rst;
- eth1g_reg_mosi : OUT t_mem_mosi;
- eth1g_reg_miso : IN t_mem_miso := c_mem_miso_rst;
- eth1g_tse_mosi : OUT t_mem_mosi;
- eth1g_tse_miso : IN t_mem_miso := c_mem_miso_rst;
- reg_diag_data_buf_re_mosi : OUT t_mem_mosi;
- reg_diag_data_buf_re_miso : IN t_mem_miso := c_mem_miso_rst;
- ram_diag_data_buf_re_mosi : OUT t_mem_mosi;
- ram_diag_data_buf_re_miso : IN t_mem_miso := c_mem_miso_rst;
- reg_diag_data_buf_im_mosi : OUT t_mem_mosi;
- reg_diag_data_buf_im_miso : IN t_mem_miso := c_mem_miso_rst;
- ram_diag_data_buf_im_mosi : OUT t_mem_mosi;
- ram_diag_data_buf_im_miso : IN t_mem_miso := c_mem_miso_rst;
- reg_diag_bg_mosi : OUT t_mem_mosi;
- reg_diag_bg_miso : IN t_mem_miso := c_mem_miso_rst;
- ram_diag_bg_mosi : OUT t_mem_mosi;
- ram_diag_bg_miso : IN t_mem_miso := c_mem_miso_rst;
- reg_diagnostics_mosi : OUT t_mem_mosi;
- reg_diagnostics_miso : IN t_mem_miso := c_mem_miso_rst;
- reg_tr_nonbonded_mosi : OUT t_mem_mosi;
- reg_tr_nonbonded_miso : IN t_mem_miso := c_mem_miso_rst;
- ram_reorder_row_input_mosi : OUT t_mem_mosi;
- ram_reorder_row_input_miso : IN t_mem_miso := c_mem_miso_rst;
- ram_reorder_row_mesh_mosi : OUT t_mem_mosi;
- ram_reorder_row_mesh_miso : IN t_mem_miso := c_mem_miso_rst
+ mm_clk : IN STD_LOGIC := '1';
+ mm_rst : IN STD_LOGIC := '1';
+ pout_wdi : OUT STD_LOGIC := '1';
+ reg_wdi_mosi : OUT t_mem_mosi;
+ reg_wdi_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_unb_system_info_mosi : OUT t_mem_mosi;
+ reg_unb_system_info_miso : IN t_mem_miso := c_mem_miso_rst;
+ rom_unb_system_info_mosi : OUT t_mem_mosi;
+ rom_unb_system_info_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_unb_sens_mosi : OUT t_mem_mosi;
+ reg_unb_sens_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_ppsh_mosi : OUT t_mem_mosi;
+ reg_ppsh_miso : IN t_mem_miso := c_mem_miso_rst;
+ eth1g_mm_rst : OUT STD_LOGIC;
+ eth1g_reg_interrupt : IN STD_LOGIC;
+ eth1g_ram_mosi : OUT t_mem_mosi;
+ eth1g_ram_miso : IN t_mem_miso := c_mem_miso_rst;
+ eth1g_reg_mosi : OUT t_mem_mosi;
+ eth1g_reg_miso : IN t_mem_miso := c_mem_miso_rst;
+ eth1g_tse_mosi : OUT t_mem_mosi;
+ eth1g_tse_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_diag_data_buf_re_mosi : OUT t_mem_mosi;
+ reg_diag_data_buf_re_miso : IN t_mem_miso := c_mem_miso_rst;
+ ram_diag_data_buf_re_mosi : OUT t_mem_mosi;
+ ram_diag_data_buf_re_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_diag_data_buf_im_mosi : OUT t_mem_mosi;
+ reg_diag_data_buf_im_miso : IN t_mem_miso := c_mem_miso_rst;
+ ram_diag_data_buf_im_mosi : OUT t_mem_mosi;
+ ram_diag_data_buf_im_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_diag_bg_mosi : OUT t_mem_mosi;
+ reg_diag_bg_miso : IN t_mem_miso := c_mem_miso_rst;
+ ram_diag_bg_mosi : OUT t_mem_mosi;
+ ram_diag_bg_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_diagnostics_mosi : OUT t_mem_mosi;
+ reg_diagnostics_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_tr_nonbonded_mosi : OUT t_mem_mosi;
+ reg_tr_nonbonded_miso : IN t_mem_miso := c_mem_miso_rst
);
END ENTITY mmm_apertif_unb1_cor_mesh_ref;
@@ -310,13 +302,13 @@ BEGIN
PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_eth1g_tse : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_TSE")
PORT MAP(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
- u_mm_file_reg_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_RE")
+ u_mm_file_reg_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_RE")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso );
- u_mm_file_ram_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_RE")
+ u_mm_file_ram_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_RE")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso );
- u_mm_file_reg_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_IM")
+ u_mm_file_reg_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_IM")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso );
- u_mm_file_ram_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_IM")
+ u_mm_file_ram_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_IM")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso );
u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
@@ -326,10 +318,6 @@ BEGIN
PORT MAP(mm_rst, mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
u_mm_file_reg_tr_nonbonded : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
PORT MAP(mm_rst, mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
- u_mm_file_ram_reorder_row_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_REORDER_ROW_INPUT")
- PORT MAP(mm_rst, mm_clk, ram_reorder_row_input_mosi, ram_reorder_row_input_miso );
- u_mm_file_ram_reorder_row_mesh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_REORDER_ROW_MESH")
- PORT MAP(mm_rst, mm_clk, ram_reorder_row_mesh_mosi, ram_reorder_row_mesh_miso );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
----------------------------------------------------------------------------