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RTSD
HDL
Commits
787bb09a
Commit
787bb09a
authored
10 years ago
by
Eric Kooistra
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Made wait for xon more robust (in case it is initially 'X') in proc_tech_mac_10g_tx_packet.
parent
c4adc7b4
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libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
+73
-76
73 additions, 76 deletions
libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
with
73 additions
and
76 deletions
libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
+
73
−
76
View file @
787bb09a
...
@@ -203,7 +203,9 @@ PACKAGE BODY tb_tech_mac_10g_pkg IS
...
@@ -203,7 +203,9 @@ PACKAGE BODY tb_tech_mac_10g_pkg IS
VARIABLE
v_hdr_words_arr
:
t_network_total_header_64b_arr
;
VARIABLE
v_hdr_words_arr
:
t_network_total_header_64b_arr
;
BEGIN
BEGIN
ff_src_out
<=
c_dp_sosi_rst
;
ff_src_out
<=
c_dp_sosi_rst
;
IF
ff_src_in
.
xon
=
'1'
THEN
-- Generate this packet
-- Wait until XON is active
proc_common_wait_until_high
(
ff_clk
,
ff_src_in
.
xon
);
-- Generate this packet
-- Select header
-- Select header
CASE
c_data_type
IS
CASE
c_data_type
IS
...
@@ -282,11 +284,6 @@ PACKAGE BODY tb_tech_mac_10g_pkg IS
...
@@ -282,11 +284,6 @@ PACKAGE BODY tb_tech_mac_10g_pkg IS
proc_dp_stream_ready_latency
(
c_ready_latency
,
ff_clk
,
ff_src_in
.
ready
,
ff_en
,
'0'
,
'1'
,
'0'
,
'1'
,
ff_src_out
.
sync
,
ff_src_out
.
valid
,
ff_src_out
.
sop
,
ff_src_out
.
eop
);
proc_dp_stream_ready_latency
(
c_ready_latency
,
ff_clk
,
ff_src_in
.
ready
,
ff_en
,
'0'
,
'1'
,
'0'
,
'1'
,
ff_src_out
.
sync
,
ff_src_out
.
valid
,
ff_src_out
.
sop
,
ff_src_out
.
eop
);
END
IF
;
END
IF
;
ELSE
-- Wait until XON is active
proc_common_wait_until_high
(
ff_clk
,
ff_src_in
.
xon
);
END
IF
;
END
proc_tech_mac_10g_tx_packet
;
END
proc_tech_mac_10g_tx_packet
;
...
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