added 27b complex mult for e2sg

libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl

@@ -34,3 +34,7 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
 vmap altmult_complex_1910 ./work/
 
   vcom  "$IP_DIR/../altmult_complex_1910/sim/ip_arria10_e2sg_complex_mult_altmult_complex_1910_cumkcni.vhd" -work altmult_complex_1910
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult_27b/sim"
+
+  vcom  "$IP_DIR/../altmult_complex_1910/sim/ip_arria10_e2sg_complex_mult_27b_altmult_complex_1910_ecifj3y.vhd" -work altmult_complex_1910

libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl

@@ -30,7 +30,8 @@
 
 
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult/sim"
-vmap altmult_complex_1910 ./work/
-  vcom  "$IP_DIR/../altmult_complex_1910/sim/ip_arria10_e2sg_complex_mult_altmult_complex_1910_cumkcni.vhd" -work altmult_complex_1910
-  vcom "$IP_DIR/ip_arria10_e2sg_complex_mult.vhd"                                                           -work altmult_complex_1910
+  vcom "$IP_DIR/ip_arria10_e2sg_complex_mult.vhd"
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult_27b/sim"
+  vcom "$IP_DIR/ip_arria10_e2sg_complex_mult_27b.vhd"
 

libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg

@@ -17,8 +17,10 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_complex_mult/ip_arria10_e2sg_complex_mult.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_complex_mult_27b/ip_arria10_e2sg_complex_mult_27b.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
     ip_arria10_e2sg_complex_mult.ip
+    ip_arria10_e2sg_complex_mult_27b.ip
 

libraries/technology/mult/tech_complex_mult.vhd

@@ -252,18 +252,18 @@ BEGIN
     br <= RESIZE_SVEC(in_br, c_dsp_mult_27_w);
     bi <= RESIZE_SVEC(in_bi, c_dsp_mult_27_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_27_w);
 
-    --u0 : ip_arria10_e2sg_complex_mult_27b
-    --PORT MAP (
-    --  aclr        => rst,
-    --  clock       => clk,
-    --  dataa_imag  => ai,
-    --  dataa_real  => ar,
-    --  datab_imag  => bi,
-    --  datab_real  => br,
-    --  ena         => clken,
-    --  result_imag => mult_im,
-    --  result_real => mult_re
-    --);
+    u0 : ip_arria10_e2sg_complex_mult_27b
+    PORT MAP (
+      aclr        => rst,
+      clock       => clk,
+      dataa_imag  => ai,
+      dataa_real  => ar,
+      datab_imag  => bi,
+      datab_real  => br,
+      ena         => clken,
+      result_imag => mult_im,
+      result_real => mult_re
+    );
 
     -- Back to true input widths and then resize for output width
     result_re <= RESIZE_SVEC(mult_re, g_out_p_w);