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Commit d9959642 authored by Reinier van der Walle's avatar Reinier van der Walle
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added 27 bit complex mult to hdllib

parent 3ec3ea5e
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1 merge request!147L2SDP-494
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libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
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......@@ -17,6 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
$RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult.qip
$RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult_27b/ip_arria10_e1sg_complex_mult_27b.qip
[generate_ip_libs]
qsys-generate_ip_files =
......
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