merge master into STAT-266 to stay in sync.

Merge branch 'master' into STAT-266

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board_spec.xml

@@ -31,6 +31,13 @@
     <interface name="board" port="kernel_stream_snk_10GbE" type="streamsink" width="72" chan_id="kernel_output_10GbE"/>
     <interface name="board" port="kernel_stream_src_40GbE" type="streamsource" width="264" chan_id="kernel_input_40GbE"/>
     <interface name="board" port="kernel_stream_snk_40GbE" type="streamsink" width="264" chan_id="kernel_output_40GbE"/>
+
+    <!-- Ring interface, ring_0 is to PN to the left. Ring_1 is to PN to the right  -->
+    <interface name="board" port="kernel_stream_src_40GbE_ring_0" type="streamsource" width="264" chan_id="kernel_input_40GbE_ring_0"/>
+    <interface name="board" port="kernel_stream_snk_40GbE_ring_0" type="streamsink" width="264" chan_id="kernel_output_40GbE_ring_0"/>
+    <interface name="board" port="kernel_stream_src_40GbE_ring_1" type="streamsource" width="264" chan_id="kernel_input_40GbE_ring_1"/>
+    <interface name="board" port="kernel_stream_snk_40GbE_ring_1" type="streamsink" width="264" chan_id="kernel_output_40GbE_ring_1"/>
+
     <interface name="board" port="kernel_stream_src_ADC" type="streamsource" width="16" chan_id="kernel_input_ADC"/>
   </channels>
 

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/flat.qsf

@@ -492,7 +492,202 @@ set_location_assignment PIN_U12 -to JESD204B_SYNC[0]
 set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[0]
 
 
-set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_40GbE.ip
-set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_10GbE.ip
-set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_1GbE_mc.ip
-set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_jesd204b.ip
+set_location_assignment PIN_AP40 -to RING_0_RX[0]
+set_location_assignment PIN_AR38 -to RING_0_RX[1]
+set_location_assignment PIN_AT40 -to RING_0_RX[2]
+set_location_assignment PIN_AU38 -to RING_0_RX[3]
+set_location_assignment PIN_AP44 -to RING_0_TX[0]
+set_location_assignment PIN_AR42 -to RING_0_TX[1]
+set_location_assignment PIN_AT44 -to RING_0_TX[2]
+set_location_assignment PIN_AU42 -to RING_0_TX[3]
+set_location_assignment PIN_H40 -to RING_1_RX[0]
+set_location_assignment PIN_J38 -to RING_1_RX[1]
+set_location_assignment PIN_F40 -to RING_1_RX[2]
+set_location_assignment PIN_G38 -to RING_1_RX[3]
+set_location_assignment PIN_H44 -to RING_1_TX[0]
+set_location_assignment PIN_J42 -to RING_1_TX[1]
+set_location_assignment PIN_G42 -to RING_1_TX[2]
+set_location_assignment PIN_F44 -to RING_1_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_0_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_0_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_0_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_0_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_RX[3]
+
+
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_1_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_1_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_1_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_RX[3]
+
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_0_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_0_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_0_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_0_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[3]
+
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_1_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_1_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_1_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[3]
+
+
+set_global_assignment -name IP_FILE ip/board/board_reg_ta2_unb2b_jesd204b.ip

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/hdllib.cfg

+hdl_lib_name = ta2_unb2b_top
+hdl_library_clause_name = ta2_unb2b_top_lib
+hdl_lib_uses_synth = common technology dp unb2b_board ta2_unb2b_40GbE ta2_unb2b_10GbE ta2_unb2b_1GbE_mc ta2_unb2b_jesd204b
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+hdl_lib_include_ip = 
+
+synth_files =
+  top_components_pkg.vhd
+  ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
+  ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
+  ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd
+  ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
+  top.vhd
+test_bench_files =     
+
+regression_test_vhdl = 
+    
+[modelsim_project_file]
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+    
+
+quartus_vhdl_files = 
+
+quartus_qip_files =

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_cpu_0.ip

@@ -2218,7 +2218,7 @@
         <spirit:parameter>
           <spirit:name>dataSlaveMapParam</spirit:name>
           <spirit:displayName>dataSlaveMapParam</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x8000' end='0x9000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x9000' end='0xA000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
+          <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='reg_ta2_unb2b_jesd204b.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
         </spirit:parameter>
         <spirit:parameter>
           <spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
                 <suppliedSystemInfos>
                     <entry>
                         <key>ADDRESS_MAP</key>
-                        <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='kernel_clk_gen.ctrl' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x8000' end='0x9000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x9000' end='0xA000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                        <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /&gt;&lt;slave name='reg_ta2_unb2b_jesd204b.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /&gt;&lt;slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                     </entry>
                     <entry>
                         <key>ADDRESS_WIDTH</key>

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/freeze_wrapper.v

@@ -63,6 +63,20 @@ module freeze_wrapper(
   output wire         board_kernel_stream_snk_40GbE_valid,
   input  wire         board_kernel_stream_snk_40GbE_ready,
   
+  input  wire [263:0] board_kernel_stream_src_40GbE_ring_0_data,
+  input  wire         board_kernel_stream_src_40GbE_ring_0_valid,
+  output wire         board_kernel_stream_src_40GbE_ring_0_ready,
+  output wire [263:0] board_kernel_stream_snk_40GbE_ring_0_data,
+  output wire         board_kernel_stream_snk_40GbE_ring_0_valid,
+  input  wire         board_kernel_stream_snk_40GbE_ring_0_ready,
+  
+  input  wire [263:0] board_kernel_stream_src_40GbE_ring_1_data,
+  input  wire         board_kernel_stream_src_40GbE_ring_1_valid,
+  output wire         board_kernel_stream_src_40GbE_ring_1_ready,
+  output wire [263:0] board_kernel_stream_snk_40GbE_ring_1_data,
+  output wire         board_kernel_stream_snk_40GbE_ring_1_valid,
+  input  wire         board_kernel_stream_snk_40GbE_ring_1_ready,
+
   output [6:0]     board_kernel_register_mem_address,                
   output           board_kernel_register_mem_clken,      
   output           board_kernel_register_mem_chipselect, 
@@ -187,28 +201,45 @@ pr_region pr_region_inst
   .kernel_cra_debugaccess(board_kernel_cra_debugaccess),
 
 
-
   .kernel_stream_src_40GbE_data(board_kernel_stream_src_40GbE_data),
   .kernel_stream_src_40GbE_ready(board_kernel_stream_src_40GbE_ready),
   .kernel_stream_src_40GbE_valid(board_kernel_stream_src_40GbE_valid),
   .kernel_stream_snk_40GbE_data(board_kernel_stream_snk_40GbE_data),
   .kernel_stream_snk_40GbE_ready(board_kernel_stream_snk_40GbE_ready),
   .kernel_stream_snk_40GbE_valid(board_kernel_stream_snk_40GbE_valid),
+
+  .kernel_stream_src_40GbE_ring_0_data(board_kernel_stream_src_40GbE_ring_0_data),
+  .kernel_stream_src_40GbE_ring_0_ready(board_kernel_stream_src_40GbE_ring_0_ready),
+  .kernel_stream_src_40GbE_ring_0_valid(board_kernel_stream_src_40GbE_ring_0_valid),
+  .kernel_stream_snk_40GbE_ring_0_data(board_kernel_stream_snk_40GbE_ring_0_data),
+  .kernel_stream_snk_40GbE_ring_0_ready(board_kernel_stream_snk_40GbE_ring_0_ready),
+  .kernel_stream_snk_40GbE_ring_0_valid(board_kernel_stream_snk_40GbE_ring_0_valid),
+
+  .kernel_stream_src_40GbE_ring_1_data(board_kernel_stream_src_40GbE_ring_1_data),
+  .kernel_stream_src_40GbE_ring_1_ready(board_kernel_stream_src_40GbE_ring_1_ready),
+  .kernel_stream_src_40GbE_ring_1_valid(board_kernel_stream_src_40GbE_ring_1_valid),
+  .kernel_stream_snk_40GbE_ring_1_data(board_kernel_stream_snk_40GbE_ring_1_data),
+  .kernel_stream_snk_40GbE_ring_1_ready(board_kernel_stream_snk_40GbE_ring_1_ready),
+  .kernel_stream_snk_40GbE_ring_1_valid(board_kernel_stream_snk_40GbE_ring_1_valid),
+
   .kernel_stream_src_10GbE_data(board_kernel_stream_src_10GbE_data),
   .kernel_stream_src_10GbE_ready(board_kernel_stream_src_10GbE_ready),
   .kernel_stream_src_10GbE_valid(board_kernel_stream_src_10GbE_valid),
   .kernel_stream_snk_10GbE_data(board_kernel_stream_snk_10GbE_data),
   .kernel_stream_snk_10GbE_ready(board_kernel_stream_snk_10GbE_ready),
   .kernel_stream_snk_10GbE_valid(board_kernel_stream_snk_10GbE_valid),
+
   .kernel_stream_src_1GbE_data(board_kernel_stream_src_1GbE_data),
   .kernel_stream_src_1GbE_ready(board_kernel_stream_src_1GbE_ready),
   .kernel_stream_src_1GbE_valid(board_kernel_stream_src_1GbE_valid),
   .kernel_stream_snk_1GbE_data(board_kernel_stream_snk_1GbE_data),
   .kernel_stream_snk_1GbE_ready(board_kernel_stream_snk_1GbE_ready),
   .kernel_stream_snk_1GbE_valid(board_kernel_stream_snk_1GbE_valid),
+
   .kernel_stream_src_ADC_data(board_kernel_stream_src_ADC_data),
   .kernel_stream_src_ADC_ready(board_kernel_stream_src_ADC_ready),
   .kernel_stream_src_ADC_valid(board_kernel_stream_src_ADC_valid),
+
   .kernel_register_mem_address(board_kernel_register_mem_address),  
   .kernel_register_mem_clken(board_kernel_register_mem_clken),  
   .kernel_register_mem_chipselect(board_kernel_register_mem_chipselect),  

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/pr_region.v

@@ -66,7 +66,21 @@ module pr_region (
   output wire         kernel_stream_src_40GbE_ready,
   output wire [263:0] kernel_stream_snk_40GbE_data,
   output wire         kernel_stream_snk_40GbE_valid,
-  input  wire         kernel_stream_snk_40GbE_ready
+  input  wire         kernel_stream_snk_40GbE_ready,
+
+  input  wire [263:0] kernel_stream_src_40GbE_ring_0_data,
+  input  wire         kernel_stream_src_40GbE_ring_0_valid,
+  output wire         kernel_stream_src_40GbE_ring_0_ready,
+  output wire [263:0] kernel_stream_snk_40GbE_ring_0_data,
+  output wire         kernel_stream_snk_40GbE_ring_0_valid,
+  input  wire         kernel_stream_snk_40GbE_ring_0_ready,
+
+  input  wire [263:0] kernel_stream_src_40GbE_ring_1_data,
+  input  wire         kernel_stream_src_40GbE_ring_1_valid,
+  output wire         kernel_stream_src_40GbE_ring_1_ready,
+  output wire [263:0] kernel_stream_snk_40GbE_ring_1_data,
+  output wire         kernel_stream_snk_40GbE_ring_1_valid,
+  input  wire         kernel_stream_snk_40GbE_ring_1_ready
 
 
 //  input  wire         kernel_mem0_waitrequest,
@@ -179,6 +193,24 @@ kernel_system kernel_system_inst
   .kernel_output_40GbE_valid(kernel_stream_snk_40GbE_valid),
 
 
+  .kernel_input_40GbE_ring_0_data(kernel_stream_src_40GbE_ring_0_data),
+  .kernel_input_40GbE_ring_0_ready(kernel_stream_src_40GbE_ring_0_ready),
+  .kernel_input_40GbE_ring_0_valid(kernel_stream_src_40GbE_ring_0_valid),
+
+  .kernel_output_40GbE_ring_0_data(kernel_stream_snk_40GbE_ring_0_data),
+  .kernel_output_40GbE_ring_0_ready(kernel_stream_snk_40GbE_ring_0_ready),
+  .kernel_output_40GbE_ring_0_valid(kernel_stream_snk_40GbE_ring_0_valid),
+
+
+  .kernel_input_40GbE_ring_1_data(kernel_stream_src_40GbE_ring_1_data),
+  .kernel_input_40GbE_ring_1_ready(kernel_stream_src_40GbE_ring_1_ready),
+  .kernel_input_40GbE_ring_1_valid(kernel_stream_src_40GbE_ring_1_valid),
+
+  .kernel_output_40GbE_ring_1_data(kernel_stream_snk_40GbE_ring_1_data),
+  .kernel_output_40GbE_ring_1_ready(kernel_stream_snk_40GbE_ring_1_ready),
+  .kernel_output_40GbE_ring_1_valid(kernel_stream_snk_40GbE_ring_1_valid),
+
+
   .kernel_input_10GbE_data(kernel_stream_src_10GbE_data),
   .kernel_input_10GbE_ready(kernel_stream_src_10GbE_ready),
   .kernel_input_10GbE_valid(kernel_stream_src_10GbE_valid),

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd

@@ -200,7 +200,7 @@ BEGIN
   dp_latency_adapter_tx_snk_in.valid <= kernel_snk_valid;
   kernel_snk_ready <= dp_latency_adapter_tx_snk_out.ready; -- Flow control towards source (kernel)
 
-  rx_status <= dp_latency_adapter_tx_snk_out.xon;
+  rx_status <= dp_xonoff_src_in.xon; -- use xonoff_src_in for status as xonoff_snk_out is always '1'
 
   tx_serial_r <= unb2_board_front_io_serial_tx_arr(0);
   unb2_board_front_io_serial_rx_arr(0) <= rx_serial_r;

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/hdllib.cfg

+hdl_lib_name = ta2_unb2b_40GbE
+hdl_library_clause_name = ta2_unb2b_40GbE_lib
+hdl_lib_uses_synth = common technology dp  
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+hdl_lib_include_ip = 
+
+synth_files =
+  ta2_unb2b_40GbE.vhd
+test_bench_files =     
+
+regression_test_vhdl = 
+    
+[modelsim_project_file]
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+    
+
+quartus_vhdl_files = 
+
+quartus_qip_files =