diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board.qsys b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board.qsys
index 038de3352891ea89acd49085cfdc04bf8e703bcf..ec14d09d4a9024ef87279827b4eb3360f610754c 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board.qsys
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board.qsys
@@ -46,7 +46,7 @@
{
datum _sortIndex
{
- value = "24";
+ value = "25";
type = "int";
}
}
@@ -102,7 +102,7 @@
{
datum _sortIndex
{
- value = "23";
+ value = "24";
type = "int";
}
}
@@ -110,7 +110,7 @@
{
datum _sortIndex
{
- value = "21";
+ value = "22";
type = "int";
}
}
@@ -126,7 +126,7 @@
{
datum _sortIndex
{
- value = "22";
+ value = "23";
type = "int";
}
}
@@ -380,6 +380,22 @@
type = "String";
}
}
+ element reg_ta2_unb2b_jesd204b
+ {
+ datum _sortIndex
+ {
+ value = "21";
+ type = "int";
+ }
+ }
+ element reg_ta2_unb2b_jesd204b.mem
+ {
+ datum baseAddress
+ {
+ value = "1024";
+ type = "String";
+ }
+ }
element reg_unb_pmbus
{
datum _sortIndex
@@ -464,46 +480,6 @@
type = "String";
}
}
- element ta2_unb2b_10GbE
- {
- datum _sortIndex
- {
- value = "26";
- type = "int";
- }
- }
- element ta2_unb2b_1GbE_mc
- {
- datum _sortIndex
- {
- value = "27";
- type = "int";
- }
- }
- element ta2_unb2b_40GbE
- {
- datum _sortIndex
- {
- value = "25";
- type = "int";
- }
- }
- element ta2_unb2b_jesd204b
- {
- datum _sortIndex
- {
- value = "28";
- type = "int";
- }
- }
- element ta2_unb2b_jesd204b.mem
- {
- datum baseAddress
- {
- value = "1024";
- type = "String";
- }
- }
element timer_0
{
datum _sortIndex
@@ -522,6 +498,7 @@
}
}
]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115U2F45E1SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="1" />
@@ -532,6 +509,7 @@
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="0" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
@@ -595,6 +573,18 @@
</consumedSystemInfos>
</value>
</entry>
+ <entry>
+ <key>rom_system_info_clk</key>
+ <value>
+ <connectionPointName>rom_system_info_clk</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
</connPtSystemInfos>
</systemInfosDefinition>]]></parameter>
<parameter name="systemScripts" value="" />
@@ -1072,6 +1062,46 @@
internal="reg_remu.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_ta2_unb2b_jesd204b_address"
+ internal="reg_ta2_unb2b_jesd204b.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ta2_unb2b_jesd204b_clk"
+ internal="reg_ta2_unb2b_jesd204b.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ta2_unb2b_jesd204b_read"
+ internal="reg_ta2_unb2b_jesd204b.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ta2_unb2b_jesd204b_readdata"
+ internal="reg_ta2_unb2b_jesd204b.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ta2_unb2b_jesd204b_reset"
+ internal="reg_ta2_unb2b_jesd204b.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ta2_unb2b_jesd204b_waitrequest"
+ internal="reg_ta2_unb2b_jesd204b.waitrequest"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ta2_unb2b_jesd204b_write"
+ internal="reg_ta2_unb2b_jesd204b.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ta2_unb2b_jesd204b_writedata"
+ internal="reg_ta2_unb2b_jesd204b.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_unb_pmbus_address"
internal="reg_unb_pmbus.address"
@@ -1205,131 +1235,6 @@
internal="rom_system_info.writedata"
type="conduit"
dir="end" />
- <interface
- name="ta2_unb2b_10gbe_kernel_snk"
- internal="ta2_unb2b_10GbE.kernel_snk"
- type="avalon_streaming"
- dir="end" />
- <interface
- name="ta2_unb2b_10gbe_kernel_src"
- internal="ta2_unb2b_10GbE.kernel_src"
- type="avalon_streaming"
- dir="start" />
- <interface
- name="ta2_unb2b_10gbe_refclk"
- internal="ta2_unb2b_10GbE.refclk"
- type="clock"
- dir="end" />
- <interface
- name="ta2_unb2b_10gbe_rx_serial_data"
- internal="ta2_unb2b_10GbE.rx_serial_data"
- type="conduit"
- dir="end" />
- <interface
- name="ta2_unb2b_10gbe_rx_status"
- internal="ta2_unb2b_10GbE.rx_status"
- type="conduit"
- dir="end" />
- <interface
- name="ta2_unb2b_10gbe_tx_serial_data"
- internal="ta2_unb2b_10GbE.tx_serial_data"
- type="conduit"
- dir="end" />
- <interface
- name="ta2_unb2b_1gbe_mc_kernel_snk"
- internal="ta2_unb2b_1GbE_mc.kernel_snk"
- type="avalon_streaming"
- dir="end" />
- <interface
- name="ta2_unb2b_1gbe_mc_kernel_src"
- internal="ta2_unb2b_1GbE_mc.kernel_src"
- type="avalon_streaming"
- dir="start" />
- <interface
- name="ta2_unb2b_1gbe_mc_st_clk"
- internal="ta2_unb2b_1GbE_mc.st_clk"
- type="clock"
- dir="end" />
- <interface
- name="ta2_unb2b_1gbe_mc_st_rst"
- internal="ta2_unb2b_1GbE_mc.st_rst"
- type="reset"
- dir="end" />
- <interface
- name="ta2_unb2b_1gbe_mc_udp_rx_snk_in"
- internal="ta2_unb2b_1GbE_mc.udp_rx_snk_in"
- type="avalon_streaming"
- dir="end" />
- <interface
- name="ta2_unb2b_1gbe_mc_udp_rx_snk_in_xon"
- internal="ta2_unb2b_1GbE_mc.udp_rx_snk_in_xon"
- type="conduit"
- dir="end" />
- <interface
- name="ta2_unb2b_1gbe_mc_udp_tx_src_out"
- internal="ta2_unb2b_1GbE_mc.udp_tx_src_out"
- type="avalon_streaming"
- dir="start" />
- <interface
- name="ta2_unb2b_1gbe_mc_udp_tx_src_out_xon"
- internal="ta2_unb2b_1GbE_mc.udp_tx_src_out_xon"
- type="conduit"
- dir="end" />
- <interface
- name="ta2_unb2b_40gbe_kernel_snk"
- internal="ta2_unb2b_40GbE.kernel_snk"
- type="avalon_streaming"
- dir="end" />
- <interface
- name="ta2_unb2b_40gbe_kernel_src"
- internal="ta2_unb2b_40GbE.kernel_src"
- type="avalon_streaming"
- dir="start" />
- <interface
- name="ta2_unb2b_40gbe_refclk"
- internal="ta2_unb2b_40GbE.refclk"
- type="clock"
- dir="end" />
- <interface
- name="ta2_unb2b_40gbe_rx_serial_data"
- internal="ta2_unb2b_40GbE.rx_serial_data"
- type="conduit"
- dir="end" />
- <interface
- name="ta2_unb2b_40gbe_rx_status"
- internal="ta2_unb2b_40GbE.rx_status"
- type="conduit"
- dir="end" />
- <interface
- name="ta2_unb2b_40gbe_tx_serial_data"
- internal="ta2_unb2b_40GbE.tx_serial_data"
- type="conduit"
- dir="end" />
- <interface
- name="ta2_unb2b_jesd204b_jesd204b_refclk"
- internal="ta2_unb2b_jesd204b.jesd204b_refclk"
- type="clock"
- dir="end" />
- <interface
- name="ta2_unb2b_jesd204b_jesd204b_sync_n"
- internal="ta2_unb2b_jesd204b.jesd204b_sync_n"
- type="conduit"
- dir="end" />
- <interface
- name="ta2_unb2b_jesd204b_jesd204b_sysref"
- internal="ta2_unb2b_jesd204b.jesd204b_sysref"
- type="conduit"
- dir="end" />
- <interface
- name="ta2_unb2b_jesd204b_kernel_src"
- internal="ta2_unb2b_jesd204b.kernel_src"
- type="avalon_streaming"
- dir="start" />
- <interface
- name="ta2_unb2b_jesd204b_serial_rx_arr"
- internal="ta2_unb2b_jesd204b.serial_rx_arr"
- type="conduit"
- dir="end" />
<module
name="avs_eth_0"
kind="altera_generic_component"
@@ -2842,6483 +2747,38 @@
</connPtSystemInfos>
</systemInfos>
</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>interrupt</name>
- <type>interrupt</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>ins_interrupt_irq</name>
- <role>irq</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- <value>avs_eth_0.mms_reg</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>mm</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>mm_reset</value>
- </entry>
- <entry>
- <key>bridgedReceiverOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToReceiver</key>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>irq</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_irq_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mm</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_mm_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mm_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_mm_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>mm</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mms_ram</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>mms_ram_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>10</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>mms_ram_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>mms_ram_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>mms_ram_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>mms_ram_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>mm</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>mm_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>2</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mms_reg</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>mms_reg_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>mms_reg_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>mms_reg_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>mms_reg_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>mms_reg_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>64</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>mm</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>mm_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mms_tse</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>mms_tse_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>10</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>mms_tse_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>mms_tse_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>mms_tse_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>mms_tse_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>mms_tse_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>mm</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>mm_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>ram_address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_ram_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>10</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>ram_read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_ram_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>ram_readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_ram_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>ram_write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_ram_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>ram_writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_ram_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reg_address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reg_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reg_read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reg_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reg_readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reg_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reg_write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reg_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reg_writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reg_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>tse_address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_tse_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>10</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>tse_read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_tse_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>tse_readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_tse_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>tse_waitrequest</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_tse_waitrequest_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>tse_write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_tse_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>tse_writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_tse_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_avs_eth_0</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>board_avs_eth_0</fileSetName>
- <fileSetFixedName>board_avs_eth_0</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>board_avs_eth_0</fileSetName>
- <fileSetFixedName>board_avs_eth_0</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>board_avs_eth_0</fileSetName>
- <fileSetFixedName>board_avs_eth_0</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_avs_eth_0.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="board_onchip_memory"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>clk1</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset1</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>reset_req</name>
- <role>reset_req</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>s1</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>7</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>clken</name>
- <role>clken</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>chipselect</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>256</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>256</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>byteenable</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset1</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>true</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>altera_avalon_onchip_memory2</className>
- <version>19.1</version>
- <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>autoInitializationFileName</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>UNIQUE_ID</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>NONE</parameterDefaultValue>
- <parameterName>deviceFamily</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE_FAMILY</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>NONE</parameterDefaultValue>
- <parameterName>deviceFeatures</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE_FEATURES</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>s1</key>
- <value>
- <connectionPointName>s1</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='s1' start='0x0' end='0x1000' datawidth='256' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>12</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>256</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>clk1</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset1</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>reset_req</name>
- <role>reset_req</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>s1</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>7</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>clken</name>
- <role>clken</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>chipselect</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>256</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>256</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>byteenable</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset1</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>true</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_onchip_memory</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>board_onchip_memory</fileSetName>
- <fileSetFixedName>board_onchip_memory</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>board_onchip_memory</fileSetName>
- <fileSetFixedName>board_onchip_memory</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>board_onchip_memory</fileSetName>
- <fileSetFixedName>board_onchip_memory</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_onchip_memory.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.CONTENTS_INFO</key>
- <value>""</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.DUAL_PORT</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</key>
- <value>AUTO</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.INIT_CONTENTS_FILE</key>
- <value>board_onchip_memory_board_onchip_memory</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.INIT_MEM_CONTENT</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.INSTANCE_ID</key>
- <value>NONE</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.RAM_BLOCK_TYPE</key>
- <value>AUTO</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.READ_DURING_WRITE_MODE</key>
- <value>DONT_CARE</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.SINGLE_CLOCK_OP</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.SIZE_MULTIPLE</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.SIZE_VALUE</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.WRITABLE</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</key>
- <value>SIM_DIR</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.GENERATE_DAT_SYM</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.GENERATE_HEX</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.HAS_BYTE_LANE</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.HEX_INSTALL_DIR</key>
- <value>QPF_DIR</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</key>
- <value>256</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.MEM_INIT_FILENAME</key>
- <value>board_onchip_memory_board_onchip_memory</value>
- </entry>
- <entry>
- <key>postgeneration.simulation.init_file.param_name</key>
- <value>INIT_FILE</value>
- </entry>
- <entry>
- <key>postgeneration.simulation.init_file.type</key>
- <value>MEM_INIT</value>
- </entry>
- </assignmentValueMap>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="clk_0"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>clk_out</name>
- <role>clk</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedDirectClock</key>
- <value>clk_in</value>
- </entry>
- <entry>
- <key>clockRate</key>
- <value>100000000</value>
- </entry>
- <entry>
- <key>clockRateKnown</key>
- <value>true</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>true</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_in</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>in_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>clk</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>100000000</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_in_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>reset</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_reset</name>
- <type>reset</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>reset_n_out</name>
- <role>reset_n</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedDirectReset</key>
- <value>clk_in_reset</value>
- </entry>
- <entry>
- <key>associatedResetSinks</key>
- <value>clk_in_reset</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>clock_source</className>
- <displayName>Clock Source</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>0</parameterDefaultValue>
- <parameterName>inputClockFrequency</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>clk_in</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>clk</key>
- <value>
- <connectionPointName>clk</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>clk_in</key>
- <value>
- <connectionPointName>clk_in</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>0</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>clk_out</name>
- <role>clk</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedDirectClock</key>
- <value>clk_in</value>
- </entry>
- <entry>
- <key>clockRate</key>
- <value>100000000</value>
- </entry>
- <entry>
- <key>clockRateKnown</key>
- <value>true</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>true</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_in</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>in_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>clk</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>100000000</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_in_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>reset</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_reset</name>
- <type>reset</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>reset_n_out</name>
- <role>reset_n</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedDirectReset</key>
- <value>clk_in_reset</value>
- </entry>
- <entry>
- <key>associatedResetSinks</key>
- <value>clk_in_reset</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_clk_0</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>board_clk_0</fileSetName>
- <fileSetFixedName>board_clk_0</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>board_clk_0</fileSetName>
- <fileSetFixedName>board_clk_0</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>board_clk_0</fileSetName>
- <fileSetFixedName>board_clk_0</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_clk_0.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="cpu_0"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>custom_instruction_master</name>
- <type>nios_custom_instruction</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>dummy_ci_port</name>
- <role>readra</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>CIName</key>
- <value></value>
- </entry>
- <entry>
- <key>addressWidth</key>
- <value>8</value>
- </entry>
- <entry>
- <key>clockCycle</key>
- <value>0</value>
- </entry>
- <entry>
- <key>enabled</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxAddressWidth</key>
- <value>8</value>
- </entry>
- <entry>
- <key>opcodeExtension</key>
- <value>0</value>
- </entry>
- <entry>
- <key>sharedCombinationalAndMulticycle</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>data_master</name>
- <type>avalon</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>d_address</name>
- <role>address</role>
- <direction>Output</direction>
- <width>18</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>d_byteenable</name>
- <role>byteenable</role>
- <direction>Output</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>d_read</name>
- <role>read</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>d_readdata</name>
- <role>readdata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>d_waitrequest</name>
- <role>waitrequest</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>d_write</name>
- <role>write</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>d_writedata</name>
- <role>writedata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_debugaccess_to_roms</name>
- <role>debugaccess</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>debug.providesServices</key>
- <value>master</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>adaptsTo</key>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>1</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>SYMBOLS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>true</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>dBSBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>doStreamReads</key>
- <value>false</value>
- </entry>
- <entry>
- <key>doStreamWrites</key>
- <value>false</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isAsynchronous</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isReadable</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isWriteable</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxAddressWidth</key>
- <value>32</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>true</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>debug_mem_slave</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>debug_mem_slave_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>9</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_byteenable</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_debugaccess</name>
- <role>debugaccess</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.hideDevice</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>qsys.ui.connect</key>
- <value>instruction_master,data_master</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>2048</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>true</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>true</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>debug_reset_request</name>
- <type>reset</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>debug_reset_request</name>
- <role>reset</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedDirectReset</key>
- </entry>
- <entry>
- <key>associatedResetSinks</key>
- <value>none</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>instruction_master</name>
- <type>avalon</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>i_address</name>
- <role>address</role>
- <direction>Output</direction>
- <width>18</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>i_read</name>
- <role>read</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>i_readdata</name>
- <role>readdata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>i_waitrequest</name>
- <role>waitrequest</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>adaptsTo</key>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>1</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>SYMBOLS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>true</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>dBSBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>doStreamReads</key>
- <value>false</value>
- </entry>
- <entry>
- <key>doStreamWrites</key>
- <value>false</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isAsynchronous</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isReadable</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isWriteable</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>true</value>
- </entry>
- <entry>
- <key>maxAddressWidth</key>
- <value>32</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>irq</name>
- <type>interrupt</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>irq</name>
- <role>irq</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- <value>cpu_0.data_master</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>irqMap</key>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>INDIVIDUAL_REQUESTS</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>reset_req</name>
- <role>reset_req</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>altera_nios2_gen2</className>
- <version>19.1</version>
- <displayName>Nios II Processor</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_CLK_CLOCK_DOMAIN</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>clk</systemInfoArgs>
- <systemInfotype>CLOCK_DOMAIN</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_CLK_RESET_DOMAIN</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>clk</systemInfoArgs>
- <systemInfotype>RESET_DOMAIN</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>AUTO_DEVICE</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>50000000</parameterDefaultValue>
- <parameterName>clockFrequency</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>clk</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>customInstSlavesSystemInfo</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>custom_instruction_master</systemInfoArgs>
- <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>customInstSlavesSystemInfo_nios_a</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>custom_instruction_master_a</systemInfoArgs>
- <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>customInstSlavesSystemInfo_nios_b</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>custom_instruction_master_b</systemInfoArgs>
- <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>customInstSlavesSystemInfo_nios_c</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>custom_instruction_master_c</systemInfoArgs>
- <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>1</parameterDefaultValue>
- <parameterName>dataAddrWidth</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>data_master</systemInfoArgs>
- <systemInfotype>ADDRESS_WIDTH</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>1</parameterDefaultValue>
- <parameterName>dataMasterHighPerformanceAddrWidth</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>data_master_high_performance</systemInfoArgs>
- <systemInfotype>ADDRESS_WIDTH</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>dataMasterHighPerformanceMapParam</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>data_master_high_performance</systemInfoArgs>
- <systemInfotype>ADDRESS_MAP</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>dataSlaveMapParam</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>data_master</systemInfoArgs>
- <systemInfotype>ADDRESS_MAP</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>STRATIXIV</parameterDefaultValue>
- <parameterName>deviceFamilyName</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE_FAMILY</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>deviceFeaturesSystemInfo</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE_FEATURES</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>1</parameterDefaultValue>
- <parameterName>faAddrWidth</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>flash_instruction_master</systemInfoArgs>
- <systemInfotype>ADDRESS_WIDTH</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>faSlaveMapParam</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>flash_instruction_master</systemInfoArgs>
- <systemInfotype>ADDRESS_MAP</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>1</parameterDefaultValue>
- <parameterName>instAddrWidth</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>instruction_master</systemInfoArgs>
- <systemInfotype>ADDRESS_WIDTH</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>instSlaveMapParam</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>instruction_master</systemInfoArgs>
- <systemInfotype>ADDRESS_MAP</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>1</parameterDefaultValue>
- <parameterName>instructionMasterHighPerformanceAddrWidth</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>instruction_master_high_performance</systemInfoArgs>
- <systemInfotype>ADDRESS_WIDTH</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>instructionMasterHighPerformanceMapParam</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>instruction_master_high_performance</systemInfoArgs>
- <systemInfotype>ADDRESS_MAP</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>0</parameterDefaultValue>
- <parameterName>internalIrqMaskSystemInfo</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>irq</systemInfoArgs>
- <systemInfotype>INTERRUPTS_USED</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>1</parameterDefaultValue>
- <parameterName>tightlyCoupledDataMaster0AddrWidth</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>tightly_coupled_data_master_0</systemInfoArgs>
- <systemInfotype>ADDRESS_WIDTH</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>tightlyCoupledDataMaster0MapParam</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>tightly_coupled_data_master_0</systemInfoArgs>
- <systemInfotype>ADDRESS_MAP</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>1</parameterDefaultValue>
- <parameterName>tightlyCoupledDataMaster1AddrWidth</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>tightly_coupled_data_master_1</systemInfoArgs>
- <systemInfotype>ADDRESS_WIDTH</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>tightlyCoupledDataMaster1MapParam</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>tightly_coupled_data_master_1</systemInfoArgs>
- <systemInfotype>ADDRESS_MAP</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>1</parameterDefaultValue>
- <parameterName>tightlyCoupledDataMaster2AddrWidth</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>tightly_coupled_data_master_2</systemInfoArgs>
- <systemInfotype>ADDRESS_WIDTH</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>tightlyCoupledDataMaster2MapParam</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>tightly_coupled_data_master_2</systemInfoArgs>
- <systemInfotype>ADDRESS_MAP</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>1</parameterDefaultValue>
- <parameterName>tightlyCoupledDataMaster3AddrWidth</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>tightly_coupled_data_master_3</systemInfoArgs>
- <systemInfotype>ADDRESS_WIDTH</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>tightlyCoupledDataMaster3MapParam</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>tightly_coupled_data_master_3</systemInfoArgs>
- <systemInfotype>ADDRESS_MAP</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>1</parameterDefaultValue>
- <parameterName>tightlyCoupledInstructionMaster0AddrWidth</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>tightly_coupled_instruction_master_0</systemInfoArgs>
- <systemInfotype>ADDRESS_WIDTH</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>tightlyCoupledInstructionMaster0MapParam</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>tightly_coupled_instruction_master_0</systemInfoArgs>
- <systemInfotype>ADDRESS_MAP</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>1</parameterDefaultValue>
- <parameterName>tightlyCoupledInstructionMaster1AddrWidth</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>tightly_coupled_instruction_master_1</systemInfoArgs>
- <systemInfotype>ADDRESS_WIDTH</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>tightlyCoupledInstructionMaster1MapParam</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>tightly_coupled_instruction_master_1</systemInfoArgs>
- <systemInfotype>ADDRESS_MAP</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>1</parameterDefaultValue>
- <parameterName>tightlyCoupledInstructionMaster2AddrWidth</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>tightly_coupled_instruction_master_2</systemInfoArgs>
- <systemInfotype>ADDRESS_WIDTH</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>tightlyCoupledInstructionMaster2MapParam</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>tightly_coupled_instruction_master_2</systemInfoArgs>
- <systemInfotype>ADDRESS_MAP</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>1</parameterDefaultValue>
- <parameterName>tightlyCoupledInstructionMaster3AddrWidth</parameterName>
- <parameterType>java.lang.Integer</parameterType>
- <systemInfoArgs>tightly_coupled_instruction_master_3</systemInfoArgs>
- <systemInfotype>ADDRESS_WIDTH</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>tightlyCoupledInstructionMaster3MapParam</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfoArgs>tightly_coupled_instruction_master_3</systemInfoArgs>
- <systemInfotype>ADDRESS_MAP</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>clk</key>
- <value>
- <connectionPointName>clk</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_DOMAIN</key>
- <value>1</value>
- </entry>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- <entry>
- <key>RESET_DOMAIN</key>
- <value>1</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>custom_instruction_master</key>
- <value>
- <connectionPointName>custom_instruction_master</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CUSTOM_INSTRUCTION_SLAVES</key>
- <value></value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>data_master</key>
- <value>
- <connectionPointName>data_master</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='ta2_unb2b_jesd204b.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>18</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>debug_mem_slave</key>
- <value>
- <connectionPointName>debug_mem_slave</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='debug_mem_slave' start='0x0' end='0x800' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>11</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>instruction_master</key>
- <value>
- <connectionPointName>instruction_master</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>18</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>irq</key>
- <value>
- <connectionPointName>irq</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>INTERRUPTS_USED</key>
- <value>7</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>custom_instruction_master</name>
- <type>nios_custom_instruction</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>dummy_ci_port</name>
- <role>readra</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>CIName</key>
- <value></value>
- </entry>
- <entry>
- <key>addressWidth</key>
- <value>8</value>
- </entry>
- <entry>
- <key>clockCycle</key>
- <value>0</value>
- </entry>
- <entry>
- <key>enabled</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxAddressWidth</key>
- <value>8</value>
- </entry>
- <entry>
- <key>opcodeExtension</key>
- <value>0</value>
- </entry>
- <entry>
- <key>sharedCombinationalAndMulticycle</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>data_master</name>
- <type>avalon</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>d_address</name>
- <role>address</role>
- <direction>Output</direction>
- <width>18</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>d_byteenable</name>
- <role>byteenable</role>
- <direction>Output</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>d_read</name>
- <role>read</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>d_readdata</name>
- <role>readdata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>d_waitrequest</name>
- <role>waitrequest</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>d_write</name>
- <role>write</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>d_writedata</name>
- <role>writedata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_debugaccess_to_roms</name>
- <role>debugaccess</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>debug.providesServices</key>
- <value>master</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>adaptsTo</key>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>1</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>SYMBOLS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>true</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>dBSBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>doStreamReads</key>
- <value>false</value>
- </entry>
- <entry>
- <key>doStreamWrites</key>
- <value>false</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isAsynchronous</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isReadable</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isWriteable</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxAddressWidth</key>
- <value>32</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>true</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>debug_mem_slave</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>debug_mem_slave_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>9</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_byteenable</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_debugaccess</name>
- <role>debugaccess</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.hideDevice</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>qsys.ui.connect</key>
- <value>instruction_master,data_master</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>2048</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>true</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>true</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>debug_reset_request</name>
- <type>reset</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>debug_reset_request</name>
- <role>reset</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedDirectReset</key>
- </entry>
- <entry>
- <key>associatedResetSinks</key>
- <value>none</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>instruction_master</name>
- <type>avalon</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>i_address</name>
- <role>address</role>
- <direction>Output</direction>
- <width>18</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>i_read</name>
- <role>read</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>i_readdata</name>
- <role>readdata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>i_waitrequest</name>
- <role>waitrequest</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>adaptsTo</key>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>1</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>SYMBOLS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>true</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>dBSBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>doStreamReads</key>
- <value>false</value>
- </entry>
- <entry>
- <key>doStreamWrites</key>
- <value>false</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isAsynchronous</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isReadable</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isWriteable</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>true</value>
- </entry>
- <entry>
- <key>maxAddressWidth</key>
- <value>32</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>irq</name>
- <type>interrupt</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>irq</name>
- <role>irq</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- <value>cpu_0.data_master</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>irqMap</key>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>INDIVIDUAL_REQUESTS</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>reset_req</name>
- <role>reset_req</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_cpu_0</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>board_cpu_0</fileSetName>
- <fileSetFixedName>board_cpu_0</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>board_cpu_0</fileSetName>
- <fileSetFixedName>board_cpu_0</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>board_cpu_0</fileSetName>
- <fileSetFixedName>board_cpu_0</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_cpu_0.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap>
- <entry>
- <key>debug.hostConnection</key>
- <value>type jtag id 70:34|110:135</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.BIG_ENDIAN</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.BREAK_ADDR</key>
- <value>0x00003820</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</key>
- <value></value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.CPU_FREQ</key>
- <value>100000000u</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.CPU_ID_SIZE</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.CPU_ID_VALUE</key>
- <value>0x00000000</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.CPU_IMPLEMENTATION</key>
- <value>"tiny"</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.DATA_ADDR_WIDTH</key>
- <value>18</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.DCACHE_LINE_SIZE</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.DCACHE_SIZE</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.EXCEPTION_ADDR</key>
- <value>0x00020020</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.FLASH_ACCELERATOR_LINES</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.FLUSHDA_SUPPORTED</key>
- <value></value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.HARDWARE_MULX_PRESENT</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.HAS_DEBUG_CORE</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.HAS_DEBUG_STUB</key>
- <value></value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION</key>
- <value></value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.HAS_JMPI_INSTRUCTION</key>
- <value></value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.ICACHE_LINE_SIZE</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.ICACHE_SIZE</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.INST_ADDR_WIDTH</key>
- <value>18</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.OCI_VERSION</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.RESET_ADDR</key>
- <value>0x00020000</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.DataCacheVictimBufImpl</key>
- <value>ram</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.HDLSimCachesCleared</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.breakOffset</key>
- <value>32</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.breakSlave</key>
- <value>cpu_0.debug_mem_slave</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.cpuArchitecture</key>
- <value>Nios II</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.exceptionOffset</key>
- <value>32</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.exceptionSlave</key>
- <value>onchip_memory2_0.s1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.resetOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.resetSlave</key>
- <value>onchip_memory2_0.s1</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.compatible</key>
- <value>altr,nios2-1.1</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.group</key>
- <value>cpu</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.name</key>
- <value>nios2</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.params.altr,exception-addr</key>
- <value>0x00020020</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.params.altr,implementation</key>
- <value>"tiny"</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.params.altr,reset-addr</key>
- <value>0x00020000</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.params.clock-frequency</key>
- <value>100000000u</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.params.dcache-line-size</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.params.dcache-size</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.params.icache-line-size</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.params.icache-size</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.vendor</key>
- <value>altr</value>
- </entry>
- </assignmentValueMap>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="jtag_uart_0"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>avalon_jtag_slave</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>av_chipselect</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>av_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>av_read_n</name>
- <role>read_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>av_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>av_write_n</name>
- <role>write_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>av_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>av_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>1</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>NATIVE</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>2</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>true</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- <cmsisInfo>
- <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
-<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
- <peripherals>
- <peripheral>
- <name>altera_avalon_jtag_uart</name><baseAddress>0x00000000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>8</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>DATA</name>
- <displayName>Data</displayName>
- <description>Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.</description>
- <addressOffset>0x0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>data</name>
- <description>The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>8</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>rvalid</name>
- <description>Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.</description>
- <bitOffset>0xf</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field><name>ravail</name>
- <description>The number of characters remaining in the read FIFO (after the current read).</description>
- <bitOffset>0x10</bitOffset>
- <bitWidth>16</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CONTROL</name>
- <displayName>Control</displayName>
- <description>Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>re</name>
- <description>Interrupt-enable bit for read interrupts.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>we</name>
- <description>Interrupt-enable bit for write interrupts</description>
- <bitOffset>0x1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>ri</name>
- <description>Indicates that the read interrupt is pending.</description>
- <bitOffset>0x8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field><name>wi</name>
- <description>Indicates that the write interrupt is pending.</description>
- <bitOffset>0x9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field><name>ac</name>
- <description>Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.</description>
- <bitOffset>0xa</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>wspace</name>
- <description>The number of spaces available in the write FIFO</description>
- <bitOffset>0x10</bitOffset>
- <bitWidth>16</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device> </cmsisSrcFileContents>
- <addressGroup></addressGroup>
- <cmsisVars/>
- </cmsisInfo>
- </interface>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>irq</name>
- <type>interrupt</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>av_irq</name>
- <role>irq</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- <value>jtag_uart_0.avalon_jtag_slave</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bridgedReceiverOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToReceiver</key>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>rst_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>altera_avalon_jtag_uart</className>
- <version>19.1</version>
- <displayName>JTAG UART Intel FPGA IP</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>avalonSpec</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>AVALON_SPEC</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>0</parameterDefaultValue>
- <parameterName>clkFreq</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>clk</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>avalon_jtag_slave</key>
- <value>
- <connectionPointName>avalon_jtag_slave</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='avalon_jtag_slave' start='0x0' end='0x8' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>3</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>clk</key>
- <value>
- <connectionPointName>clk</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>avalon_jtag_slave</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>av_chipselect</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>av_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>av_read_n</name>
- <role>read_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>av_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>av_write_n</name>
- <role>write_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>av_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>av_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>1</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>NATIVE</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>2</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>true</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- <cmsisInfo>
- <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
-<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
- <peripherals>
- <peripheral>
- <name>altera_avalon_jtag_uart</name><baseAddress>0x00000000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>8</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>DATA</name>
- <displayName>Data</displayName>
- <description>Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.</description>
- <addressOffset>0x0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>data</name>
- <description>The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>8</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>rvalid</name>
- <description>Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.</description>
- <bitOffset>0xf</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field><name>ravail</name>
- <description>The number of characters remaining in the read FIFO (after the current read).</description>
- <bitOffset>0x10</bitOffset>
- <bitWidth>16</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CONTROL</name>
- <displayName>Control</displayName>
- <description>Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>re</name>
- <description>Interrupt-enable bit for read interrupts.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>we</name>
- <description>Interrupt-enable bit for write interrupts</description>
- <bitOffset>0x1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>ri</name>
- <description>Indicates that the read interrupt is pending.</description>
- <bitOffset>0x8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field><name>wi</name>
- <description>Indicates that the write interrupt is pending.</description>
- <bitOffset>0x9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field><name>ac</name>
- <description>Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.</description>
- <bitOffset>0xa</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>wspace</name>
- <description>The number of spaces available in the write FIFO</description>
- <bitOffset>0x10</bitOffset>
- <bitWidth>16</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device> </cmsisSrcFileContents>
- <addressGroup></addressGroup>
- <cmsisVars/>
- </cmsisInfo>
- </interface>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>irq</name>
- <type>interrupt</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>av_irq</name>
- <role>irq</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- <value>jtag_uart_0.avalon_jtag_slave</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bridgedReceiverOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToReceiver</key>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>rst_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_jtag_uart_0</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>board_jtag_uart_0</fileSetName>
- <fileSetFixedName>board_jtag_uart_0</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>board_jtag_uart_0</fileSetName>
- <fileSetFixedName>board_jtag_uart_0</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>board_jtag_uart_0</fileSetName>
- <fileSetFixedName>board_jtag_uart_0</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_jtag_uart_0.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.CMacro.READ_DEPTH</key>
- <value>64</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.READ_THRESHOLD</key>
- <value>8</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.WRITE_DEPTH</key>
- <value>64</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.WRITE_THRESHOLD</key>
- <value>8</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.compatible</key>
- <value>altr,juart-1.0</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.group</key>
- <value>serial</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.name</key>
- <value>juart</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.vendor</key>
- <value>altr</value>
- </entry>
- </assignmentValueMap>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="kernel_clk_export"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>clk_out</name>
- <role>clk</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedDirectClock</key>
- <value>clk_in</value>
- </entry>
- <entry>
- <key>clockRate</key>
- <value>400000000</value>
- </entry>
- <entry>
- <key>clockRateKnown</key>
- <value>true</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>true</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_in</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>in_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>clk</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>400000000</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_in_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>reset</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_reset</name>
- <type>reset</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>reset_n_out</name>
- <role>reset_n</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedDirectReset</key>
- <value>clk_in_reset</value>
- </entry>
- <entry>
- <key>associatedResetSinks</key>
- <value>clk_in_reset</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>clock_source</className>
- <displayName>Clock Source</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>0</parameterDefaultValue>
- <parameterName>inputClockFrequency</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>clk_in</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>clk</key>
- <value>
- <connectionPointName>clk</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>400000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>clk_in</key>
- <value>
- <connectionPointName>clk_in</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>400000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>clk_out</name>
- <role>clk</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedDirectClock</key>
- <value>clk_in</value>
- </entry>
- <entry>
- <key>clockRate</key>
- <value>400000000</value>
- </entry>
- <entry>
- <key>clockRateKnown</key>
- <value>true</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>true</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_in</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>in_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>clk</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>400000000</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_in_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>reset</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk_reset</name>
- <type>reset</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>reset_n_out</name>
- <role>reset_n</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedDirectReset</key>
- <value>clk_in_reset</value>
- </entry>
- <entry>
- <key>associatedResetSinks</key>
- <value>clk_in_reset</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_kernel_clk</hdlLibraryName>
+ <hdlLibraryName>board_avs_eth_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_kernel_clk</fileSetName>
- <fileSetFixedName>board_kernel_clk</fileSetFixedName>
+ <fileSetName>board_avs_eth_0</fileSetName>
+ <fileSetFixedName>board_avs_eth_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_kernel_clk</fileSetName>
- <fileSetFixedName>board_kernel_clk</fileSetFixedName>
+ <fileSetName>board_avs_eth_0</fileSetName>
+ <fileSetFixedName>board_avs_eth_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_kernel_clk</fileSetName>
- <fileSetFixedName>board_kernel_clk</fileSetFixedName>
+ <fileSetName>board_avs_eth_0</fileSetName>
+ <fileSetFixedName>board_avs_eth_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_kernel_clk.ip</parameter>
+ <parameter name="logicalView">ip/board/board_avs_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="kernel_clk_gen"
+ name="board_onchip_memory"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -9326,12 +2786,12 @@
<boundary>
<interfaces>
<interface>
- <name>clk</name>
+ <name>clk1</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>clk_clk</name>
+ <name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
@@ -9340,18 +2800,13 @@
</port>
</ports>
<assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>clk</value>
- </entry>
- </assignmentValueMap>
+ <assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
- <value>50000000</value>
+ <value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
@@ -9364,60 +2819,74 @@
</parameters>
</interface>
<interface>
- <name>ctrl</name>
- <type>avalon</type>
+ <name>reset1</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>ctrl_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
+ <name>reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>ctrl_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>ctrl_readdatavalid</name>
- <role>readdatavalid</role>
- <direction>Output</direction>
+ <name>reset_req</name>
+ <role>reset_req</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk1</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>s1</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
<port>
- <name>ctrl_burstcount</name>
- <role>burstcount</role>
+ <name>address</name>
+ <role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>ctrl_writedata</name>
- <role>writedata</role>
+ <name>clken</name>
+ <role>clken</role>
<direction>Input</direction>
- <width>32</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>ctrl_address</name>
- <role>address</role>
+ <name>chipselect</name>
+ <role>chipselect</role>
<direction>Input</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>ctrl_write</name>
+ <name>write</name>
<role>write</role>
<direction>Input</direction>
<width>1</width>
@@ -9425,28 +2894,28 @@
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>ctrl_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>256</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>ctrl_byteenable</name>
- <role>byteenable</role>
+ <name>writedata</name>
+ <role>writedata</role>
<direction>Input</direction>
- <width>4</width>
+ <width>256</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>ctrl_debugaccess</name>
- <role>debugaccess</role>
+ <name>byteenable</name>
+ <role>byteenable</role>
<direction>Input</direction>
- <width>1</width>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -9457,7 +2926,7 @@
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
@@ -9485,7 +2954,7 @@
</entry>
<entry>
<key>addressUnits</key>
- <value>SYMBOLS</value>
+ <value>WORDS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
@@ -9493,11 +2962,11 @@
</entry>
<entry>
<key>associatedClock</key>
- <value>clk</value>
+ <value>clk1</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>reset</value>
+ <value>reset1</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
@@ -9524,7 +2993,7 @@
</entry>
<entry>
<key>explicitAddressSpan</key>
- <value>0</value>
+ <value>4096</value>
</entry>
<entry>
<key>holdTime</key>
@@ -9544,7 +3013,7 @@
</entry>
<entry>
<key>isMemoryDevice</key>
- <value>false</value>
+ <value>true</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
@@ -9556,7 +3025,7 @@
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
- <value>4</value>
+ <value>0</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
@@ -9584,7 +3053,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>readWaitStates</key>
@@ -9600,186 +3069,267 @@
</entry>
<entry>
<key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_clk</name>
- <type>clock</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_clk_clk</name>
- <role>clk</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedDirectClock</key>
- </entry>
- <entry>
- <key>clockRate</key>
- <value>400000000</value>
- </entry>
- <entry>
- <key>clockRateKnown</key>
- <value>true</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>true</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_clk2x</name>
- <type>clock</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_clk2x_clk</name>
- <role>clk</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
+ <value>false</value>
+ </entry>
<entry>
- <key>associatedDirectClock</key>
+ <key>setupTime</key>
+ <value>0</value>
</entry>
<entry>
- <key>clockRate</key>
- <value>800000000</value>
+ <key>timingUnits</key>
+ <value>Cycles</value>
</entry>
<entry>
- <key>clockRateKnown</key>
- <value>true</value>
+ <key>transparentBridge</key>
+ <value>false</value>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>true</value>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_pll_locked</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_pll_locked_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>writeLatency</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>writeWaitStates</key>
+ <value>0</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>writeWaitTime</key>
+ <value>0</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>altera_avalon_onchip_memory2</className>
+ <version>18.0</version>
+ <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>autoInitializationFileName</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfotype>UNIQUE_ID</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>NONE</parameterDefaultValue>
+ <parameterName>deviceFamily</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfotype>DEVICE_FAMILY</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>NONE</parameterDefaultValue>
+ <parameterName>deviceFeatures</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfotype>DEVICE_FEATURES</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>s1</key>
+ <value>
+ <connectionPointName>s1</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='s1' start='0x0' end='0x1000' datawidth='256' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>12</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>256</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>board_onchip_memory</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>board_onchip_memory</fileSetName>
+ <fileSetFixedName>board_onchip_memory</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>board_onchip_memory</fileSetName>
+ <fileSetFixedName>board_onchip_memory</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>board_onchip_memory</fileSetName>
+ <fileSetFixedName>board_onchip_memory</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/board/board_onchip_memory.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.CONTENTS_INFO</key>
+ <value>""</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.DUAL_PORT</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</key>
+ <value>AUTO</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.INIT_CONTENTS_FILE</key>
+ <value>board_onchip_memory_board_onchip_memory</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.INIT_MEM_CONTENT</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.INSTANCE_ID</key>
+ <value>NONE</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.RAM_BLOCK_TYPE</key>
+ <value>AUTO</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.READ_DURING_WRITE_MODE</key>
+ <value>DONT_CARE</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.SINGLE_CLOCK_OP</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.SIZE_MULTIPLE</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.SIZE_VALUE</key>
+ <value>4096</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.WRITABLE</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</key>
+ <value>SIM_DIR</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.memoryInfo.GENERATE_DAT_SYM</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.memoryInfo.GENERATE_HEX</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.memoryInfo.HAS_BYTE_LANE</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.memoryInfo.HEX_INSTALL_DIR</key>
+ <value>QPF_DIR</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.memoryInfo.MEM_INIT_FILENAME</key>
+ <value>board_onchip_memory_board_onchip_memory</value>
+ </entry>
+ <entry>
+ <key>postgeneration.simulation.init_file.param_name</key>
+ <value>INIT_FILE</value>
+ </entry>
+ <entry>
+ <key>postgeneration.simulation.init_file.type</key>
+ <value>MEM_INIT</value>
+ </entry>
+ </assignmentValueMap>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="clk_0"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
<interface>
- <name>kernel_pll_refclk</name>
+ <name>clk</name>
<type>clock</type>
- <isStart>false</isStart>
+ <isStart>true</isStart>
<ports>
<port>
- <name>kernel_pll_refclk_clk</name>
+ <name>clk_out</name>
<role>clk</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>ui.blockdiagram.direction</key>
- <value>input</value>
- </entry>
- </assignmentValueMap>
+ <assignments>
+ <assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
+ <entry>
+ <key>associatedDirectClock</key>
+ <value>clk_in</value>
+ </entry>
<entry>
<key>clockRate</key>
<value>100000000</value>
</entry>
+ <entry>
+ <key>clockRateKnown</key>
+ <value>true</value>
+ </entry>
<entry>
<key>externallyDriven</key>
- <value>false</value>
+ <value>true</value>
</entry>
<entry>
<key>ptfSchematicName</key>
@@ -9788,13 +3338,13 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
- <type>reset</type>
+ <name>clk_in</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>reset_reset_n</name>
- <role>reset_n</role>
+ <name>in_clk</name>
+ <role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -9805,637 +3355,177 @@
<assignmentValueMap>
<entry>
<key>qsys.ui.export_name</key>
- <value>reset</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
<value>clk</value>
</entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>acl_kernel_clk_a10</className>
- <version>16.1</version>
- <displayName>OpenCL A10 Kernel Clock Generator</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>AUTO_DEVICE</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>AUTO_DEVICE_FAMILY</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE_FAMILY</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue></parameterDefaultValue>
- <parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>ctrl</key>
- <value>
- <connectionPointName>ctrl</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='ctrl' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>12</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>kernel_clk</key>
- <value>
- <connectionPointName>kernel_clk</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>400000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>kernel_clk2x</key>
- <value>
- <connectionPointName>kernel_clk2x</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>800000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>clk</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>50000000</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>ctrl</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>ctrl_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>ctrl_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>ctrl_readdatavalid</name>
- <role>readdatavalid</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>ctrl_burstcount</name>
- <role>burstcount</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>ctrl_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>ctrl_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>12</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>ctrl_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>ctrl_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>ctrl_byteenable</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>ctrl_debugaccess</name>
- <role>debugaccess</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>SYMBOLS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>4</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_clk</name>
- <type>clock</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_clk_clk</name>
- <role>clk</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedDirectClock</key>
- </entry>
- <entry>
- <key>clockRate</key>
- <value>400000000</value>
- </entry>
- <entry>
- <key>clockRateKnown</key>
- <value>true</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>true</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_clk2x</name>
- <type>clock</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_clk2x_clk</name>
- <role>clk</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedDirectClock</key>
- </entry>
- <entry>
- <key>clockRate</key>
- <value>800000000</value>
- </entry>
- <entry>
- <key>clockRateKnown</key>
- <value>true</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>true</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_pll_locked</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_pll_locked_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_pll_refclk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_pll_refclk_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>ui.blockdiagram.direction</key>
- <value>input</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>100000000</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>reset</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>100000000</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk_in_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>qsys.ui.export_name</key>
+ <value>reset</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk_reset</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_n_out</name>
+ <role>reset_n</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ <value>clk_in_reset</value>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>clk_in_reset</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>clock_source</className>
+ <displayName>Clock Source</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>0</parameterDefaultValue>
+ <parameterName>inputClockFrequency</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>clk_in</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>clk</key>
+ <value>
+ <connectionPointName>clk</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>clk_in</key>
+ <value>
+ <connectionPointName>clk_in</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>0</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_kernel_clk_gen</hdlLibraryName>
+ <hdlLibraryName>board_clk_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_kernel_clk_gen</fileSetName>
- <fileSetFixedName>board_kernel_clk_gen</fileSetFixedName>
+ <fileSetName>board_clk_0</fileSetName>
+ <fileSetFixedName>board_clk_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_kernel_clk_gen</fileSetName>
- <fileSetFixedName>board_kernel_clk_gen</fileSetFixedName>
+ <fileSetName>board_clk_0</fileSetName>
+ <fileSetFixedName>board_clk_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_kernel_clk_gen</fileSetName>
- <fileSetFixedName>board_kernel_clk_gen</fileSetFixedName>
+ <fileSetName>board_clk_0</fileSetName>
+ <fileSetFixedName>board_clk_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_kernel_clk_gen.ip</parameter>
+ <parameter name="logicalView">ip/board/board_clk_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="kernel_interface"
+ name="cpu_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -10443,170 +3533,389 @@
<boundary>
<interfaces>
<interface>
- <name>acl_bsp_memorg_host0x018</name>
- <type>conduit</type>
+ <name>clk</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>acl_bsp_memorg_host0x018_mode</name>
- <role>mode</role>
+ <name>clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>custom_instruction_master</name>
+ <type>nios_custom_instruction</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>dummy_ci_port</name>
+ <role>readra</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>CIName</key>
+ <value></value>
+ </entry>
+ <entry>
+ <key>addressWidth</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>clockCycle</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>enabled</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maxAddressWidth</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>opcodeExtension</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>sharedCombinationalAndMulticycle</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>data_master</name>
+ <type>avalon</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>d_address</name>
+ <role>address</role>
+ <direction>Output</direction>
+ <width>18</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>d_byteenable</name>
+ <role>byteenable</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>d_read</name>
+ <role>read</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>d_readdata</name>
+ <role>readdata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>d_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>d_write</name>
+ <role>write</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>d_writedata</name>
+ <role>writedata</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
+ <port>
+ <name>debug_mem_slave_debugaccess_to_roms</name>
+ <role>debugaccess</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
</ports>
<assignments>
- <assignmentValueMap/>
+ <assignmentValueMap>
+ <entry>
+ <key>debug.providesServices</key>
+ <value>master</value>
+ </entry>
+ </assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
+ <entry>
+ <key>adaptsTo</key>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>SYMBOLS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
<entry>
<key>associatedClock</key>
+ <value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
+ <value>reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>dBSBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>doStreamReads</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>doStreamWrites</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isAsynchronous</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isReadable</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isWriteable</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maxAddressWidth</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
<entry>
- <key>qsys.ui.export_name</key>
- <value>clk</value>
+ <key>readLatency</key>
+ <value>0</value>
</entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>100000000</value>
+ <key>readWaitTime</key>
+ <value>1</value>
</entry>
<entry>
- <key>externallyDriven</key>
+ <key>registerIncomingSignals</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>ctrl</name>
+ <name>debug_mem_slave</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
- <name>ctrl_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
+ <name>debug_mem_slave_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>9</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>ctrl_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>debug_mem_slave_byteenable</name>
+ <role>byteenable</role>
+ <direction>Input</direction>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>ctrl_readdatavalid</name>
- <role>readdatavalid</role>
- <direction>Output</direction>
+ <name>debug_mem_slave_debugaccess</name>
+ <role>debugaccess</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>ctrl_burstcount</name>
- <role>burstcount</role>
+ <name>debug_mem_slave_read</name>
+ <role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>ctrl_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
+ <name>debug_mem_slave_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>ctrl_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>14</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>ctrl_write</name>
- <role>write</role>
- <direction>Input</direction>
+ <name>debug_mem_slave_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>ctrl_read</name>
- <role>read</role>
+ <name>debug_mem_slave_write</name>
+ <role>write</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>ctrl_byteenable</name>
- <role>byteenable</role>
+ <name>debug_mem_slave_writedata</name>
+ <role>writedata</role>
<direction>Input</direction>
- <width>4</width>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
- <port>
- <name>ctrl_debugaccess</name>
- <role>debugaccess</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
</ports>
<assignments>
<assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.hideDevice</key>
+ <value>1</value>
+ </entry>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
@@ -10616,6 +3925,10 @@
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
+ <entry>
+ <key>qsys.ui.connect</key>
+ <value>instruction_master,data_master</value>
+ </entry>
</assignmentValueMap>
</assignments>
<parameters>
@@ -10630,11 +3943,11 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16384</value>
+ <value>2048</value>
</entry>
<entry>
<key>addressUnits</key>
- <value>SYMBOLS</value>
+ <value>WORDS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
@@ -10693,7 +4006,7 @@
</entry>
<entry>
<key>isMemoryDevice</key>
- <value>false</value>
+ <value>true</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
@@ -10705,7 +4018,7 @@
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
@@ -10737,15 +4050,15 @@
</entry>
<entry>
<key>readWaitStates</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
- <value>false</value>
+ <value>true</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
@@ -10787,14 +4100,14 @@
</parameters>
</interface>
<interface>
- <name>kernel_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
+ <name>debug_reset_request</name>
+ <type>reset</type>
+ <isStart>true</isStart>
<ports>
<port>
- <name>kernel_clk_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>debug_reset_request</name>
+ <role>reset</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -10806,82 +4119,38 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
+ <value>clk</value>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedDirectReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>associatedResetSinks</key>
+ <value>none</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>kernel_cra</name>
+ <name>instruction_master</name>
<type>avalon</type>
<isStart>true</isStart>
<ports>
<port>
- <name>kernel_cra_waitrequest</name>
- <role>waitrequest</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_cra_readdata</name>
- <role>readdata</role>
- <direction>Input</direction>
- <width>64</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_cra_readdatavalid</name>
- <role>readdatavalid</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_cra_burstcount</name>
- <role>burstcount</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_cra_writedata</name>
- <role>writedata</role>
- <direction>Output</direction>
- <width>64</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_cra_address</name>
+ <name>i_address</name>
<role>address</role>
<direction>Output</direction>
- <width>30</width>
+ <width>18</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>kernel_cra_write</name>
- <role>write</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_cra_read</name>
+ <name>i_read</name>
<role>read</role>
<direction>Output</direction>
<width>1</width>
@@ -10889,17 +4158,17 @@
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>kernel_cra_byteenable</name>
- <role>byteenable</role>
- <direction>Output</direction>
- <width>8</width>
+ <name>i_readdata</name>
+ <role>readdata</role>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>kernel_cra_debugaccess</name>
- <role>debugaccess</role>
- <direction>Output</direction>
+ <name>i_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -10915,7 +4184,7 @@
</entry>
<entry>
<key>addressGroup</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -10923,11 +4192,11 @@
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
- <value>false</value>
+ <value>true</value>
</entry>
<entry>
<key>associatedClock</key>
- <value>kernel_clk</value>
+ <value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
@@ -10987,7 +4256,7 @@
</entry>
<entry>
<key>linewrapBursts</key>
- <value>false</value>
+ <value>true</value>
</entry>
<entry>
<key>maxAddressWidth</key>
@@ -11018,207 +4287,48 @@
<value>0</value>
</entry>
<entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_irq_from_kernel</name>
- <type>interrupt</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_irq_from_kernel_irq</name>
- <role>irq</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>irqMap</key>
- <value><map><mapping port='0' sender='sender0_irq' /></map></value>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>INDIVIDUAL_REQUESTS</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_irq_to_host</name>
- <type>interrupt</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_irq_to_host_irq</name>
- <role>irq</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bridgedReceiverOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToReceiver</key>
- <value>kernel_interface.kernel_irq_from_kernel</value>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_reset</name>
- <type>reset</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_reset_reset_n</name>
- <role>reset_n</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
+ <key>readWaitTime</key>
+ <value>1</value>
</entry>
<entry>
- <key>associatedDirectReset</key>
- <value>reset</value>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
</entry>
<entry>
- <key>associatedResetSinks</key>
- <value>reset,reset,sw_reset_in</value>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>setupTime</key>
+ <value>0</value>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
<entry>
- <key>qsys.ui.export_name</key>
- <value>reset</value>
+ <key>timingUnits</key>
+ <value>Cycles</value>
</entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
<entry>
- <key>associatedClock</key>
- <value>clk</value>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>writeWaitTime</key>
+ <value>0</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>sw_reset_export</name>
- <type>reset</type>
+ <name>irq</name>
+ <type>interrupt</type>
<isStart>true</isStart>
<ports>
<port>
- <name>sw_reset_export_reset_n</name>
- <role>reset_n</role>
- <direction>Output</direction>
- <width>1</width>
+ <name>irq</name>
+ <role>irq</role>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -11226,33 +4336,44 @@
</assignments>
<parameters>
<parameterValueMap>
+ <entry>
+ <key>associatedAddressablePoint</key>
+ <value>cpu_0.data_master</value>
+ </entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
- <key>associatedDirectReset</key>
+ <key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
- <key>associatedResetSinks</key>
- <value>reset,sw_reset_in</value>
+ <key>irqMap</key>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>irqScheme</key>
+ <value>INDIVIDUAL_REQUESTS</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>sw_reset_in</name>
+ <name>reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>sw_reset_in_reset</name>
- <role>reset</role>
+ <name>reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>reset_req</name>
+ <role>reset_req</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -11278,12 +4399,26 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>kernel_interface</className>
- <version>15.1</version>
- <displayName>OpenCL Kernel Interface</displayName>
+ <className>altera_nios2_gen2</className>
+ <version>18.0</version>
+ <displayName>Nios II Processor</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_CLK_CLOCK_DOMAIN</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>clk</systemInfoArgs>
+ <systemInfotype>CLOCK_DOMAIN</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_CLK_RESET_DOMAIN</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>clk</systemInfoArgs>
+ <systemInfotype>RESET_DOMAIN</systemInfotype>
+ </descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>AUTO_DEVICE</parameterName>
@@ -11292,913 +4427,588 @@
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
- <parameterName>AUTO_DEVICE_FAMILY</parameterName>
+ <parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>50000000</parameterDefaultValue>
+ <parameterName>clockFrequency</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>clk</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>customInstSlavesSystemInfo</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>custom_instruction_master</systemInfoArgs>
+ <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>customInstSlavesSystemInfo_nios_a</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>custom_instruction_master_a</systemInfoArgs>
+ <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>customInstSlavesSystemInfo_nios_b</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>custom_instruction_master_b</systemInfoArgs>
+ <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>customInstSlavesSystemInfo_nios_c</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>custom_instruction_master_c</systemInfoArgs>
+ <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>1</parameterDefaultValue>
+ <parameterName>dataAddrWidth</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>data_master</systemInfoArgs>
+ <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>1</parameterDefaultValue>
+ <parameterName>dataMasterHighPerformanceAddrWidth</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>data_master_high_performance</systemInfoArgs>
+ <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>dataMasterHighPerformanceMapParam</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>data_master_high_performance</systemInfoArgs>
+ <systemInfotype>ADDRESS_MAP</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>dataSlaveMapParam</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>data_master</systemInfoArgs>
+ <systemInfotype>ADDRESS_MAP</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>STRATIXIV</parameterDefaultValue>
+ <parameterName>deviceFamilyName</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_FAMILY</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
- <parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName>
+ <parameterName>deviceFeaturesSystemInfo</parameterName>
<parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
+ <systemInfotype>DEVICE_FEATURES</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>1</parameterDefaultValue>
+ <parameterName>faAddrWidth</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>flash_instruction_master</systemInfoArgs>
+ <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>faSlaveMapParam</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>flash_instruction_master</systemInfoArgs>
+ <systemInfotype>ADDRESS_MAP</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>1</parameterDefaultValue>
+ <parameterName>instAddrWidth</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>instruction_master</systemInfoArgs>
+ <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>instSlaveMapParam</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>instruction_master</systemInfoArgs>
+ <systemInfotype>ADDRESS_MAP</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>1</parameterDefaultValue>
+ <parameterName>instructionMasterHighPerformanceAddrWidth</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>instruction_master_high_performance</systemInfoArgs>
+ <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>instructionMasterHighPerformanceMapParam</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>instruction_master_high_performance</systemInfoArgs>
+ <systemInfotype>ADDRESS_MAP</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>0</parameterDefaultValue>
+ <parameterName>internalIrqMaskSystemInfo</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>irq</systemInfoArgs>
+ <systemInfotype>INTERRUPTS_USED</systemInfotype>
</descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>ctrl</key>
- <value>
- <connectionPointName>ctrl</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='ctrl' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>14</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>acl_bsp_memorg_host0x018</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>acl_bsp_memorg_host0x018_mode</name>
- <role>mode</role>
- <direction>Output</direction>
- <width>2</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>clk</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>100000000</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>ctrl</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>ctrl_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>ctrl_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>ctrl_readdatavalid</name>
- <role>readdatavalid</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>ctrl_burstcount</name>
- <role>burstcount</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>ctrl_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>ctrl_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>14</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>ctrl_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>ctrl_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>ctrl_byteenable</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>ctrl_debugaccess</name>
- <role>debugaccess</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>16384</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>SYMBOLS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>1</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_clk_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_cra</name>
- <type>avalon</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_cra_waitrequest</name>
- <role>waitrequest</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_cra_readdata</name>
- <role>readdata</role>
- <direction>Input</direction>
- <width>64</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_cra_readdatavalid</name>
- <role>readdatavalid</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_cra_burstcount</name>
- <role>burstcount</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_cra_writedata</name>
- <role>writedata</role>
- <direction>Output</direction>
- <width>64</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_cra_address</name>
- <role>address</role>
- <direction>Output</direction>
- <width>30</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_cra_write</name>
- <role>write</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_cra_read</name>
- <role>read</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_cra_byteenable</name>
- <role>byteenable</role>
- <direction>Output</direction>
- <width>8</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_cra_debugaccess</name>
- <role>debugaccess</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>adaptsTo</key>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>SYMBOLS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>dBSBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>doStreamReads</key>
- <value>false</value>
- </entry>
- <entry>
- <key>doStreamWrites</key>
- <value>false</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isAsynchronous</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isReadable</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isWriteable</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxAddressWidth</key>
- <value>32</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_irq_from_kernel</name>
- <type>interrupt</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_irq_from_kernel_irq</name>
- <role>irq</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>irqMap</key>
- <value><map><mapping port='0' sender='sender0_irq' /></map></value>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>INDIVIDUAL_REQUESTS</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_irq_to_host</name>
- <type>interrupt</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_irq_to_host_irq</name>
- <role>irq</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bridgedReceiverOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToReceiver</key>
- <value>kernel_interface.kernel_irq_from_kernel</value>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_reset</name>
- <type>reset</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_reset_reset_n</name>
- <role>reset_n</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedDirectReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>associatedResetSinks</key>
- <value>reset,reset,sw_reset_in</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>reset</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>sw_reset_export</name>
- <type>reset</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>sw_reset_export_reset_n</name>
- <role>reset_n</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedDirectReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>associatedResetSinks</key>
- <value>reset,sw_reset_in</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>sw_reset_in</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>sw_reset_in_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ <descriptor>
+ <parameterDefaultValue>1</parameterDefaultValue>
+ <parameterName>tightlyCoupledDataMaster0AddrWidth</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>tightly_coupled_data_master_0</systemInfoArgs>
+ <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>tightlyCoupledDataMaster0MapParam</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>tightly_coupled_data_master_0</systemInfoArgs>
+ <systemInfotype>ADDRESS_MAP</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>1</parameterDefaultValue>
+ <parameterName>tightlyCoupledDataMaster1AddrWidth</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>tightly_coupled_data_master_1</systemInfoArgs>
+ <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>tightlyCoupledDataMaster1MapParam</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>tightly_coupled_data_master_1</systemInfoArgs>
+ <systemInfotype>ADDRESS_MAP</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>1</parameterDefaultValue>
+ <parameterName>tightlyCoupledDataMaster2AddrWidth</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>tightly_coupled_data_master_2</systemInfoArgs>
+ <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>tightlyCoupledDataMaster2MapParam</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>tightly_coupled_data_master_2</systemInfoArgs>
+ <systemInfotype>ADDRESS_MAP</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>1</parameterDefaultValue>
+ <parameterName>tightlyCoupledDataMaster3AddrWidth</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>tightly_coupled_data_master_3</systemInfoArgs>
+ <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>tightlyCoupledDataMaster3MapParam</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>tightly_coupled_data_master_3</systemInfoArgs>
+ <systemInfotype>ADDRESS_MAP</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>1</parameterDefaultValue>
+ <parameterName>tightlyCoupledInstructionMaster0AddrWidth</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>tightly_coupled_instruction_master_0</systemInfoArgs>
+ <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>tightlyCoupledInstructionMaster0MapParam</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>tightly_coupled_instruction_master_0</systemInfoArgs>
+ <systemInfotype>ADDRESS_MAP</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>1</parameterDefaultValue>
+ <parameterName>tightlyCoupledInstructionMaster1AddrWidth</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>tightly_coupled_instruction_master_1</systemInfoArgs>
+ <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>tightlyCoupledInstructionMaster1MapParam</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>tightly_coupled_instruction_master_1</systemInfoArgs>
+ <systemInfotype>ADDRESS_MAP</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>1</parameterDefaultValue>
+ <parameterName>tightlyCoupledInstructionMaster2AddrWidth</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>tightly_coupled_instruction_master_2</systemInfoArgs>
+ <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>tightlyCoupledInstructionMaster2MapParam</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>tightly_coupled_instruction_master_2</systemInfoArgs>
+ <systemInfotype>ADDRESS_MAP</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>1</parameterDefaultValue>
+ <parameterName>tightlyCoupledInstructionMaster3AddrWidth</parameterName>
+ <parameterType>java.lang.Integer</parameterType>
+ <systemInfoArgs>tightly_coupled_instruction_master_3</systemInfoArgs>
+ <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>tightlyCoupledInstructionMaster3MapParam</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfoArgs>tightly_coupled_instruction_master_3</systemInfoArgs>
+ <systemInfotype>ADDRESS_MAP</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>clk</key>
+ <value>
+ <connectionPointName>clk</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_DOMAIN</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ <entry>
+ <key>RESET_DOMAIN</key>
+ <value>1</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>custom_instruction_master</key>
+ <value>
+ <connectionPointName>custom_instruction_master</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CUSTOM_INSTRUCTION_SLAVES</key>
+ <value></value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>data_master</key>
+ <value>
+ <connectionPointName>data_master</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='reg_ta2_unb2b_jesd204b.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>18</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>debug_mem_slave</key>
+ <value>
+ <connectionPointName>debug_mem_slave</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='debug_mem_slave' start='0x0' end='0x800' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>11</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>instruction_master</key>
+ <value>
+ <connectionPointName>instruction_master</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>18</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>irq</key>
+ <value>
+ <connectionPointName>irq</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>INTERRUPTS_USED</key>
+ <value>7</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_kernel_interface</hdlLibraryName>
+ <hdlLibraryName>board_cpu_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_kernel_interface</fileSetName>
- <fileSetFixedName>board_kernel_interface</fileSetFixedName>
+ <fileSetName>board_cpu_0</fileSetName>
+ <fileSetFixedName>board_cpu_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_kernel_interface</fileSetName>
- <fileSetFixedName>board_kernel_interface</fileSetFixedName>
+ <fileSetName>board_cpu_0</fileSetName>
+ <fileSetFixedName>board_cpu_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_kernel_interface</fileSetName>
- <fileSetFixedName>board_kernel_interface</fileSetFixedName>
+ <fileSetName>board_cpu_0</fileSetName>
+ <fileSetFixedName>board_cpu_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_kernel_interface.ip</parameter>
+ <parameter name="logicalView">ip/board/board_cpu_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
+ <assignmentValueMap>
+ <entry>
+ <key>debug.hostConnection</key>
+ <value>type jtag id 70:34|110:135</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.BIG_ENDIAN</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.BREAK_ADDR</key>
+ <value>0x00003820</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</key>
+ <value></value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.CPU_FREQ</key>
+ <value>100000000u</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.CPU_ID_SIZE</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.CPU_ID_VALUE</key>
+ <value>0x00000000</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.CPU_IMPLEMENTATION</key>
+ <value>"tiny"</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.DATA_ADDR_WIDTH</key>
+ <value>18</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.DCACHE_LINE_SIZE</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.DCACHE_SIZE</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.EXCEPTION_ADDR</key>
+ <value>0x00020020</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.FLASH_ACCELERATOR_LINES</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.FLUSHDA_SUPPORTED</key>
+ <value></value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.HARDWARE_MULX_PRESENT</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.HAS_DEBUG_CORE</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.HAS_DEBUG_STUB</key>
+ <value></value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION</key>
+ <value></value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.HAS_JMPI_INSTRUCTION</key>
+ <value></value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.ICACHE_LINE_SIZE</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.ICACHE_SIZE</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.INST_ADDR_WIDTH</key>
+ <value>18</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.OCI_VERSION</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.RESET_ADDR</key>
+ <value>0x00020000</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.DataCacheVictimBufImpl</key>
+ <value>ram</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.HDLSimCachesCleared</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.breakOffset</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.breakSlave</key>
+ <value>cpu_0.debug_mem_slave</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.cpuArchitecture</key>
+ <value>Nios II</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.exceptionOffset</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.exceptionSlave</key>
+ <value>onchip_memory2_0.s1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.resetOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.resetSlave</key>
+ <value>onchip_memory2_0.s1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.compatible</key>
+ <value>altr,nios2-1.1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.group</key>
+ <value>cpu</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.name</key>
+ <value>nios2</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.params.altr,exception-addr</key>
+ <value>0x00020020</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.params.altr,implementation</key>
+ <value>"tiny"</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.params.altr,reset-addr</key>
+ <value>0x00020000</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.params.clock-frequency</key>
+ <value>100000000u</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.params.dcache-line-size</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.params.dcache-size</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.params.icache-line-size</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.params.icache-size</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.vendor</key>
+ <value>altr</value>
+ </entry>
+ </assignmentValueMap>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="onchip_memory2_0"
+ name="jtag_uart_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -12206,115 +5016,36 @@
<boundary>
<interfaces>
<interface>
- <name>clk1</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset1</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>reset_req</name>
- <role>reset_req</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>s1</name>
+ <name>avalon_jtag_slave</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
- <name>address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>15</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>clken</name>
- <role>clken</role>
+ <name>av_chipselect</name>
+ <role>chipselect</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>chipselect</name>
- <role>chipselect</role>
+ <name>av_address</name>
+ <role>address</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>write</name>
- <role>write</role>
+ <name>av_read_n</name>
+ <role>read_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>readdata</name>
+ <name>av_readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
@@ -12322,7 +5053,15 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>writedata</name>
+ <name>av_write_n</name>
+ <role>write_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>av_writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
@@ -12330,12 +5069,12 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>byteenable</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>4</width>
+ <name>av_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -12346,7 +5085,7 @@
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
@@ -12354,7 +5093,7 @@
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
+ <value>1</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -12362,7 +5101,7 @@
<parameterValueMap>
<entry>
<key>addressAlignment</key>
- <value>DYNAMIC</value>
+ <value>NATIVE</value>
</entry>
<entry>
<key>addressGroup</key>
@@ -12370,7 +5109,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>131072</value>
+ <value>2</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -12382,11 +5121,11 @@
</entry>
<entry>
<key>associatedClock</key>
- <value>clk1</value>
+ <value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>reset1</value>
+ <value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
@@ -12413,7 +5152,7 @@
</entry>
<entry>
<key>explicitAddressSpan</key>
- <value>131072</value>
+ <value>0</value>
</entry>
<entry>
<key>holdTime</key>
@@ -12433,7 +5172,7 @@
</entry>
<entry>
<key>isMemoryDevice</key>
- <value>true</value>
+ <value>false</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
@@ -12469,19 +5208,19 @@
</entry>
<entry>
<key>printableDevice</key>
- <value>false</value>
+ <value>true</value>
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
@@ -12516,12 +5255,217 @@
<value>0</value>
</entry>
<entry>
- <key>writeWaitStates</key>
- <value>0</value>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ <cmsisInfo>
+ <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
+ <peripherals>
+ <peripheral>
+ <name>altera_avalon_jtag_uart</name><baseAddress>0x00000000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>8</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>DATA</name>
+ <displayName>Data</displayName>
+ <description>Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.</description>
+ <addressOffset>0x0</addressOffset>
+ <size>32</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <resetMask>0xffffffff</resetMask>
+ <fields>
+ <field><name>data</name>
+ <description>The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.</description>
+ <bitOffset>0x0</bitOffset>
+ <bitWidth>8</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field><name>rvalid</name>
+ <description>Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.</description>
+ <bitOffset>0xf</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field><name>ravail</name>
+ <description>The number of characters remaining in the read FIFO (after the current read).</description>
+ <bitOffset>0x10</bitOffset>
+ <bitWidth>16</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CONTROL</name>
+ <displayName>Control</displayName>
+ <description>Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.</description>
+ <addressOffset>0x4</addressOffset>
+ <size>32</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <resetMask>0xffffffff</resetMask>
+ <fields>
+ <field><name>re</name>
+ <description>Interrupt-enable bit for read interrupts.</description>
+ <bitOffset>0x0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field><name>we</name>
+ <description>Interrupt-enable bit for write interrupts</description>
+ <bitOffset>0x1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field><name>ri</name>
+ <description>Indicates that the read interrupt is pending.</description>
+ <bitOffset>0x8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field><name>wi</name>
+ <description>Indicates that the write interrupt is pending.</description>
+ <bitOffset>0x9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field><name>ac</name>
+ <description>Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.</description>
+ <bitOffset>0xa</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field><name>wspace</name>
+ <description>The number of spaces available in the write FIFO</description>
+ <bitOffset>0x10</bitOffset>
+ <bitWidth>16</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ </peripherals>
+</device> </cmsisSrcFileContents>
+ <addressGroup></addressGroup>
+ <cmsisVars/>
+ </cmsisInfo>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>irq</name>
+ <type>interrupt</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>av_irq</name>
+ <role>irq</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedAddressablePoint</key>
+ <value>jtag_uart_0.avalon_jtag_slave</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>reset</value>
+ </entry>
+ <entry>
+ <key>bridgedReceiverOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToReceiver</key>
+ </entry>
+ <entry>
+ <key>irqScheme</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rst_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
</entry>
<entry>
- <key>writeWaitTime</key>
- <value>0</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -12529,46 +5473,41 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>altera_avalon_onchip_memory2</className>
- <version>19.1</version>
- <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName>
+ <className>altera_avalon_jtag_uart</className>
+ <version>18.0</version>
+ <displayName>JTAG UART Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
- <parameterName>autoInitializationFileName</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>UNIQUE_ID</systemInfotype>
- </descriptor>
- <descriptor>
- <parameterDefaultValue>NONE</parameterDefaultValue>
- <parameterName>deviceFamily</parameterName>
+ <parameterName>avalonSpec</parameterName>
<parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE_FAMILY</systemInfotype>
+ <systemInfotype>AVALON_SPEC</systemInfotype>
</descriptor>
<descriptor>
- <parameterDefaultValue>NONE</parameterDefaultValue>
- <parameterName>deviceFeatures</parameterName>
- <parameterType>java.lang.String</parameterType>
- <systemInfotype>DEVICE_FEATURES</systemInfotype>
+ <parameterDefaultValue>0</parameterDefaultValue>
+ <parameterName>clkFreq</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>clk</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
<entry>
- <key>s1</key>
+ <key>avalon_jtag_slave</key>
<value>
- <connectionPointName>s1</connectionPointName>
+ <connectionPointName>avalon_jtag_slave</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='s1' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='avalon_jtag_slave' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>17</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -12578,463 +5517,87 @@
<consumedSystemInfos/>
</value>
</entry>
+ <entry>
+ <key>clk</key>
+ <value>
+ <connectionPointName>clk</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>clk1</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset1</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>reset_req</name>
- <role>reset_req</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>s1</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>15</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>clken</name>
- <role>clken</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>chipselect</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>byteenable</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>131072</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk1</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset1</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>131072</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>true</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_onchip_memory2_0</hdlLibraryName>
+ <hdlLibraryName>board_jtag_uart_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_onchip_memory2_0</fileSetName>
- <fileSetFixedName>board_onchip_memory2_0</fileSetFixedName>
+ <fileSetName>board_jtag_uart_0</fileSetName>
+ <fileSetFixedName>board_jtag_uart_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_onchip_memory2_0</fileSetName>
- <fileSetFixedName>board_onchip_memory2_0</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>board_onchip_memory2_0</fileSetName>
- <fileSetFixedName>board_onchip_memory2_0</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_onchip_memory2_0.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.CONTENTS_INFO</key>
- <value>""</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.DUAL_PORT</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</key>
- <value>AUTO</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.INIT_CONTENTS_FILE</key>
- <value>onchip_memory2_0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.INIT_MEM_CONTENT</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.INSTANCE_ID</key>
- <value>NONE</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.RAM_BLOCK_TYPE</key>
- <value>AUTO</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.READ_DURING_WRITE_MODE</key>
- <value>DONT_CARE</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.SINGLE_CLOCK_OP</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.SIZE_MULTIPLE</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.SIZE_VALUE</key>
- <value>131072</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.WRITABLE</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</key>
- <value>SIM_DIR</value>
- </entry>
+ <fileSetName>board_jtag_uart_0</fileSetName>
+ <fileSetFixedName>board_jtag_uart_0</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>board_jtag_uart_0</fileSetName>
+ <fileSetFixedName>board_jtag_uart_0</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/board/board_jtag_uart_0.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap>
<entry>
- <key>embeddedsw.memoryInfo.GENERATE_DAT_SYM</key>
- <value>1</value>
+ <key>embeddedsw.CMacro.READ_DEPTH</key>
+ <value>64</value>
</entry>
<entry>
- <key>embeddedsw.memoryInfo.GENERATE_HEX</key>
- <value>1</value>
+ <key>embeddedsw.CMacro.READ_THRESHOLD</key>
+ <value>8</value>
</entry>
<entry>
- <key>embeddedsw.memoryInfo.HAS_BYTE_LANE</key>
- <value>0</value>
+ <key>embeddedsw.CMacro.WRITE_DEPTH</key>
+ <value>64</value>
</entry>
<entry>
- <key>embeddedsw.memoryInfo.HEX_INSTALL_DIR</key>
- <value>QPF_DIR</value>
+ <key>embeddedsw.CMacro.WRITE_THRESHOLD</key>
+ <value>8</value>
</entry>
<entry>
- <key>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</key>
- <value>32</value>
+ <key>embeddedsw.dts.compatible</key>
+ <value>altr,juart-1.0</value>
</entry>
<entry>
- <key>embeddedsw.memoryInfo.MEM_INIT_FILENAME</key>
- <value>onchip_memory2_0</value>
+ <key>embeddedsw.dts.group</key>
+ <value>serial</value>
</entry>
<entry>
- <key>postgeneration.simulation.init_file.param_name</key>
- <value>INIT_FILE</value>
+ <key>embeddedsw.dts.name</key>
+ <value>juart</value>
</entry>
<entry>
- <key>postgeneration.simulation.init_file.type</key>
- <value>MEM_INIT</value>
+ <key>embeddedsw.dts.vendor</key>
+ <value>altr</value>
</entry>
</assignmentValueMap>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="pio_pps"
+ name="kernel_clk_export"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -13042,17 +5605,130 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>clk</name>
+ <type>clock</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>clk_out</name>
+ <role>clk</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedDirectClock</key>
+ <value>clk_in</value>
+ </entry>
+ <entry>
+ <key>clockRate</key>
+ <value>400000000</value>
+ </entry>
+ <entry>
+ <key>clockRateKnown</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk_in</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
+ <name>in_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>qsys.ui.export_name</key>
+ <value>clk</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>400000000</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk_in_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>qsys.ui.export_name</key>
+ <value>reset</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk_reset</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_n_out</name>
+ <role>reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -13064,70 +5740,183 @@
<key>associatedClock</key>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>associatedDirectReset</key>
+ <value>clk_in_reset</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>associatedResetSinks</key>
+ <value>clk_in_reset</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>clock_source</className>
+ <displayName>Clock Source</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>0</parameterDefaultValue>
+ <parameterName>inputClockFrequency</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>clk_in</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>clk</key>
+ <value>
+ <connectionPointName>clk</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>400000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>clk_in</key>
+ <value>
+ <connectionPointName>clk_in</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>400000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>board_kernel_clk</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>board_kernel_clk</fileSetName>
+ <fileSetFixedName>board_kernel_clk</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>board_kernel_clk</fileSetName>
+ <fileSetFixedName>board_kernel_clk</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>board_kernel_clk</fileSetName>
+ <fileSetFixedName>board_kernel_clk</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/board/board_kernel_clk.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="kernel_clk_gen"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
<interface>
<name>clk</name>
- <type>conduit</type>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>clk_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
- <assignmentValueMap/>
+ <assignmentValueMap>
+ <entry>
+ <key>qsys.ui.export_name</key>
+ <value>clk</value>
+ </entry>
+ </assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>50000000</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>mem</name>
+ <name>ctrl</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
+ <name>ctrl_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>ctrl_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
+ <name>ctrl_readdatavalid</name>
+ <role>readdatavalid</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>avs_mem_writedata</name>
+ <name>ctrl_burstcount</name>
+ <role>burstcount</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>ctrl_writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
@@ -13135,7 +5924,23 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>avs_mem_read</name>
+ <name>ctrl_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>ctrl_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>ctrl_read</name>
<role>read</role>
<direction>Input</direction>
<width>1</width>
@@ -13143,13 +5948,21 @@
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>ctrl_byteenable</name>
+ <role>byteenable</role>
+ <direction>Input</direction>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
+ <port>
+ <name>ctrl_debugaccess</name>
+ <role>debugaccess</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
</ports>
<assignments>
<assignmentValueMap>
@@ -13183,11 +5996,11 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>4096</value>
</entry>
<entry>
<key>addressUnits</key>
- <value>WORDS</value>
+ <value>SYMBOLS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
@@ -13195,11 +6008,11 @@
</entry>
<entry>
<key>associatedClock</key>
- <value>system</value>
+ <value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>system_reset</value>
+ <value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
@@ -13258,7 +6071,7 @@
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
- <value>0</value>
+ <value>4</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
@@ -13286,7 +6099,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
@@ -13340,110 +6153,14 @@
</parameters>
</interface>
<interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
+ <name>kernel_clk</name>
<type>clock</type>
- <isStart>false</isStart>
+ <isStart>true</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
+ <name>kernel_clk_clk</name>
<role>clk</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -13455,57 +6172,34 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedDirectClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>clockRate</key>
+ <value>400000000</value>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>clockRateKnown</key>
+ <value>true</value>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
<entry>
- <key>associatedClock</key>
- <value>system</value>
+ <key>externallyDriven</key>
+ <value>true</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
+ <name>kernel_clk2x</name>
+ <type>clock</type>
+ <isStart>true</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
+ <name>kernel_clk2x_clk</name>
+ <role>clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -13518,30 +6212,38 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>associatedDirectClock</key>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>clockRate</key>
+ <value>800000000</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>clockRateKnown</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>kernel_pll_locked</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>kernel_pll_locked_export</name>
<role>export</role>
<direction>Output</direction>
- <width>32</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -13562,620 +6264,192 @@
</parameterValueMap>
</parameters>
</interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
+ <interface>
+ <name>kernel_pll_refclk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>kernel_pll_refclk_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
<entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
</entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
<entry>
- <key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <key>clockRate</key>
+ <value>100000000</value>
</entry>
<entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
<entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
+ <key>ptfSchematicName</key>
</entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset_reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>qsys.ui.export_name</key>
+ <value>reset</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>acl_kernel_clk_a10</className>
+ <version>16.1</version>
+ <displayName>OpenCL A10 Kernel Clock Generator</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>AUTO_DEVICE</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfotype>DEVICE</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>AUTO_DEVICE_FAMILY</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfotype>DEVICE_FAMILY</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>ctrl</key>
+ <value>
+ <connectionPointName>ctrl</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='ctrl' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>12</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>kernel_clk</key>
+ <value>
+ <connectionPointName>kernel_clk</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>400000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>kernel_clk2x</key>
+ <value>
+ <connectionPointName>kernel_clk2x</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>800000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_pio_pps</hdlLibraryName>
+ <hdlLibraryName>board_kernel_clk_gen</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_pio_pps</fileSetName>
- <fileSetFixedName>board_pio_pps</fileSetFixedName>
+ <fileSetName>board_kernel_clk_gen</fileSetName>
+ <fileSetFixedName>board_kernel_clk_gen</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_pio_pps</fileSetName>
- <fileSetFixedName>board_pio_pps</fileSetFixedName>
+ <fileSetName>board_kernel_clk_gen</fileSetName>
+ <fileSetFixedName>board_kernel_clk_gen</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_pio_pps</fileSetName>
- <fileSetFixedName>board_pio_pps</fileSetFixedName>
+ <fileSetName>board_kernel_clk_gen</fileSetName>
+ <fileSetFixedName>board_kernel_clk_gen</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_pio_pps.ip</parameter>
+ <parameter name="logicalView">ip/board/board_kernel_clk_gen.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="pio_system_info"
+ name="kernel_interface"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14183,46 +6457,358 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
+ <name>acl_bsp_memorg_host0x018</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>5</width>
+ <name>acl_bsp_memorg_host0x018_mode</name>
+ <role>mode</role>
+ <direction>Output</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>clk_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>qsys.ui.export_name</key>
+ <value>clk</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>100000000</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>ctrl</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>ctrl_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>ctrl_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>ctrl_readdatavalid</name>
+ <role>readdatavalid</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>ctrl_burstcount</name>
+ <role>burstcount</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>ctrl_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>ctrl_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>14</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>ctrl_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>ctrl_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>ctrl_byteenable</name>
+ <role>byteenable</role>
+ <direction>Input</direction>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
+ <port>
+ <name>ctrl_debugaccess</name>
+ <role>debugaccess</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
</ports>
<assignments>
- <assignmentValueMap/>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>16384</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>SYMBOLS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
<entry>
<key>associatedClock</key>
+ <value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
+ <value>reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>kernel_clk</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>kernel_clk_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -14234,101 +6820,120 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>mem</name>
+ <name>kernel_cra</name>
<type>avalon</type>
- <isStart>false</isStart>
+ <isStart>true</isStart>
<ports>
<port>
- <name>avs_mem_address</name>
+ <name>kernel_cra_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>kernel_cra_readdata</name>
+ <role>readdata</role>
+ <direction>Input</direction>
+ <width>64</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>kernel_cra_readdatavalid</name>
+ <role>readdatavalid</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>kernel_cra_burstcount</name>
+ <role>burstcount</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>kernel_cra_writedata</name>
+ <role>writedata</role>
+ <direction>Output</direction>
+ <width>64</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>kernel_cra_address</name>
<role>address</role>
- <direction>Input</direction>
- <width>5</width>
+ <direction>Output</direction>
+ <width>30</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>avs_mem_write</name>
+ <name>kernel_cra_write</name>
<role>write</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
+ <name>kernel_cra_read</name>
<role>read</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
+ <name>kernel_cra_byteenable</name>
+ <role>byteenable</role>
<direction>Output</direction>
- <width>32</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
+ <port>
+ <name>kernel_cra_debugaccess</name>
+ <role>debugaccess</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
</ports>
<assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
+ <assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
+ <key>adaptsTo</key>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
- <entry>
- <key>addressSpan</key>
- <value>128</value>
- </entry>
<entry>
<key>addressUnits</key>
- <value>WORDS</value>
+ <value>SYMBOLS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
@@ -14336,23 +6941,16 @@
</entry>
<entry>
<key>associatedClock</key>
- <value>system</value>
+ <value>kernel_clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>system_reset</value>
+ <value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
@@ -14366,8 +6964,16 @@
<value>false</value>
</entry>
<entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
+ <key>dBSBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>doStreamReads</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>doStreamWrites</key>
+ <value>false</value>
</entry>
<entry>
<key>holdTime</key>
@@ -14378,25 +6984,29 @@
<value>false</value>
</entry>
<entry>
- <key>isBigEndian</key>
+ <key>isAsynchronous</key>
<value>false</value>
</entry>
<entry>
- <key>isFlash</key>
+ <key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
- <key>isMemoryDevice</key>
+ <key>isReadable</key>
<value>false</value>
</entry>
<entry>
- <key>isNonVolatileStorage</key>
+ <key>isWriteable</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
+ <entry>
+ <key>maxAddressWidth</key>
+ <value>32</value>
+ </entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
@@ -14413,29 +7023,17 @@
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
<entry>
<key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>readWaitTime</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
@@ -14453,26 +7051,10 @@
<key>timingUnits</key>
<value>Cycles</value>
</entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
@@ -14481,17 +7063,17 @@
</parameters>
</interface>
<interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
+ <name>kernel_irq_from_kernel</name>
+ <type>interrupt</type>
+ <isStart>true</isStart>
<ports>
<port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>kernel_irq_from_kernel_irq</name>
+ <role>irq</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -14500,58 +7082,35 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>associatedAddressablePoint</key>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>kernel_clk</value>
</entry>
<entry>
<key>associatedReset</key>
+ <value>reset</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>irqMap</key>
+ <value><map><mapping port='0' sender='sender0_irq' /></map></value>
+ </entry>
+ <entry>
+ <key>irqScheme</key>
+ <value>INDIVIDUAL_REQUESTS</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>reset</name>
- <type>conduit</type>
+ <name>kernel_irq_to_host</name>
+ <type>interrupt</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
- <role>export</role>
+ <name>kernel_irq_to_host_irq</name>
+ <role>irq</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -14563,28 +7122,41 @@
</assignments>
<parameters>
<parameterValueMap>
+ <entry>
+ <key>associatedAddressablePoint</key>
+ </entry>
<entry>
<key>associatedClock</key>
+ <value>kernel_clk</value>
</entry>
<entry>
<key>associatedReset</key>
+ <value>reset</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>bridgedReceiverOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToReceiver</key>
+ <value>kernel_interface.kernel_irq_from_kernel</value>
+ </entry>
+ <entry>
+ <key>irqScheme</key>
+ <value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
+ <name>kernel_reset</name>
+ <type>reset</type>
+ <isStart>true</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>kernel_reset_reset_n</name>
+ <role>reset_n</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -14596,27 +7168,32 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
+ <value>kernel_clk</value>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedDirectReset</key>
+ <value>reset</value>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>associatedResetSinks</key>
+ <value>reset,reset,sw_reset_in</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
+ <name>reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
+ <name>reset_reset_n</name>
+ <role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -14624,13 +7201,18 @@
</port>
</ports>
<assignments>
- <assignmentValueMap/>
+ <assignmentValueMap>
+ <entry>
+ <key>qsys.ui.export_name</key>
+ <value>reset</value>
+ </entry>
+ </assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
+ <value>clk</value>
</entry>
<entry>
<key>synchronousEdges</key>
@@ -14640,13 +7222,13 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
+ <name>sw_reset_export</name>
+ <type>reset</type>
+ <isStart>true</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
+ <name>sw_reset_export_reset_n</name>
+ <role>reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -14660,29 +7242,35 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>clk</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>associatedDirectReset</key>
+ <value>reset</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>associatedResetSinks</key>
+ <value>reset,sw_reset_in</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>sw_reset_in</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>sw_reset_in_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -14692,13 +7280,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>clk</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -14706,617 +7292,90 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
+ <className>kernel_interface</className>
+ <version>15.1</version>
+ <displayName>OpenCL Kernel Interface</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>AUTO_DEVICE</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfotype>DEVICE</systemInfotype>
</descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>7</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>5</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>5</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>128</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>AUTO_DEVICE_FAMILY</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfotype>DEVICE_FAMILY</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>ctrl</key>
+ <value>
+ <connectionPointName>ctrl</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='ctrl' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>14</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_pio_system_info</hdlLibraryName>
+ <hdlLibraryName>board_kernel_interface</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_pio_system_info</fileSetName>
- <fileSetFixedName>board_pio_system_info</fileSetFixedName>
+ <fileSetName>board_kernel_interface</fileSetName>
+ <fileSetFixedName>board_kernel_interface</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_pio_system_info</fileSetName>
- <fileSetFixedName>board_pio_system_info</fileSetFixedName>
+ <fileSetName>board_kernel_interface</fileSetName>
+ <fileSetFixedName>board_kernel_interface</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_pio_system_info</fileSetName>
- <fileSetFixedName>board_pio_system_info</fileSetFixedName>
+ <fileSetName>board_kernel_interface</fileSetName>
+ <fileSetFixedName>board_kernel_interface</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_pio_system_info.ip</parameter>
+ <parameter name="logicalView">ip/board/board_kernel_interface.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="pio_wdi"
+ name="onchip_memory2_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -15324,7 +7383,7 @@
<boundary>
<interfaces>
<interface>
- <name>clk</name>
+ <name>clk1</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
@@ -15357,45 +7416,21 @@
</parameters>
</interface>
<interface>
- <name>external_connection</name>
- <type>conduit</type>
+ <name>reset1</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>out_port</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
<port>
- <name>reset_n</name>
- <role>reset_n</role>
+ <name>reset_req</name>
+ <role>reset_req</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -15409,7 +7444,7 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>clk</value>
+ <value>clk1</value>
</entry>
<entry>
<key>synchronousEdges</key>
@@ -15427,984 +7462,431 @@
<name>address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>write_n</name>
- <role>write_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>chipselect</name>
- <role>chipselect</role>
+ <name>clken</name>
+ <role>clken</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
- <port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>NATIVE</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>4</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
+ <port>
+ <name>chipselect</name>
+ <role>chipselect</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>byteenable</name>
+ <role>byteenable</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
<entry>
- <key>readLatency</key>
+ <key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
<value>1</value>
</entry>
<entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
<entry>
- <key>writeWaitStates</key>
- <value>0</value>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
</entry>
<entry>
- <key>writeWaitTime</key>
+ <key>addressGroup</key>
<value>0</value>
</entry>
- </parameterValueMap>
- </parameters>
- <cmsisInfo>
- <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
-<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
- <peripherals>
- <peripheral>
- <name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>32</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>DATA</name>
- <displayName>Data</displayName>
- <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
- <addressOffset>0x0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>data</name>
- <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>DIRECTION</name>
- <displayName>Direction</displayName>
- <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>direction</name>
- <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>IRQ_MASK</name>
- <displayName>Interrupt mask</displayName>
- <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>interruptmask</name>
- <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>EDGE_CAP</name>
- <displayName>Edge capture</displayName>
- <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
- <addressOffset>0xc</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>edgecapture</name>
- <description>Edge detection for each input port.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>SET_BIT</name>
- <displayName>Outset</displayName>
- <description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
- <addressOffset>0x10</addressOffset>
- <size>32</size>
- <access>write-only</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>outset</name>
- <description>Specifies which bit of the output port to set.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>write-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CLEAR_BITS</name>
- <displayName>Outclear</displayName>
- <description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
- <addressOffset>0x14</addressOffset>
- <size>32</size>
- <access>write-only</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>outclear</name>
- <description>Specifies which output bit to clear.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>write-only</access>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device> </cmsisSrcFileContents>
- <addressGroup></addressGroup>
- <cmsisVars/>
- </cmsisInfo>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>altera_avalon_pio</className>
- <version>19.1</version>
- <displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>0</parameterDefaultValue>
- <parameterName>clockRate</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>clk</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>clk</key>
- <value>
- <connectionPointName>clk</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
<entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>s1</key>
- <value>
- <connectionPointName>s1</connectionPointName>
- <suppliedSystemInfos>
+ <key>addressSpan</key>
+ <value>131072</value>
+ </entry>
<entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <key>addressUnits</key>
+ <value>WORDS</value>
</entry>
<entry>
- <key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
</entry>
<entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
+ <key>associatedClock</key>
+ <value>clk1</value>
</entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>external_connection</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>out_port</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>s1</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>2</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>write_n</name>
- <role>write_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>chipselect</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>NATIVE</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>4</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- <cmsisInfo>
- <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
-<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
- <peripherals>
- <peripheral>
- <name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>32</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>DATA</name>
- <displayName>Data</displayName>
- <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
- <addressOffset>0x0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>data</name>
- <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>DIRECTION</name>
- <displayName>Direction</displayName>
- <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>direction</name>
- <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>IRQ_MASK</name>
- <displayName>Interrupt mask</displayName>
- <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>interruptmask</name>
- <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>EDGE_CAP</name>
- <displayName>Edge capture</displayName>
- <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
- <addressOffset>0xc</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>edgecapture</name>
- <description>Edge detection for each input port.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>SET_BIT</name>
- <displayName>Outset</displayName>
- <description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
- <addressOffset>0x10</addressOffset>
- <size>32</size>
- <access>write-only</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>outset</name>
- <description>Specifies which bit of the output port to set.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>write-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CLEAR_BITS</name>
- <displayName>Outclear</displayName>
- <description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
- <addressOffset>0x14</addressOffset>
- <size>32</size>
- <access>write-only</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>outclear</name>
- <description>Specifies which output bit to clear.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>write-only</access>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device> </cmsisSrcFileContents>
- <addressGroup></addressGroup>
- <cmsisVars/>
- </cmsisInfo>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ <entry>
+ <key>associatedReset</key>
+ <value>reset1</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>131072</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>altera_avalon_onchip_memory2</className>
+ <version>18.0</version>
+ <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue></parameterDefaultValue>
+ <parameterName>autoInitializationFileName</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfotype>UNIQUE_ID</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>NONE</parameterDefaultValue>
+ <parameterName>deviceFamily</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfotype>DEVICE_FAMILY</systemInfotype>
+ </descriptor>
+ <descriptor>
+ <parameterDefaultValue>NONE</parameterDefaultValue>
+ <parameterName>deviceFeatures</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfotype>DEVICE_FEATURES</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>s1</key>
+ <value>
+ <connectionPointName>s1</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='s1' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>17</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_pio_wdi</hdlLibraryName>
+ <hdlLibraryName>board_onchip_memory2_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_pio_wdi</fileSetName>
- <fileSetFixedName>board_pio_wdi</fileSetFixedName>
+ <fileSetName>board_onchip_memory2_0</fileSetName>
+ <fileSetFixedName>board_onchip_memory2_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_pio_wdi</fileSetName>
- <fileSetFixedName>board_pio_wdi</fileSetFixedName>
+ <fileSetName>board_onchip_memory2_0</fileSetName>
+ <fileSetFixedName>board_onchip_memory2_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_pio_wdi</fileSetName>
- <fileSetFixedName>board_pio_wdi</fileSetFixedName>
+ <fileSetName>board_onchip_memory2_0</fileSetName>
+ <fileSetFixedName>board_onchip_memory2_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_pio_wdi.ip</parameter>
+ <parameter name="logicalView">ip/board/board_onchip_memory2_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
- <key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key>
+ <key>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</key>
<value>0</value>
</entry>
<entry>
- <key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key>
+ <key>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</key>
<value>0</value>
</entry>
<entry>
- <key>embeddedsw.CMacro.CAPTURE</key>
+ <key>embeddedsw.CMacro.CONTENTS_INFO</key>
+ <value>""</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.DUAL_PORT</key>
<value>0</value>
</entry>
<entry>
- <key>embeddedsw.CMacro.DATA_WIDTH</key>
- <value>1</value>
+ <key>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</key>
+ <value>AUTO</value>
</entry>
<entry>
- <key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key>
- <value>0</value>
+ <key>embeddedsw.CMacro.INIT_CONTENTS_FILE</key>
+ <value>onchip_memory2_0</value>
</entry>
<entry>
- <key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key>
- <value>0</value>
+ <key>embeddedsw.CMacro.INIT_MEM_CONTENT</key>
+ <value>1</value>
</entry>
<entry>
- <key>embeddedsw.CMacro.EDGE_TYPE</key>
+ <key>embeddedsw.CMacro.INSTANCE_ID</key>
<value>NONE</value>
</entry>
<entry>
- <key>embeddedsw.CMacro.FREQ</key>
- <value>100000000</value>
+ <key>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</key>
+ <value>1</value>
</entry>
<entry>
- <key>embeddedsw.CMacro.HAS_IN</key>
+ <key>embeddedsw.CMacro.RAM_BLOCK_TYPE</key>
+ <value>AUTO</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.READ_DURING_WRITE_MODE</key>
+ <value>DONT_CARE</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.SINGLE_CLOCK_OP</key>
<value>0</value>
</entry>
<entry>
- <key>embeddedsw.CMacro.HAS_OUT</key>
+ <key>embeddedsw.CMacro.SIZE_MULTIPLE</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.SIZE_VALUE</key>
+ <value>131072</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.WRITABLE</key>
<value>1</value>
</entry>
<entry>
- <key>embeddedsw.CMacro.HAS_TRI</key>
- <value>0</value>
+ <key>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</key>
+ <value>SIM_DIR</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.memoryInfo.GENERATE_DAT_SYM</key>
+ <value>1</value>
</entry>
<entry>
- <key>embeddedsw.CMacro.IRQ_TYPE</key>
- <value>NONE</value>
+ <key>embeddedsw.memoryInfo.GENERATE_HEX</key>
+ <value>1</value>
</entry>
<entry>
- <key>embeddedsw.CMacro.RESET_VALUE</key>
+ <key>embeddedsw.memoryInfo.HAS_BYTE_LANE</key>
<value>0</value>
</entry>
<entry>
- <key>embeddedsw.dts.compatible</key>
- <value>altr,pio-1.0</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.group</key>
- <value>gpio</value>
+ <key>embeddedsw.memoryInfo.HEX_INSTALL_DIR</key>
+ <value>QPF_DIR</value>
</entry>
<entry>
- <key>embeddedsw.dts.name</key>
- <value>pio</value>
+ <key>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</key>
+ <value>32</value>
</entry>
<entry>
- <key>embeddedsw.dts.params.altr,gpio-bank-width</key>
- <value>1</value>
+ <key>embeddedsw.memoryInfo.MEM_INIT_FILENAME</key>
+ <value>onchip_memory2_0</value>
</entry>
<entry>
- <key>embeddedsw.dts.params.resetvalue</key>
- <value>0</value>
+ <key>postgeneration.simulation.init_file.param_name</key>
+ <value>INIT_FILE</value>
</entry>
<entry>
- <key>embeddedsw.dts.vendor</key>
- <value>altr</value>
+ <key>postgeneration.simulation.init_file.type</key>
+ <value>MEM_INIT</value>
</entry>
</assignmentValueMap>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="pio_pps"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16912,640 +8394,115 @@
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>3</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>board_pio_pps</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>board_pio_pps</fileSetName>
+ <fileSetFixedName>board_pio_pps</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>board_pio_pps</fileSetName>
+ <fileSetFixedName>board_pio_pps</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>board_pio_pps</fileSetName>
+ <fileSetFixedName>board_pio_pps</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/board/board_pio_pps.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="pio_system_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17561,7 +8518,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17625,7 +8582,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17694,7 +8651,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18100,11 +9057,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18130,563 +9087,38 @@
</connPtSystemInfos>
</systemInfos>
</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>board_pio_system_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_dpmm_data</fileSetName>
- <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>board_pio_system_info</fileSetName>
+ <fileSetFixedName>board_pio_system_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_dpmm_data</fileSetName>
- <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>board_pio_system_info</fileSetName>
+ <fileSetFixedName>board_pio_system_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_dpmm_data</fileSetName>
- <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>board_pio_system_info</fileSetName>
+ <fileSetFixedName>board_pio_system_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">ip/board/board_pio_system_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="pio_wdi"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18694,17 +9126,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>clk</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>3</width>
+ <name>clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -18713,25 +9145,26 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>external_connection</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>out_port</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -18758,28 +9191,58 @@
</parameters>
</interface>
<interface>
- <name>mem</name>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>s1</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
- <name>avs_mem_address</name>
+ <name>address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>avs_mem_write</name>
- <role>write</role>
+ <name>write_n</name>
+ <role>write_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>avs_mem_writedata</name>
+ <name>writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
@@ -18787,15 +9250,15 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>avs_mem_read</name>
- <role>read</role>
+ <name>chipselect</name>
+ <role>chipselect</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>avs_mem_readdata</name>
+ <name>readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
@@ -18827,7 +9290,7 @@
<parameterValueMap>
<entry>
<key>addressAlignment</key>
- <value>DYNAMIC</value>
+ <value>NATIVE</value>
</entry>
<entry>
<key>addressGroup</key>
@@ -18835,7 +9298,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>4</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18847,11 +9310,11 @@
</entry>
<entry>
<key>associatedClock</key>
- <value>system</value>
+ <value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>system_reset</value>
+ <value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
@@ -18910,324 +9373,228 @@
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
+ <value>0</value>
+ </entry>
<entry>
- <key>associatedClock</key>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
<entry>
- <key>clockRate</key>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
<value>0</value>
</entry>
<entry>
- <key>externallyDriven</key>
+ <key>readWaitStates</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
<entry>
- <key>associatedClock</key>
- <value>system</value>
+ <key>setupTime</key>
+ <value>0</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>timingUnits</key>
+ <value>Cycles</value>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>transparentBridge</key>
+ <value>false</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
</entry>
<entry>
- <key>prSafe</key>
+ <key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>writeLatency</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>writeWaitStates</key>
+ <value>0</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>writeWaitTime</key>
+ <value>0</value>
</entry>
</parameterValueMap>
</parameters>
+ <cmsisInfo>
+ <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
+ <peripherals>
+ <peripheral>
+ <name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>32</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>DATA</name>
+ <displayName>Data</displayName>
+ <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
+ <addressOffset>0x0</addressOffset>
+ <size>32</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <resetMask>0xffffffff</resetMask>
+ <fields>
+ <field><name>data</name>
+ <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
+ <bitOffset>0x0</bitOffset>
+ <bitWidth>32</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIRECTION</name>
+ <displayName>Direction</displayName>
+ <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
+ <addressOffset>0x4</addressOffset>
+ <size>32</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <resetMask>0xffffffff</resetMask>
+ <fields>
+ <field><name>direction</name>
+ <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
+ <bitOffset>0x0</bitOffset>
+ <bitWidth>32</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IRQ_MASK</name>
+ <displayName>Interrupt mask</displayName>
+ <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
+ <addressOffset>0x8</addressOffset>
+ <size>32</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <resetMask>0xffffffff</resetMask>
+ <fields>
+ <field><name>interruptmask</name>
+ <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
+ <bitOffset>0x0</bitOffset>
+ <bitWidth>32</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EDGE_CAP</name>
+ <displayName>Edge capture</displayName>
+ <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
+ <addressOffset>0xc</addressOffset>
+ <size>32</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <resetMask>0xffffffff</resetMask>
+ <fields>
+ <field><name>edgecapture</name>
+ <description>Edge detection for each input port.</description>
+ <bitOffset>0x0</bitOffset>
+ <bitWidth>32</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SET_BIT</name>
+ <displayName>Outset</displayName>
+ <description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
+ <addressOffset>0x10</addressOffset>
+ <size>32</size>
+ <access>write-only</access>
+ <resetValue>0x0</resetValue>
+ <resetMask>0xffffffff</resetMask>
+ <fields>
+ <field><name>outset</name>
+ <description>Specifies which bit of the output port to set.</description>
+ <bitOffset>0x0</bitOffset>
+ <bitWidth>32</bitWidth>
+ <access>write-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CLEAR_BITS</name>
+ <displayName>Outclear</displayName>
+ <description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
+ <addressOffset>0x14</addressOffset>
+ <size>32</size>
+ <access>write-only</access>
+ <resetValue>0x0</resetValue>
+ <resetMask>0xffffffff</resetMask>
+ <fields>
+ <field><name>outclear</name>
+ <description>Specifies which output bit to clear.</description>
+ <bitOffset>0x0</bitOffset>
+ <bitWidth>32</bitWidth>
+ <access>write-only</access>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ </peripherals>
+</device> </cmsisSrcFileContents>
+ <addressGroup></addressGroup>
+ <cmsisVars/>
+ </cmsisInfo>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
+ <className>altera_avalon_pio</className>
+ <version>18.0</version>
+ <displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterDefaultValue>0</parameterDefaultValue>
+ <parameterName>clockRate</parameterName>
<parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
+ <systemInfoArgs>clk</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
</descriptors>
@@ -19235,17 +9602,30 @@
<systemInfos>
<connPtSystemInfos>
<entry>
- <key>mem</key>
+ <key>clk</key>
<value>
- <connectionPointName>mem</connectionPointName>
+ <connectionPointName>clk</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>s1</key>
+ <value>
+ <connectionPointName>s1</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19255,579 +9635,118 @@
<consumedSystemInfos/>
</value>
</entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>32</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>board_pio_wdi</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_epcs</fileSetName>
- <fileSetFixedName>board_reg_epcs</fileSetFixedName>
+ <fileSetName>board_pio_wdi</fileSetName>
+ <fileSetFixedName>board_pio_wdi</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_epcs</fileSetName>
- <fileSetFixedName>board_reg_epcs</fileSetFixedName>
+ <fileSetName>board_pio_wdi</fileSetName>
+ <fileSetFixedName>board_pio_wdi</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_epcs</fileSetName>
- <fileSetFixedName>board_reg_epcs</fileSetFixedName>
+ <fileSetName>board_pio_wdi</fileSetName>
+ <fileSetFixedName>board_pio_wdi</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_epcs.ip</parameter>
+ <parameter name="logicalView">ip/board/board_pio_wdi.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.CAPTURE</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.DATA_WIDTH</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.EDGE_TYPE</key>
+ <value>NONE</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.FREQ</key>
+ <value>100000000</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.HAS_IN</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.HAS_OUT</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.HAS_TRI</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.IRQ_TYPE</key>
+ <value>NONE</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.RESET_VALUE</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.compatible</key>
+ <value>altr,pio-1.0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.group</key>
+ <value>gpio</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.name</key>
+ <value>pio</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.params.altr,gpio-bank-width</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.params.resetvalue</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.vendor</key>
+ <value>altr</value>
+ </entry>
+ </assignmentValueMap>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19843,7 +9762,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19907,7 +9826,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19976,7 +9895,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20352,623 +10271,98 @@
<key>prSafe</key>
<value>false</value>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>5</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>32</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>board_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>board_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>board_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>board_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20984,7 +10378,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21048,7 +10442,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21117,7 +10511,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21523,593 +10917,68 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>6</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>64</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>board_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>board_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>board_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>board_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22125,7 +10994,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22189,7 +11058,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22258,7 +11127,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -22632,625 +11501,100 @@
</entry>
<entry>
<key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>3</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>5</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>board_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>board_reg_epcs</fileSetName>
+ <fileSetFixedName>board_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>board_reg_epcs</fileSetName>
+ <fileSetFixedName>board_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>board_reg_epcs</fileSetName>
+ <fileSetFixedName>board_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23266,7 +11610,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23330,7 +11674,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23399,7 +11743,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -23805,593 +12149,68 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
+ <value>5</value>
</entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>board_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_mmdp_data</fileSetName>
- <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>board_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_mmdp_data</fileSetName>
- <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>board_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_mmdp_data</fileSetName>
- <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>board_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -24407,7 +12226,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24471,7 +12290,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24540,7 +12359,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24910,629 +12729,104 @@
<key>associatedClock</key>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>5</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>32</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>6</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_remu</hdlLibraryName>
+ <hdlLibraryName>board_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_remu</fileSetName>
- <fileSetFixedName>board_reg_remu</fileSetFixedName>
+ <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_remu</fileSetName>
- <fileSetFixedName>board_reg_remu</fileSetFixedName>
+ <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_remu</fileSetName>
- <fileSetFixedName>board_reg_remu</fileSetFixedName>
+ <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_remu.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_unb_pmbus"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -25548,7 +12842,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25612,7 +12906,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25681,7 +12975,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26087,593 +13381,68 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
<value>32</value>
</entry>
</suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>6</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>6</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>256</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_unb_pmbus</hdlLibraryName>
+ <hdlLibraryName>board_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>board_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>board_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>board_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>board_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>board_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>board_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_unb_pmbus.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_unb_sens"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26689,7 +13458,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26753,7 +13522,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26822,7 +13591,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27188,633 +13957,108 @@
</assignments>
<parameters>
<parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>8</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>6</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>6</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>256</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_unb_sens</hdlLibraryName>
+ <hdlLibraryName>board_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_unb_sens</fileSetName>
- <fileSetFixedName>board_reg_unb_sens</fileSetFixedName>
+ <fileSetName>board_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_unb_sens</fileSetName>
- <fileSetFixedName>board_reg_unb_sens</fileSetFixedName>
+ <fileSetName>board_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_unb_sens</fileSetName>
- <fileSetFixedName>board_reg_unb_sens</fileSetFixedName>
+ <fileSetName>board_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_unb_sens.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_wdi"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -27830,7 +14074,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27894,7 +14138,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27963,7 +14207,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28369,11 +14613,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28383,579 +14627,54 @@
<consumedSystemInfos/>
</value>
</entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_wdi</hdlLibraryName>
+ <hdlLibraryName>board_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_wdi</fileSetName>
- <fileSetFixedName>board_reg_wdi</fileSetFixedName>
+ <fileSetName>board_reg_remu</fileSetName>
+ <fileSetFixedName>board_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_wdi</fileSetName>
- <fileSetFixedName>board_reg_wdi</fileSetFixedName>
+ <fileSetName>board_reg_remu</fileSetName>
+ <fileSetFixedName>board_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_wdi</fileSetName>
- <fileSetFixedName>board_reg_wdi</fileSetFixedName>
+ <fileSetName>board_reg_remu</fileSetName>
+ <fileSetFixedName>board_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_wdi.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="rom_system_info"
+ name="reg_ta2_unb2b_jesd204b"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -28971,7 +14690,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>10</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29035,7 +14754,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>10</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29071,6 +14790,14 @@
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
+ <port>
+ <name>avs_mem_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
</ports>
<assignments>
<assignmentValueMap>
@@ -29104,7 +14831,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>4096</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29207,15 +14934,15 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
@@ -29419,6 +15146,38 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>waitrequest</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_waitrequest_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>write</name>
<type>conduit</type>
@@ -29486,9 +15245,9 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>avs_common_mm</className>
+ <className>avs_common_mm_readlatency0</className>
<version>1.0</version>
- <displayName>avs_common_mm</displayName>
+ <displayName>avs_common_mm_readlatency0</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
@@ -29510,593 +15269,68 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>12</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>10</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>10</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>4096</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>10</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_rom_system_info</hdlLibraryName>
+ <hdlLibraryName>board_reg_ta2_unb2b_jesd204b</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_rom_system_info</fileSetName>
- <fileSetFixedName>board_rom_system_info</fileSetFixedName>
+ <fileSetName>board_reg_ta2_unb2b_jesd204b</fileSetName>
+ <fileSetFixedName>board_reg_ta2_unb2b_jesd204b</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_rom_system_info</fileSetName>
- <fileSetFixedName>board_rom_system_info</fileSetFixedName>
+ <fileSetName>board_reg_ta2_unb2b_jesd204b</fileSetName>
+ <fileSetFixedName>board_reg_ta2_unb2b_jesd204b</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_rom_system_info</fileSetName>
- <fileSetFixedName>board_rom_system_info</fileSetFixedName>
+ <fileSetName>board_reg_ta2_unb2b_jesd204b</fileSetName>
+ <fileSetFixedName>board_reg_ta2_unb2b_jesd204b</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_rom_system_info.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_ta2_unb2b_jesd204b.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ta2_unb2b_10GbE"
+ name="reg_unb_pmbus"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30104,17 +15338,17 @@
<boundary>
<interfaces>
<interface>
- <name>config_reset</name>
- <type>reset</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>config_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -30126,21 +15360,24 @@
<key>associatedClock</key>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>kernel_clk</name>
- <type>clock</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>kernel_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -30152,166 +15389,260 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>kernel_reset</name>
- <type>reset</type>
+ <name>mem</name>
+ <type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
- <name>kernel_reset</name>
- <role>reset</role>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_snk</name>
- <type>avalon_streaming</type>
- <isStart>false</isStart>
- <ports>
<port>
- <name>kernel_snk_data</name>
- <role>data</role>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
<direction>Input</direction>
- <width>72</width>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>kernel_snk_ready</name>
- <role>ready</role>
- <direction>Output</direction>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>kernel_snk_valid</name>
- <role>valid</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
- <assignmentValueMap/>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
<entry>
<key>associatedClock</key>
- <value>kernel_clk</value>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
</entry>
<entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
+ <key>readWaitStates</key>
+ <value>0</value>
</entry>
<entry>
- <key>beatsPerCycle</key>
- <value>1</value>
+ <key>readWaitTime</key>
+ <value>0</value>
</entry>
<entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
</entry>
<entry>
- <key>emptyWithinPacket</key>
+ <key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
- <key>errorDescriptor</key>
+ <key>setupTime</key>
+ <value>0</value>
</entry>
<entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
+ <key>timingUnits</key>
+ <value>Cycles</value>
</entry>
<entry>
- <key>highOrderSymbolAtMSB</key>
+ <key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
- <key>maxChannel</key>
+ <key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
+ <key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
- <key>readyAllowance</key>
+ <key>writeLatency</key>
<value>0</value>
</entry>
<entry>
- <key>readyLatency</key>
+ <key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
+ <key>writeWaitTime</key>
+ <value>0</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>kernel_src</name>
- <type>avalon_streaming</type>
- <isStart>true</isStart>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
<ports>
<port>
- <name>kernel_src_data</name>
- <role>data</role>
- <direction>Output</direction>
- <width>72</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_src_ready</name>
- <role>ready</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_src_valid</name>
- <role>valid</role>
+ <name>coe_read_export</name>
+ <role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -30325,71 +15656,58 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>kernel_clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
</entry>
<entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
+ <key>prSafe</key>
<value>false</value>
</entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
<entry>
- <key>maxChannel</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>packetDescription</key>
- <value></value>
+ <key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>refclk</name>
- <type>clock</type>
+ <name>reset</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>clk_ref_r</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -30401,27 +15719,26 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>rx_serial_data</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>rx_serial_r</name>
- <role>conduit</role>
+ <name>csi_system_clk</name>
+ <role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -30434,27 +15751,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>rx_status</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>rx_status</name>
- <role>rx_status</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -30467,25 +15785,23 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>tx_serial_data</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>tx_serial_r</name>
- <role>conduit</role>
+ <name>coe_write_export</name>
+ <role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -30510,463 +15826,127 @@
</parameterValueMap>
</parameters>
</interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>ta2_unb2b_10GbE</className>
- <version>1.0</version>
- <displayName>ta2_unb2b_10GbE</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors/>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos/>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>config_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>config_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_snk</name>
- <type>avalon_streaming</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_snk_data</name>
- <role>data</role>
- <direction>Input</direction>
- <width>72</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_snk_ready</name>
- <role>ready</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_snk_valid</name>
- <role>valid</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_src</name>
- <type>avalon_streaming</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_src_data</name>
- <role>data</role>
- <direction>Output</direction>
- <width>72</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_src_ready</name>
- <role>ready</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_src_valid</name>
- <role>valid</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>refclk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk_ref_r</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>rx_serial_data</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>rx_serial_r</name>
- <role>conduit</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>rx_status</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>rx_status</name>
- <role>rx_status</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>tx_serial_data</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>tx_serial_r</name>
- <role>conduit</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_ta2_unb2b_10GbE</hdlLibraryName>
+ <hdlLibraryName>board_reg_unb_pmbus</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_ta2_unb2b_10GbE</fileSetName>
- <fileSetFixedName>board_ta2_unb2b_10GbE</fileSetFixedName>
+ <fileSetName>board_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>board_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_ta2_unb2b_10GbE</fileSetName>
- <fileSetFixedName>board_ta2_unb2b_10GbE</fileSetFixedName>
+ <fileSetName>board_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>board_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_ta2_unb2b_10GbE</fileSetName>
- <fileSetFixedName>board_ta2_unb2b_10GbE</fileSetFixedName>
+ <fileSetName>board_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>board_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_ta2_unb2b_10GbE.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_unb_pmbus.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ta2_unb2b_1GbE_mc"
+ name="reg_unb_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30974,17 +15954,17 @@
<boundary>
<interfaces>
<interface>
- <name>kernel_clk</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>kernel_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -30993,28 +15973,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>kernel_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>kernel_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -31027,210 +16006,260 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>kernel_clk</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>kernel_snk</name>
- <type>avalon_streaming</type>
+ <name>mem</name>
+ <type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
- <name>kernel_snk_data</name>
- <role>data</role>
+ <name>avs_mem_address</name>
+ <role>address</role>
<direction>Input</direction>
- <width>40</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>kernel_snk_ready</name>
- <role>ready</role>
- <direction>Output</direction>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>kernel_snk_valid</name>
- <role>valid</role>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
</ports>
<assignments>
- <assignmentValueMap/>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
<entry>
<key>associatedClock</key>
- <value>kernel_clk</value>
+ <value>system</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>kernel_reset</value>
+ <value>system_reset</value>
</entry>
<entry>
- <key>beatsPerCycle</key>
- <value>1</value>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
</entry>
<entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
</entry>
<entry>
- <key>emptyWithinPacket</key>
+ <key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
- <key>errorDescriptor</key>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
</entry>
<entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
</entry>
<entry>
- <key>highOrderSymbolAtMSB</key>
+ <key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
- <key>maxChannel</key>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
- <key>packetDescription</key>
- <value></value>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
+ <key>printableDevice</key>
+ <value>false</value>
</entry>
<entry>
- <key>symbolsPerBeat</key>
+ <key>readLatency</key>
<value>1</value>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_src</name>
- <type>avalon_streaming</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_src_data</name>
- <role>data</role>
- <direction>Output</direction>
- <width>40</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_src_ready</name>
- <role>ready</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_src_valid</name>
- <role>valid</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
<entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
+ <key>readWaitStates</key>
+ <value>0</value>
</entry>
<entry>
- <key>beatsPerCycle</key>
- <value>1</value>
+ <key>readWaitTime</key>
+ <value>0</value>
</entry>
<entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
</entry>
<entry>
- <key>emptyWithinPacket</key>
+ <key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
- <key>errorDescriptor</key>
+ <key>setupTime</key>
+ <value>0</value>
</entry>
<entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
+ <key>timingUnits</key>
+ <value>Cycles</value>
</entry>
<entry>
- <key>highOrderSymbolAtMSB</key>
+ <key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
- <key>maxChannel</key>
+ <key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
+ <key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
- <key>readyAllowance</key>
+ <key>writeLatency</key>
<value>0</value>
</entry>
<entry>
- <key>readyLatency</key>
+ <key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
+ <key>writeWaitTime</key>
+ <value>0</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>st_clk</name>
- <type>clock</type>
+ <name>read</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>st_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -31242,31 +16271,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>st_rst</name>
- <type>reset</type>
+ <name>readdata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>st_rst</name>
- <role>reset</role>
+ <name>coe_readdata_export</name>
+ <role>export</role>
<direction>Input</direction>
- <width>1</width>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -31276,68 +16304,30 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>st_clk</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>udp_rx_snk_in</name>
- <type>avalon_streaming</type>
+ <name>reset</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>udp_rx_siso_ready</name>
- <role>ready</role>
+ <name>coe_reset_export</name>
+ <role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
- <port>
- <name>udp_rx_sosi_data</name>
- <role>data</role>
- <direction>Input</direction>
- <width>40</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>udp_rx_sosi_empty</name>
- <role>empty</role>
- <direction>Input</direction>
- <width>2</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>udp_rx_sosi_eop</name>
- <role>endofpacket</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>udp_rx_sosi_sop</name>
- <role>startofpacket</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>udp_rx_sosi_valid</name>
- <role>valid</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
</ports>
<assignments>
<assignmentValueMap/>
@@ -31346,71 +16336,26 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>st_clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>st_rst</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>udp_rx_snk_in_xon</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>udp_rx_siso_xon</name>
- <role>xon</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -31422,73 +16367,32 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
- <value>st_clk</value>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
- <value>st_rst</value>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>udp_tx_src_out</name>
- <type>avalon_streaming</type>
- <isStart>true</isStart>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
<ports>
<port>
- <name>udp_tx_siso_ready</name>
- <role>ready</role>
+ <name>csi_system_reset</name>
+ <role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
- <port>
- <name>udp_tx_sosi_data</name>
- <role>data</role>
- <direction>Output</direction>
- <width>40</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>udp_tx_sosi_empty</name>
- <role>empty</role>
- <direction>Output</direction>
- <width>2</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>udp_tx_sosi_eop</name>
- <role>endofpacket</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>udp_tx_sosi_sop</name>
- <role>startofpacket</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>udp_tx_sosi_valid</name>
- <role>valid</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
</ports>
<assignments>
<assignmentValueMap/>
@@ -31497,74 +16401,59 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>st_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>st_rst</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
+ <value>system</value>
</entry>
<entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
<entry>
- <key>maxChannel</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>packetDescription</key>
- <value></value>
+ <key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>udp_tx_src_out_xon</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>udp_tx_siso_xon</name>
- <role>xon</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -31574,11 +16463,9 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>st_clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>st_rst</value>
</entry>
<entry>
<key>prSafe</key>
@@ -31590,667 +16477,92 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>ta2_unb2b_1GbE_mc</className>
+ <className>avs_common_mm</className>
<version>1.0</version>
- <displayName>ta2_unb2b_1GbE_mc</displayName>
+ <displayName>avs_common_mm</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
- <descriptors/>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
- <connPtSystemInfos/>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
</systemInfos>
</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>kernel_snk</name>
- <type>avalon_streaming</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_snk_data</name>
- <role>data</role>
- <direction>Input</direction>
- <width>40</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_snk_ready</name>
- <role>ready</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_snk_valid</name>
- <role>valid</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_src</name>
- <type>avalon_streaming</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_src_data</name>
- <role>data</role>
- <direction>Output</direction>
- <width>40</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_src_ready</name>
- <role>ready</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_src_valid</name>
- <role>valid</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>st_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>st_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>st_rst</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>st_rst</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>st_clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>udp_rx_snk_in</name>
- <type>avalon_streaming</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>udp_rx_siso_ready</name>
- <role>ready</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>udp_rx_sosi_data</name>
- <role>data</role>
- <direction>Input</direction>
- <width>40</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>udp_rx_sosi_empty</name>
- <role>empty</role>
- <direction>Input</direction>
- <width>2</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>udp_rx_sosi_eop</name>
- <role>endofpacket</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>udp_rx_sosi_sop</name>
- <role>startofpacket</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>udp_rx_sosi_valid</name>
- <role>valid</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>st_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>st_rst</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>udp_tx_src_out</name>
- <type>avalon_streaming</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>udp_tx_siso_ready</name>
- <role>ready</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>udp_tx_sosi_data</name>
- <role>data</role>
- <direction>Output</direction>
- <width>40</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>udp_tx_sosi_empty</name>
- <role>empty</role>
- <direction>Output</direction>
- <width>2</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>udp_tx_sosi_eop</name>
- <role>endofpacket</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>udp_tx_sosi_sop</name>
- <role>startofpacket</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>udp_tx_sosi_valid</name>
- <role>valid</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>st_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>st_rst</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>udp_tx_src_out_xon</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>udp_tx_siso_xon</name>
- <role>xon</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>st_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>st_rst</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>udp_rx_snk_in_xon</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>udp_rx_siso_xon</name>
- <role>xon</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>st_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>st_rst</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_ta2_unb2b_1GbE_mc</hdlLibraryName>
+ <hdlLibraryName>board_reg_unb_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_ta2_unb2b_1GbE_mc</fileSetName>
- <fileSetFixedName>board_ta2_unb2b_1GbE_mc</fileSetFixedName>
+ <fileSetName>board_reg_unb_sens</fileSetName>
+ <fileSetFixedName>board_reg_unb_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_ta2_unb2b_1GbE_mc</fileSetName>
- <fileSetFixedName>board_ta2_unb2b_1GbE_mc</fileSetFixedName>
+ <fileSetName>board_reg_unb_sens</fileSetName>
+ <fileSetFixedName>board_reg_unb_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_ta2_unb2b_1GbE_mc</fileSetName>
- <fileSetFixedName>board_ta2_unb2b_1GbE_mc</fileSetFixedName>
+ <fileSetName>board_reg_unb_sens</fileSetName>
+ <fileSetFixedName>board_reg_unb_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_ta2_unb2b_1GbE_mc.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_unb_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ta2_unb2b_40GbE"
+ name="reg_wdi"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -32258,17 +16570,17 @@
<boundary>
<interfaces>
<interface>
- <name>config_clk</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>config_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -32277,28 +16589,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>config_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>config_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -32311,57 +16622,260 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>config_clk</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>kernel_clk</name>
- <type>clock</type>
+ <name>mem</name>
+ <type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
- <name>kernel_clk</name>
- <role>clk</role>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
</ports>
<assignments>
- <assignmentValueMap/>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
<value>0</value>
</entry>
<entry>
- <key>externallyDriven</key>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>kernel_reset</name>
- <type>reset</type>
+ <name>read</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>kernel_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -32374,43 +16888,29 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>kernel_clk</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>kernel_snk</name>
- <type>avalon_streaming</type>
+ <name>readdata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>kernel_snk_data</name>
- <role>data</role>
- <direction>Input</direction>
- <width>264</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_snk_ready</name>
- <role>ready</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_snk_valid</name>
- <role>valid</role>
+ <name>coe_readdata_export</name>
+ <role>export</role>
<direction>Input</direction>
- <width>1</width>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -32420,86 +16920,25 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>kernel_clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>kernel_src</name>
- <type>avalon_streaming</type>
- <isStart>true</isStart>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
<ports>
<port>
- <name>kernel_src_data</name>
- <role>data</role>
- <direction>Output</direction>
- <width>264</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_src_ready</name>
- <role>ready</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_src_valid</name>
- <role>valid</role>
+ <name>coe_reset_export</name>
+ <role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -32513,69 +16952,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>kernel_clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>refclk</name>
+ <name>system</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>clk_ref_r</name>
+ <name>csi_system_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
@@ -32603,17 +16997,17 @@
</parameters>
</interface>
<interface>
- <name>rx_serial_data</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>rx_serial_r</name>
- <role>conduit</role>
+ <name>csi_system_reset</name>
+ <role>reset</role>
<direction>Input</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -32623,25 +17017,23 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>rx_status</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>rx_status</name>
- <role>rx_status</role>
+ <name>coe_write_export</name>
+ <role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -32667,15 +17059,15 @@
</parameters>
</interface>
<interface>
- <name>tx_serial_data</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>tx_serial_r</name>
- <role>conduit</role>
+ <name>coe_writedata_export</name>
+ <role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32701,494 +17093,92 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>ta2_unb2b_40GbE</className>
+ <className>avs_common_mm</className>
<version>1.0</version>
- <displayName>ta2_unb2b_40GbE</displayName>
+ <displayName>avs_common_mm</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
- <descriptors/>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
- <connPtSystemInfos/>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>config_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>config_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>config_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>config_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>config_clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_snk</name>
- <type>avalon_streaming</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_snk_data</name>
- <role>data</role>
- <direction>Input</direction>
- <width>264</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_snk_ready</name>
- <role>ready</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_snk_valid</name>
- <role>valid</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_src</name>
- <type>avalon_streaming</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_src_data</name>
- <role>data</role>
- <direction>Output</direction>
- <width>264</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_src_ready</name>
- <role>ready</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_src_valid</name>
- <role>valid</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>refclk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk_ref_r</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>rx_serial_data</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>rx_serial_r</name>
- <role>conduit</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>rx_status</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>rx_status</name>
- <role>rx_status</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>tx_serial_data</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>tx_serial_r</name>
- <role>conduit</role>
- <direction>Output</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_ta2_unb2b_40GbE</hdlLibraryName>
+ <hdlLibraryName>board_reg_wdi</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_ta2_unb2b_40GbE</fileSetName>
- <fileSetFixedName>board_ta2_unb2b_40GbE</fileSetFixedName>
+ <fileSetName>board_reg_wdi</fileSetName>
+ <fileSetFixedName>board_reg_wdi</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_ta2_unb2b_40GbE</fileSetName>
- <fileSetFixedName>board_ta2_unb2b_40GbE</fileSetFixedName>
+ <fileSetName>board_reg_wdi</fileSetName>
+ <fileSetFixedName>board_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_ta2_unb2b_40GbE</fileSetName>
- <fileSetFixedName>board_ta2_unb2b_40GbE</fileSetFixedName>
+ <fileSetName>board_reg_wdi</fileSetName>
+ <fileSetFixedName>board_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_ta2_unb2b_40GbE.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_wdi.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ta2_unb2b_jesd204b"
+ name="rom_system_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33196,34 +17186,18 @@
<boundary>
<interfaces>
<interface>
- <name>kernel_src</name>
- <type>avalon_streaming</type>
- <isStart>true</isStart>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
<ports>
<port>
- <name>kernel_src_data</name>
- <role>data</role>
+ <name>coe_address_export</name>
+ <role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
- <port>
- <name>kernel_src_ready</name>
- <role>ready</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_src_valid</name>
- <role>valid</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
</ports>
<assignments>
<assignmentValueMap/>
@@ -33232,104 +17206,26 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>kernel_clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>config_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>config_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -33344,38 +17240,11 @@
<key>associatedClock</key>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -33386,31 +17255,31 @@
<isStart>false</isStart>
<ports>
<port>
- <name>jesd204b_mosi_address</name>
+ <name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>jesd204b_mosi_wrdata</name>
- <role>writedata</role>
+ <name>avs_mem_write</name>
+ <role>write</role>
<direction>Input</direction>
- <width>32</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>jesd204b_mosi_wr</name>
- <role>write</role>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
<direction>Input</direction>
- <width>1</width>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>jesd204b_mosi_rd</name>
+ <name>avs_mem_read</name>
<role>read</role>
<direction>Input</direction>
<width>1</width>
@@ -33418,21 +17287,13 @@
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>jesd204b_miso_rddata</name>
+ <name>avs_mem_readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
- <port>
- <name>jesd204b_miso_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
</ports>
<assignments>
<assignmentValueMap>
@@ -33466,7 +17327,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>4096</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -33478,11 +17339,11 @@
</entry>
<entry>
<key>associatedClock</key>
- <value>config_clk</value>
+ <value>system</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>config_reset</value>
+ <value>system_reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
@@ -33573,11 +17434,11 @@
</entry>
<entry>
<key>readWaitStates</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>readWaitTime</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
@@ -33596,41 +17457,105 @@
<value>Cycles</value>
</entry>
<entry>
- <key>transparentBridge</key>
- <value>false</value>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>wellBehavedWaitrequest</key>
+ <key>prSafe</key>
<value>false</value>
</entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>config_clk</name>
- <type>clock</type>
+ <name>reset</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>config_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -33642,26 +17567,25 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>jesd204b_refclk</name>
+ <name>system</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>jesd204b_refclk</name>
+ <name>csi_system_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
@@ -33689,13 +17613,13 @@
</parameters>
</interface>
<interface>
- <name>jesd204b_sysref</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>jesd204b_sysref</name>
- <role>conduit</role>
+ <name>csi_system_reset</name>
+ <role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -33709,31 +17633,27 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>jesd204b_refclk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
+ <value>system</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>jesd204b_sync_n</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>jesd204b_sync_n_arr</name>
- <role>conduit</role>
+ <name>coe_write_export</name>
+ <role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -33743,11 +17663,9 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>jesd204b_refclk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>kernel_reset</value>
</entry>
<entry>
<key>prSafe</key>
@@ -33757,15 +17675,15 @@
</parameters>
</interface>
<interface>
- <name>serial_rx_arr</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>serial_rx_arr</name>
- <role>conduit</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33777,11 +17695,9 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>kernel_clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>kernel_reset</value>
</entry>
<entry>
<key>prSafe</key>
@@ -33793,12 +17709,20 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>ta2_unb2b_jesd204b</className>
+ <className>avs_common_mm</className>
<version>1.0</version>
- <displayName>ta2_unb2b_jesd204b</displayName>
+ <displayName>avs_common_mm</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
- <descriptors/>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
@@ -33809,647 +17733,61 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>10</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>kernel_src</name>
- <type>avalon_streaming</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_src_data</name>
- <role>data</role>
- <direction>Output</direction>
- <width>16</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_src_ready</name>
- <role>ready</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_src_valid</name>
- <role>valid</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>config_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>config_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>jesd204b_mosi_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>8</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>jesd204b_mosi_wrdata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>jesd204b_mosi_wr</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>jesd204b_mosi_rd</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>jesd204b_miso_rddata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>jesd204b_miso_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>1024</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>config_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>config_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>config_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>config_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>jesd204b_refclk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>jesd204b_refclk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>jesd204b_sysref</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>jesd204b_sysref</name>
- <role>conduit</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>jesd204b_refclk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>jesd204b_sync_n</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>jesd204b_sync_n_arr</name>
- <role>conduit</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>jesd204b_refclk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>serial_rx_arr</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>serial_rx_arr</name>
- <role>conduit</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>12</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_ta2_unb2b_jesd204b</hdlLibraryName>
+ <hdlLibraryName>board_rom_system_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_ta2_unb2b_jesd204b</fileSetName>
- <fileSetFixedName>board_ta2_unb2b_jesd204b</fileSetFixedName>
+ <fileSetName>board_rom_system_info</fileSetName>
+ <fileSetFixedName>board_rom_system_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_ta2_unb2b_jesd204b</fileSetName>
- <fileSetFixedName>board_ta2_unb2b_jesd204b</fileSetFixedName>
+ <fileSetName>board_rom_system_info</fileSetName>
+ <fileSetFixedName>board_rom_system_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_ta2_unb2b_jesd204b</fileSetName>
- <fileSetFixedName>board_ta2_unb2b_jesd204b</fileSetFixedName>
+ <fileSetName>board_rom_system_info</fileSetName>
+ <fileSetFixedName>board_rom_system_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_ta2_unb2b_jesd204b.ip</parameter>
+ <parameter name="logicalView">ip/board/board_rom_system_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -34561,890 +17899,255 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>s1</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>16</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>16</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>chipselect</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>write_n</name>
- <role>write_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isTimerDevice</key>
- <value>1</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>NATIVE</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
+ <key>associatedClock</key>
+ <value>clk</value>
</entry>
<entry>
- <key>transparentBridge</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>s1</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>16</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>16</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>chipselect</name>
+ <role>chipselect</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>write_n</name>
+ <role>write_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
<entry>
- <key>waitrequestAllowance</key>
+ <key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
</entry>
<entry>
- <key>writeLatency</key>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
- <key>writeWaitStates</key>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
<entry>
- <key>writeWaitTime</key>
- <value>0</value>
+ <key>embeddedsw.configuration.isTimerDevice</key>
+ <value>1</value>
</entry>
- </parameterValueMap>
- </parameters>
- <cmsisInfo>
- <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
-<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
- <peripherals>
- <peripheral>
- <name>altera_avalon_timer</name><baseAddress>0x00000000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>16</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>status</name>
- <displayName>Status</displayName>
- <description>The status register has two defined bits. TO (timeout), RUN</description>
- <addressOffset>0x0</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffff</resetMask>
- <fields>
- <field><name>TO</name>
- <description>The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <readAction>clear</readAction>
- </field>
- <field><name>RUN</name>
- <description>The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by
- a write operation to the status register.</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>Reserved</name>
- <description>Reserved</description>
- <bitOffset>2</bitOffset>
- <bitWidth>14</bitWidth>
- <access>read-write</access>
- <parameters>
- <parameter>
- <name>Reserved</name>
- <value>true</value>
- </parameter>
- </parameters>
- </field>
- </fields>
- </register>
- <register>
- <name>control</name>
- <description>The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP</description>
- <addressOffset>0x1</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <reset>
- <value>0x0</value>
- </reset>
- <field>
- <name>ITO</name>
- <description>If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CONT</name>
- <description>The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>START</name>
- <description>Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>STOP</name>
- <description>Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>Reserved</name>
- <description>Reserved</description>
- <bitOffset>4</bitOffset>
- <bitWidth>12</bitWidth>
- <access>read-write</access>
- <parameters>
- <parameter>
- <name>Reserved</name>
- <value>true</value>
- </parameter>
- </parameters>
- </field>
- </register>
- <register>
- <name>${period_name_0}</name>
- <description>The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.</description>
- <addressOffset>0x2</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>${period_name_0_reset_value}</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${period_name_1}</name>
- <description></description>
- <addressOffset>0x3</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>${period_name_1_reset_value}</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${period_snap_0}</name>
- <description></description>
- <addressOffset>0x4</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>${period_snap_0_reset_value}</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${period_snap_1}</name>
- <description></description>
- <addressOffset>0x5</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>${period_snap_1_reset_value}</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${snap_0}</name>
- <description>A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.</description>
- <addressOffset>0x6</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${snap_1}</name>
- <description></description>
- <addressOffset>0x7</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${snap_2}</name>
- <description></description>
- <addressOffset>0x8</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${snap_3}</name>
- <description></description>
- <addressOffset>0x9</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device> </cmsisSrcFileContents>
- <addressGroup></addressGroup>
- <cmsisVars>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
<entry>
- <key>period_name_1_reset_value</key>
- <value>0x1</value>
+ <key>addressAlignment</key>
+ <value>NATIVE</value>
</entry>
<entry>
- <key>snap_0</key>
- <value>Reserved</value>
+ <key>addressGroup</key>
+ <value>0</value>
</entry>
<entry>
- <key>period_name_0_reset_value</key>
- <value>0x869f</value>
+ <key>addressSpan</key>
+ <value>8</value>
</entry>
<entry>
- <key>snap_2</key>
- <value>Reserved</value>
+ <key>addressUnits</key>
+ <value>WORDS</value>
</entry>
<entry>
- <key>snap_1</key>
- <value>Reserved</value>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
</entry>
<entry>
- <key>snap_3</key>
- <value>Reserved</value>
+ <key>associatedClock</key>
+ <value>clk</value>
</entry>
<entry>
- <key>period_name_0</key>
- <value>periodl</value>
+ <key>associatedReset</key>
+ <value>reset</value>
</entry>
<entry>
- <key>period_name_1</key>
- <value>periodh</value>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
</entry>
<entry>
- <key>period_snap_1</key>
- <value>snaph</value>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
</entry>
<entry>
- <key>period_snap_1_reset_value</key>
- <value>0x0</value>
+ <key>bridgesToMaster</key>
</entry>
<entry>
- <key>period_snap_0_reset_value</key>
- <value>0x0</value>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
</entry>
<entry>
- <key>period_snap_0</key>
- <value>snapl</value>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
</entry>
- </cmsisVars>
- </cmsisInfo>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>altera_avalon_timer</className>
- <version>19.1</version>
- <displayName>Interval Timer Intel FPGA IP</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>0</parameterDefaultValue>
- <parameterName>systemFrequency</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>clk</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>clk</key>
- <value>
- <connectionPointName>clk</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
<entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
</entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>s1</key>
- <value>
- <connectionPointName>s1</connectionPointName>
- <suppliedSystemInfos>
<entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='s1' start='0x0' end='0x20' datawidth='16' /></address-map></value>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
</entry>
<entry>
- <key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <key>holdTime</key>
+ <value>0</value>
</entry>
<entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>16</value>
+ <key>interleaveBursts</key>
+ <value>false</value>
</entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>irq</name>
- <type>interrupt</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>irq</name>
- <role>irq</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- <value>timer_0.s1</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bridgedReceiverOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToReceiver</key>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>s1</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>16</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>16</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>chipselect</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>write_n</name>
- <role>write_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isTimerDevice</key>
- <value>1</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>NATIVE</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- <cmsisInfo>
- <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ <cmsisInfo>
+ <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
<peripherals>
<peripheral>
@@ -35621,61 +18324,116 @@
</peripheral>
</peripherals>
</device> </cmsisSrcFileContents>
- <addressGroup></addressGroup>
- <cmsisVars>
- <entry>
- <key>period_name_1_reset_value</key>
- <value>0x1</value>
- </entry>
- <entry>
- <key>snap_0</key>
- <value>Reserved</value>
- </entry>
- <entry>
- <key>period_name_0_reset_value</key>
- <value>0x869f</value>
- </entry>
- <entry>
- <key>snap_2</key>
- <value>Reserved</value>
- </entry>
- <entry>
- <key>snap_1</key>
- <value>Reserved</value>
- </entry>
- <entry>
- <key>snap_3</key>
- <value>Reserved</value>
- </entry>
- <entry>
- <key>period_name_0</key>
- <value>periodl</value>
- </entry>
- <entry>
- <key>period_name_1</key>
- <value>periodh</value>
- </entry>
- <entry>
- <key>period_snap_1</key>
- <value>snaph</value>
- </entry>
- <entry>
- <key>period_snap_1_reset_value</key>
- <value>0x0</value>
- </entry>
- <entry>
- <key>period_snap_0_reset_value</key>
- <value>0x0</value>
- </entry>
- <entry>
- <key>period_snap_0</key>
- <value>snapl</value>
- </entry>
- </cmsisVars>
- </cmsisInfo>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
+ <addressGroup></addressGroup>
+ <cmsisVars>
+ <entry>
+ <key>period_name_1_reset_value</key>
+ <value>0x1</value>
+ </entry>
+ <entry>
+ <key>snap_0</key>
+ <value>Reserved</value>
+ </entry>
+ <entry>
+ <key>period_name_0_reset_value</key>
+ <value>0x869f</value>
+ </entry>
+ <entry>
+ <key>snap_2</key>
+ <value>Reserved</value>
+ </entry>
+ <entry>
+ <key>snap_1</key>
+ <value>Reserved</value>
+ </entry>
+ <entry>
+ <key>snap_3</key>
+ <value>Reserved</value>
+ </entry>
+ <entry>
+ <key>period_name_0</key>
+ <value>periodl</value>
+ </entry>
+ <entry>
+ <key>period_name_1</key>
+ <value>periodh</value>
+ </entry>
+ <entry>
+ <key>period_snap_1</key>
+ <value>snaph</value>
+ </entry>
+ <entry>
+ <key>period_snap_1_reset_value</key>
+ <value>0x0</value>
+ </entry>
+ <entry>
+ <key>period_snap_0_reset_value</key>
+ <value>0x0</value>
+ </entry>
+ <entry>
+ <key>period_snap_0</key>
+ <value>snapl</value>
+ </entry>
+ </cmsisVars>
+ </cmsisInfo>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>altera_avalon_timer</className>
+ <version>18.0</version>
+ <displayName>Interval Timer Intel FPGA IP</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>0</parameterDefaultValue>
+ <parameterName>systemFrequency</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>clk</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>clk</key>
+ <value>
+ <connectionPointName>clk</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>s1</key>
+ <value>
+ <connectionPointName>s1</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='s1' start='0x0' end='0x20' datawidth='16' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>5</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>16</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
<hdlLibraryName>board_timer_0</hdlLibraryName>
<fileSets>
@@ -35761,959 +18519,543 @@
</module>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x03b8" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="kernel_clk_gen.ctrl">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x9000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="kernel_interface.ctrl">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x4000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="cpu_0.debug_mem_slave">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3800" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="reg_unb_sens.mem">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0200" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="rom_system_info.mem">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x1000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="pio_system_info.mem">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x03b0" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="reg_wdi.mem">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0360" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0340" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x03a8" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x03a0" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0398" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0390" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0320" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="reg_unb_pmbus.mem">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0100" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00c0" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
- end="ta2_unb2b_jesd204b.mem">
- <parameter name="arbitrationPriority" value="1" />
+ end="reg_ta2_unb2b_jesd204b.mem">
<parameter name="baseAddress" value="0x0400" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="avs_eth_0.mms_ram">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x8000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0080" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="avs_eth_0.mms_tse">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x2000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="onchip_memory2_0.s1">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00020000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="pio_wdi.s1">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0380" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.data_master"
end="timer_0.s1">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0300" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.instruction_master"
end="cpu_0.debug_mem_slave">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3800" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
<connection
kind="avalon"
- version="19.2"
+ version="18.0"
start="cpu_0.instruction_master"
end="onchip_memory2_0.s1">
- <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00020000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
- <connection kind="clock" version="19.2" start="clk_0.clk" end="jtag_uart_0.clk" />
- <connection kind="clock" version="19.2" start="clk_0.clk" end="pio_wdi.clk" />
- <connection kind="clock" version="19.2" start="clk_0.clk" end="cpu_0.clk" />
- <connection kind="clock" version="19.2" start="clk_0.clk" end="timer_0.clk" />
+ <connection kind="clock" version="18.0" start="clk_0.clk" end="jtag_uart_0.clk" />
+ <connection kind="clock" version="18.0" start="clk_0.clk" end="pio_wdi.clk" />
+ <connection kind="clock" version="18.0" start="clk_0.clk" end="cpu_0.clk" />
+ <connection kind="clock" version="18.0" start="clk_0.clk" end="timer_0.clk" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
start="clk_0.clk"
end="kernel_interface.clk" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
start="clk_0.clk"
end="kernel_clk_gen.clk" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
start="clk_0.clk"
end="onchip_memory2_0.clk1" />
<connection
kind="clock"
- version="19.2"
- start="clk_0.clk"
- end="ta2_unb2b_40GbE.config_clk" />
- <connection
- kind="clock"
- version="19.2"
- start="clk_0.clk"
- end="ta2_unb2b_jesd204b.config_clk" />
- <connection
- kind="clock"
- version="19.2"
+ version="18.0"
start="clk_0.clk"
end="kernel_clk_gen.kernel_pll_refclk" />
- <connection kind="clock" version="19.2" start="clk_0.clk" end="avs_eth_0.mm" />
+ <connection kind="clock" version="18.0" start="clk_0.clk" end="avs_eth_0.mm" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
start="clk_0.clk"
end="reg_unb_sens.system" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
start="clk_0.clk"
end="rom_system_info.system" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
start="clk_0.clk"
end="pio_system_info.system" />
- <connection kind="clock" version="19.2" start="clk_0.clk" end="pio_pps.system" />
- <connection kind="clock" version="19.2" start="clk_0.clk" end="reg_wdi.system" />
- <connection kind="clock" version="19.2" start="clk_0.clk" end="reg_remu.system" />
- <connection kind="clock" version="19.2" start="clk_0.clk" end="reg_epcs.system" />
+ <connection kind="clock" version="18.0" start="clk_0.clk" end="pio_pps.system" />
+ <connection kind="clock" version="18.0" start="clk_0.clk" end="reg_wdi.system" />
+ <connection kind="clock" version="18.0" start="clk_0.clk" end="reg_remu.system" />
+ <connection kind="clock" version="18.0" start="clk_0.clk" end="reg_epcs.system" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
start="clk_0.clk"
end="reg_dpmm_ctrl.system" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
start="clk_0.clk"
end="reg_mmdp_data.system" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
start="clk_0.clk"
end="reg_dpmm_data.system" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
start="clk_0.clk"
end="reg_mmdp_ctrl.system" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
start="clk_0.clk"
end="reg_fpga_temp_sens.system" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
start="clk_0.clk"
end="reg_unb_pmbus.system" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
start="clk_0.clk"
end="reg_fpga_voltage_sens.system" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_ta2_unb2b_jesd204b.system" />
+ <connection
+ kind="clock"
+ version="18.0"
start="kernel_clk_gen.kernel_clk"
end="board_onchip_memory.clk1" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
start="kernel_clk_gen.kernel_clk"
end="kernel_clk_export.clk_in" />
<connection
kind="clock"
- version="19.2"
+ version="18.0"
start="kernel_clk_gen.kernel_clk"
end="kernel_interface.kernel_clk" />
- <connection
- kind="clock"
- version="19.2"
- start="kernel_clk_gen.kernel_clk"
- end="ta2_unb2b_40GbE.kernel_clk" />
- <connection
- kind="clock"
- version="19.2"
- start="kernel_clk_gen.kernel_clk"
- end="ta2_unb2b_10GbE.kernel_clk" />
- <connection
- kind="clock"
- version="19.2"
- start="kernel_clk_gen.kernel_clk"
- end="ta2_unb2b_1GbE_mc.kernel_clk" />
- <connection
- kind="clock"
- version="19.2"
- start="kernel_clk_gen.kernel_clk"
- end="ta2_unb2b_jesd204b.kernel_clk" />
<connection
kind="interrupt"
- version="19.2"
+ version="18.0"
start="cpu_0.irq"
- end="avs_eth_0.interrupt">
- <parameter name="irqNumber" value="0" />
- </connection>
+ end="avs_eth_0.interrupt" />
<connection
kind="interrupt"
- version="19.2"
+ version="18.0"
start="cpu_0.irq"
end="jtag_uart_0.irq">
<parameter name="irqNumber" value="1" />
</connection>
- <connection kind="interrupt" version="19.2" start="cpu_0.irq" end="timer_0.irq">
+ <connection kind="interrupt" version="18.0" start="cpu_0.irq" end="timer_0.irq">
<parameter name="irqNumber" value="2" />
</connection>
<connection
kind="reset"
- version="19.2"
- start="clk_0.clk_reset"
- end="ta2_unb2b_40GbE.config_reset" />
- <connection
- kind="reset"
- version="19.2"
- start="clk_0.clk_reset"
- end="ta2_unb2b_10GbE.config_reset" />
- <connection
- kind="reset"
- version="19.2"
- start="clk_0.clk_reset"
- end="ta2_unb2b_jesd204b.config_reset" />
- <connection
- kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="avs_eth_0.mm_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="jtag_uart_0.reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="pio_wdi.reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="timer_0.reset" />
- <connection kind="reset" version="19.2" start="clk_0.clk_reset" end="cpu_0.reset" />
+ <connection kind="reset" version="18.0" start="clk_0.clk_reset" end="cpu_0.reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="kernel_interface.reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="kernel_clk_gen.reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="onchip_memory2_0.reset1" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="reg_unb_sens.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="rom_system_info.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="pio_system_info.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="pio_pps.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="reg_wdi.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="reg_remu.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="reg_epcs.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="reg_dpmm_ctrl.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="reg_mmdp_data.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="reg_mmdp_ctrl.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="reg_dpmm_data.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="reg_fpga_temp_sens.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="reg_unb_pmbus.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="clk_0.clk_reset"
end="reg_fpga_voltage_sens.system_reset" />
<connection
kind="reset"
- version="19.2"
- start="cpu_0.debug_reset_request"
- end="ta2_unb2b_40GbE.config_reset" />
- <connection
- kind="reset"
- version="19.2"
- start="cpu_0.debug_reset_request"
- end="ta2_unb2b_10GbE.config_reset" />
- <connection
- kind="reset"
- version="19.2"
- start="cpu_0.debug_reset_request"
- end="ta2_unb2b_jesd204b.config_reset" />
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_ta2_unb2b_jesd204b.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="avs_eth_0.mm_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="jtag_uart_0.reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="pio_wdi.reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="timer_0.reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="cpu_0.reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="kernel_clk_gen.reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="kernel_interface.reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="onchip_memory2_0.reset1" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="reg_unb_sens.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="rom_system_info.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="pio_system_info.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="pio_pps.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="reg_wdi.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="reg_remu.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="reg_epcs.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="reg_dpmm_ctrl.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="reg_mmdp_data.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="reg_dpmm_data.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="reg_mmdp_ctrl.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="reg_fpga_temp_sens.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="reg_unb_pmbus.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="cpu_0.debug_reset_request"
end="reg_fpga_voltage_sens.system_reset" />
<connection
kind="reset"
- version="19.2"
- start="kernel_interface.kernel_reset"
- end="kernel_clk_export.clk_in_reset" />
- <connection
- kind="reset"
- version="19.2"
- start="kernel_interface.kernel_reset"
- end="ta2_unb2b_40GbE.kernel_reset" />
- <connection
- kind="reset"
- version="19.2"
- start="kernel_interface.kernel_reset"
- end="ta2_unb2b_10GbE.kernel_reset" />
- <connection
- kind="reset"
- version="19.2"
- start="kernel_interface.kernel_reset"
- end="ta2_unb2b_1GbE_mc.kernel_reset" />
+ version="18.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_ta2_unb2b_jesd204b.system_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="kernel_interface.kernel_reset"
- end="ta2_unb2b_jesd204b.kernel_reset" />
+ end="kernel_clk_export.clk_in_reset" />
<connection
kind="reset"
- version="19.2"
+ version="18.0"
start="kernel_interface.kernel_reset"
end="board_onchip_memory.reset1" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="0" />
</system>
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board_spec.xml b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board_spec.xml
index 05341e43b5d9b5bbed063fb83ae6ed30220ce45b..e77390839e1c1abac8aea72b159ab7991039714f 100755
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board_spec.xml
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board_spec.xml
@@ -31,6 +31,13 @@
<interface name="board" port="kernel_stream_snk_10GbE" type="streamsink" width="72" chan_id="kernel_output_10GbE"/>
<interface name="board" port="kernel_stream_src_40GbE" type="streamsource" width="264" chan_id="kernel_input_40GbE"/>
<interface name="board" port="kernel_stream_snk_40GbE" type="streamsink" width="264" chan_id="kernel_output_40GbE"/>
+
+ <!-- Ring interface, ring_0 is to PN to the left. Ring_1 is to PN to the right -->
+ <interface name="board" port="kernel_stream_src_40GbE_ring_0" type="streamsource" width="264" chan_id="kernel_input_40GbE_ring_0"/>
+ <interface name="board" port="kernel_stream_snk_40GbE_ring_0" type="streamsink" width="264" chan_id="kernel_output_40GbE_ring_0"/>
+ <interface name="board" port="kernel_stream_src_40GbE_ring_1" type="streamsource" width="264" chan_id="kernel_input_40GbE_ring_1"/>
+ <interface name="board" port="kernel_stream_snk_40GbE_ring_1" type="streamsink" width="264" chan_id="kernel_output_40GbE_ring_1"/>
+
<interface name="board" port="kernel_stream_src_ADC" type="streamsource" width="16" chan_id="kernel_input_ADC"/>
</channels>
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/flat.qsf b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/flat.qsf
index 065c54d3aace1b86558a8a4d1edd486ad399c9dd..51a771c57898344daa7b8d20fd529723bf01c449 100755
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/flat.qsf
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/flat.qsf
@@ -492,7 +492,202 @@ set_location_assignment PIN_U12 -to JESD204B_SYNC[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[0]
-set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_40GbE.ip
-set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_10GbE.ip
-set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_1GbE_mc.ip
-set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_jesd204b.ip
+set_location_assignment PIN_AP40 -to RING_0_RX[0]
+set_location_assignment PIN_AR38 -to RING_0_RX[1]
+set_location_assignment PIN_AT40 -to RING_0_RX[2]
+set_location_assignment PIN_AU38 -to RING_0_RX[3]
+set_location_assignment PIN_AP44 -to RING_0_TX[0]
+set_location_assignment PIN_AR42 -to RING_0_TX[1]
+set_location_assignment PIN_AT44 -to RING_0_TX[2]
+set_location_assignment PIN_AU42 -to RING_0_TX[3]
+set_location_assignment PIN_H40 -to RING_1_RX[0]
+set_location_assignment PIN_J38 -to RING_1_RX[1]
+set_location_assignment PIN_F40 -to RING_1_RX[2]
+set_location_assignment PIN_G38 -to RING_1_RX[3]
+set_location_assignment PIN_H44 -to RING_1_TX[0]
+set_location_assignment PIN_J42 -to RING_1_TX[1]
+set_location_assignment PIN_G42 -to RING_1_TX[2]
+set_location_assignment PIN_F44 -to RING_1_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[3]
+
+
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[3]
+
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[3]
+
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[3]
+
+
+set_global_assignment -name IP_FILE ip/board/board_reg_ta2_unb2b_jesd204b.ip
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/hdllib.cfg b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..5e76341e8e396e1f7948a7f4199100892999609b
--- /dev/null
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/hdllib.cfg
@@ -0,0 +1,37 @@
+hdl_lib_name = ta2_unb2b_top
+hdl_library_clause_name = ta2_unb2b_top_lib
+hdl_lib_uses_synth = common technology dp unb2b_board ta2_unb2b_40GbE ta2_unb2b_10GbE ta2_unb2b_1GbE_mc ta2_unb2b_jesd204b
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+hdl_lib_include_ip =
+
+synth_files =
+ top_components_pkg.vhd
+ ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
+ ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
+ ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd
+ ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
+ top.vhd
+test_bench_files =
+
+regression_test_vhdl =
+
+[modelsim_project_file]
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_sdc_files =
+ $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+
+
+quartus_vhdl_files =
+
+quartus_qip_files =
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_cpu_0.ip b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_cpu_0.ip
index 7576f2745d01d2071f20ed763182f7fa8f5a1a87..3b9742fd6ba2911dfe92d25b03eed4c2d7c570b2 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_cpu_0.ip
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x8000' end='0x9000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x9000' end='0xA000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='reg_ta2_unb2b_jesd204b.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x8000' end='0x9000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x9000' end='0xA000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='reg_ta2_unb2b_jesd204b.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_ta2_unb2b_1GbE_mc.ip b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_reg_ta2_unb2b_jesd204b.ip
similarity index 53%
rename from applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_ta2_unb2b_1GbE_mc.ip
rename to applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_reg_ta2_unb2b_jesd204b.ip
index c5df677de7de0ed003fda56bd16c6ef0650aac4e..b4884d2e29f0f16684aa11a9b65e919e267eea17 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_ta2_unb2b_1GbE_mc.ip
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_reg_ta2_unb2b_jesd204b.ip
@@ -1,149 +1,258 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
- <spirit:vendor>Altera Corporation</spirit:vendor>
- <spirit:library>board_ta2_unb2b_1GbE_mc</spirit:library>
- <spirit:name>board_ta2_unb2b_1GbE_mc</spirit:name>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>board_reg_ta2_unb2b_jesd204b</spirit:library>
+ <spirit:name>board_reg_ta2_unb2b_jesd204b</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
- <spirit:name>kernel_clk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
<spirit:slave></spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>clk</spirit:name>
+ <spirit:name>export</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>kernel_clk</spirit:name>
+ <spirit:name>coe_address_export</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
- <spirit:name>clockRate</spirit:name>
- <spirit:displayName>Clock rate</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>externallyDriven</spirit:name>
- <spirit:displayName>Externally driven</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>ptfSchematicName</spirit:name>
- <spirit:displayName>PTF schematic name</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>kernel_reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
<spirit:slave></spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>reset</spirit:name>
+ <spirit:name>export</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>kernel_reset</spirit:name>
+ <spirit:name>coe_clk_export</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">kernel_clk</spirit:value>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>synchronousEdges</spirit:name>
- <spirit:displayName>Synchronous edges</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>kernel_snk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon_streaming" spirit:version="18.0"></spirit:busType>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
<spirit:slave></spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>data</spirit:name>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>kernel_snk_data</spirit:name>
+ <spirit:name>avs_mem_read</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>ready</spirit:name>
+ <spirit:name>readdata</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>kernel_snk_ready</spirit:name>
+ <spirit:name>avs_mem_readdata</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>valid</spirit:name>
+ <spirit:name>waitrequest</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>kernel_snk_valid</spirit:name>
+ <spirit:name>avs_mem_waitrequest</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">1024</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">kernel_clk</spirit:value>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">kernel_reset</spirit:value>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>beatsPerCycle</spirit:name>
- <spirit:displayName>Beats Per Cycle</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="beatsPerCycle">1</spirit:value>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>dataBitsPerSymbol</spirit:name>
- <spirit:displayName>Data bits per symbol</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="dataBitsPerSymbol">8</spirit:value>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>emptyWithinPacket</spirit:name>
- <spirit:displayName>emptyWithinPacket</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="emptyWithinPacket">false</spirit:value>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>errorDescriptor</spirit:name>
- <spirit:displayName>Error descriptor</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="errorDescriptor"></spirit:value>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>firstSymbolInHighOrderBits</spirit:name>
- <spirit:displayName>First Symbol In High-Order Bits</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="firstSymbolInHighOrderBits">true</spirit:value>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>highOrderSymbolAtMSB</spirit:name>
- <spirit:displayName>highOrderSymbolAtMSB</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="highOrderSymbolAtMSB">false</spirit:value>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>maxChannel</spirit:name>
- <spirit:displayName>Maximum channel</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maxChannel">0</spirit:value>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>packetDescription</spirit:name>
- <spirit:displayName>Packet description </spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="packetDescription"></spirit:value>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>prSafe</spirit:name>
@@ -151,49 +260,110 @@
<spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>readyAllowance</spirit:name>
- <spirit:displayName>Ready allowance</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyAllowance">0</spirit:value>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>readyLatency</spirit:name>
- <spirit:displayName>Ready latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyLatency">0</spirit:value>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>symbolsPerBeat</spirit:name>
- <spirit:displayName>Symbols per beat </spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="symbolsPerBeat">1</spirit:value>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
</spirit:parameter>
</spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>kernel_src</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon_streaming" spirit:version="18.0"></spirit:busType>
- <spirit:master></spirit:master>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>data</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_src_data</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ready</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_src_ready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>valid</spirit:name>
+ <spirit:name>export</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>kernel_src_valid</spirit:name>
+ <spirit:name>coe_read_export</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
@@ -201,77 +371,86 @@
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
<spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">kernel_clk</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>associatedReset</spirit:name>
<spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">kernel_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>beatsPerCycle</spirit:name>
- <spirit:displayName>Beats Per Cycle</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="beatsPerCycle">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>dataBitsPerSymbol</spirit:name>
- <spirit:displayName>Data bits per symbol</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="dataBitsPerSymbol">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>emptyWithinPacket</spirit:name>
- <spirit:displayName>emptyWithinPacket</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="emptyWithinPacket">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>errorDescriptor</spirit:name>
- <spirit:displayName>Error descriptor</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="errorDescriptor"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>firstSymbolInHighOrderBits</spirit:name>
- <spirit:displayName>First Symbol In High-Order Bits</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="firstSymbolInHighOrderBits">true</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>highOrderSymbolAtMSB</spirit:name>
- <spirit:displayName>highOrderSymbolAtMSB</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="highOrderSymbolAtMSB">false</spirit:value>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
</spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
<spirit:parameter>
- <spirit:name>maxChannel</spirit:name>
- <spirit:displayName>Maximum channel</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maxChannel">0</spirit:value>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>packetDescription</spirit:name>
- <spirit:displayName>Packet description </spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="packetDescription"></spirit:value>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>prSafe</spirit:name>
<spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
<spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
</spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
<spirit:parameter>
- <spirit:name>readyAllowance</spirit:name>
- <spirit:displayName>Ready allowance</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyAllowance">0</spirit:value>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>readyLatency</spirit:name>
- <spirit:displayName>Ready latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyLatency">0</spirit:value>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>symbolsPerBeat</spirit:name>
- <spirit:displayName>Symbols per beat </spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="symbolsPerBeat">1</spirit:value>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>st_clk</spirit:name>
+ <spirit:name>system</spirit:name>
<spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
<spirit:slave></spirit:slave>
<spirit:portMaps>
@@ -280,7 +459,7 @@
<spirit:name>clk</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>st_clk</spirit:name>
+ <spirit:name>csi_system_clk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
@@ -303,7 +482,7 @@
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>st_rst</spirit:name>
+ <spirit:name>system_reset</spirit:name>
<spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
<spirit:slave></spirit:slave>
<spirit:portMaps>
@@ -312,7 +491,7 @@
<spirit:name>reset</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>st_rst</spirit:name>
+ <spirit:name>csi_system_reset</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
@@ -320,7 +499,7 @@
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
<spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">st_clk</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>synchronousEdges</spirit:name>
@@ -330,56 +509,16 @@
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>udp_rx_snk_in</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon_streaming" spirit:version="18.0"></spirit:busType>
+ <spirit:name>waitrequest</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
<spirit:slave></spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>ready</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>udp_rx_siso_ready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>data</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>udp_rx_sosi_data</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>empty</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>udp_rx_sosi_empty</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>endofpacket</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>udp_rx_sosi_eop</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>startofpacket</spirit:name>
+ <spirit:name>export</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>udp_rx_sosi_sop</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>valid</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>udp_rx_sosi_valid</spirit:name>
+ <spirit:name>coe_waitrequest_export</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
@@ -387,86 +526,31 @@
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
<spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">st_clk</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>associatedReset</spirit:name>
<spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">st_rst</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>beatsPerCycle</spirit:name>
- <spirit:displayName>Beats Per Cycle</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="beatsPerCycle">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>dataBitsPerSymbol</spirit:name>
- <spirit:displayName>Data bits per symbol</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="dataBitsPerSymbol">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>emptyWithinPacket</spirit:name>
- <spirit:displayName>emptyWithinPacket</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="emptyWithinPacket">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>errorDescriptor</spirit:name>
- <spirit:displayName>Error descriptor</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="errorDescriptor"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>firstSymbolInHighOrderBits</spirit:name>
- <spirit:displayName>First Symbol In High-Order Bits</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="firstSymbolInHighOrderBits">true</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>highOrderSymbolAtMSB</spirit:name>
- <spirit:displayName>highOrderSymbolAtMSB</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="highOrderSymbolAtMSB">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maxChannel</spirit:name>
- <spirit:displayName>Maximum channel</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maxChannel">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>packetDescription</spirit:name>
- <spirit:displayName>Packet description </spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="packetDescription"></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>prSafe</spirit:name>
<spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
<spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
</spirit:parameter>
- <spirit:parameter>
- <spirit:name>readyAllowance</spirit:name>
- <spirit:displayName>Ready allowance</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyAllowance">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readyLatency</spirit:name>
- <spirit:displayName>Ready latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyLatency">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>symbolsPerBeat</spirit:name>
- <spirit:displayName>Symbols per beat </spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="symbolsPerBeat">1</spirit:value>
- </spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>udp_rx_snk_in_xon</spirit:name>
+ <spirit:name>write</spirit:name>
<spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
<spirit:slave></spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>xon</spirit:name>
+ <spirit:name>export</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>udp_rx_siso_xon</spirit:name>
+ <spirit:name>coe_write_export</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
@@ -474,12 +558,12 @@
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
<spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">st_clk</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>associatedReset</spirit:name>
<spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">st_rst</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>prSafe</spirit:name>
@@ -489,143 +573,16 @@
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>udp_tx_src_out</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon_streaming" spirit:version="18.0"></spirit:busType>
- <spirit:master></spirit:master>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>ready</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>udp_tx_siso_ready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>data</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>udp_tx_sosi_data</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>empty</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>udp_tx_sosi_empty</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>endofpacket</spirit:name>
+ <spirit:name>export</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>udp_tx_sosi_eop</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>startofpacket</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>udp_tx_sosi_sop</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>valid</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>udp_tx_sosi_valid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">st_clk</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">st_rst</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>beatsPerCycle</spirit:name>
- <spirit:displayName>Beats Per Cycle</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="beatsPerCycle">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>dataBitsPerSymbol</spirit:name>
- <spirit:displayName>Data bits per symbol</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="dataBitsPerSymbol">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>emptyWithinPacket</spirit:name>
- <spirit:displayName>emptyWithinPacket</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="emptyWithinPacket">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>errorDescriptor</spirit:name>
- <spirit:displayName>Error descriptor</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="errorDescriptor"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>firstSymbolInHighOrderBits</spirit:name>
- <spirit:displayName>First Symbol In High-Order Bits</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="firstSymbolInHighOrderBits">true</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>highOrderSymbolAtMSB</spirit:name>
- <spirit:displayName>highOrderSymbolAtMSB</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="highOrderSymbolAtMSB">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maxChannel</spirit:name>
- <spirit:displayName>Maximum channel</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maxChannel">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>packetDescription</spirit:name>
- <spirit:displayName>Packet description </spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="packetDescription"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readyAllowance</spirit:name>
- <spirit:displayName>Ready allowance</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyAllowance">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readyLatency</spirit:name>
- <spirit:displayName>Ready latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyLatency">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>symbolsPerBeat</spirit:name>
- <spirit:displayName>Symbols per beat </spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="symbolsPerBeat">1</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>udp_tx_src_out_xon</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>xon</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>udp_tx_siso_xon</spirit:name>
+ <spirit:name>coe_writedata_export</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
@@ -633,12 +590,12 @@
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
<spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">st_clk</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>associatedReset</spirit:name>
<spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">st_rst</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>prSafe</spirit:name>
@@ -653,7 +610,7 @@
<spirit:view>
<spirit:name>QUARTUS_SYNTH</spirit:name>
<spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
- <spirit:modelName>ta2_unb2b_1GbE_mc</spirit:modelName>
+ <spirit:modelName>avs_common_mm_readlatency0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>QUARTUS_SYNTH</spirit:localName>
</spirit:fileSetRef>
@@ -661,25 +618,9 @@
</spirit:views>
<spirit:ports>
<spirit:port>
- <spirit:name>kernel_snk_data</spirit:name>
+ <spirit:name>csi_system_clk</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>39</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_snk_ready</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
@@ -689,7 +630,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>kernel_snk_valid</spirit:name>
+ <spirit:name>csi_system_reset</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -701,12 +642,12 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>kernel_src_data</spirit:name>
+ <spirit:name>avs_mem_address</spirit:name>
<spirit:wire>
- <spirit:direction>out</spirit:direction>
+ <spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>39</spirit:right>
+ <spirit:right>7</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -717,43 +658,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>kernel_src_ready</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_src_valid</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_clk</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_reset</spirit:name>
+ <spirit:name>avs_mem_write</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -765,19 +670,23 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>st_clk</spirit:name>
+ <spirit:name>avs_mem_writedata</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>st_rst</spirit:name>
+ <spirit:name>avs_mem_read</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -789,40 +698,12 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>udp_rx_siso_ready</spirit:name>
+ <spirit:name>avs_mem_readdata</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>udp_rx_sosi_data</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>39</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>udp_rx_sosi_empty</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>1</spirit:right>
+ <spirit:right>31</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -833,33 +714,9 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>udp_rx_sosi_eop</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>udp_rx_sosi_sop</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>udp_rx_sosi_valid</spirit:name>
+ <spirit:name>avs_mem_waitrequest</spirit:name>
<spirit:wire>
- <spirit:direction>in</spirit:direction>
+ <spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
@@ -869,9 +726,9 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>udp_tx_siso_ready</spirit:name>
+ <spirit:name>coe_reset_export</spirit:name>
<spirit:wire>
- <spirit:direction>in</spirit:direction>
+ <spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
@@ -881,28 +738,24 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>udp_tx_sosi_data</spirit:name>
+ <spirit:name>coe_clk_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>39</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>udp_tx_sosi_empty</spirit:name>
+ <spirit:name>coe_address_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>1</spirit:right>
+ <spirit:right>7</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -913,7 +766,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>udp_tx_sosi_eop</spirit:name>
+ <spirit:name>coe_write_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
@@ -925,19 +778,23 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>udp_tx_sosi_sop</spirit:name>
+ <spirit:name>coe_writedata_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>udp_tx_sosi_valid</spirit:name>
+ <spirit:name>coe_read_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
@@ -949,21 +806,25 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>udp_tx_siso_xon</spirit:name>
+ <spirit:name>coe_readdata_export</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>udp_rx_siso_xon</spirit:name>
+ <spirit:name>coe_waitrequest_export</spirit:name>
<spirit:wire>
- <spirit:direction>out</spirit:direction>
+ <spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
@@ -976,13 +837,29 @@
</spirit:model>
<spirit:vendorExtensions>
<altera:entity_info>
- <spirit:vendor>Altera Corporation</spirit:vendor>
- <spirit:library>board_ta2_unb2b_1GbE_mc</spirit:library>
- <spirit:name>ta2_unb2b_1GbE_mc</spirit:name>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>board_reg_ta2_unb2b_jesd204b</spirit:library>
+ <spirit:name>avs_common_mm_readlatency0</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
<altera:altera_module_parameters>
- <spirit:parameters></spirit:parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
</altera:altera_module_parameters>
<altera:altera_system_parameters>
<spirit:parameters>
@@ -1025,17 +902,17 @@
<spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>kernel_clk</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>kernel_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>8</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -1044,28 +921,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>kernel_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>kernel_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -1078,210 +954,268 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>kernel_clk</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>kernel_snk</name>
- <type>avalon_streaming</type>
+ <name>mem</name>
+ <type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
- <name>kernel_snk_data</name>
- <role>data</role>
+ <name>avs_mem_address</name>
+ <role>address</role>
<direction>Input</direction>
- <width>40</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>kernel_snk_ready</name>
- <role>ready</role>
- <direction>Output</direction>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>kernel_snk_valid</name>
- <role>valid</role>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
</ports>
<assignments>
- <assignmentValueMap/>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
</entry>
<entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
+ <key>addressGroup</key>
+ <value>0</value>
</entry>
<entry>
- <key>beatsPerCycle</key>
- <value>1</value>
+ <key>addressSpan</key>
+ <value>1024</value>
</entry>
<entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
+ <key>addressUnits</key>
+ <value>WORDS</value>
</entry>
<entry>
- <key>emptyWithinPacket</key>
+ <key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
- <key>errorDescriptor</key>
+ <key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
+ <key>associatedReset</key>
+ <value>system_reset</value>
</entry>
<entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
</entry>
<entry>
- <key>maxChannel</key>
+ <key>bridgedAddressOffset</key>
<value>0</value>
</entry>
<entry>
- <key>packetDescription</key>
- <value></value>
+ <key>bridgesToMaster</key>
</entry>
<entry>
- <key>prSafe</key>
+ <key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
- <key>readyAllowance</key>
- <value>0</value>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
</entry>
<entry>
- <key>readyLatency</key>
- <value>0</value>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
</entry>
<entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_src</name>
- <type>avalon_streaming</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_src_data</name>
- <role>data</role>
- <direction>Output</direction>
- <width>40</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_src_ready</name>
- <role>ready</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_src_valid</name>
- <role>valid</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
<entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
+ <key>holdTime</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
+ <key>interleaveBursts</key>
+ <value>false</value>
</entry>
<entry>
- <key>beatsPerCycle</key>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
</entry>
<entry>
- <key>emptyWithinPacket</key>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
<value>false</value>
</entry>
<entry>
- <key>errorDescriptor</key>
+ <key>readLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>1</value>
</entry>
<entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
</entry>
<entry>
- <key>highOrderSymbolAtMSB</key>
+ <key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
- <key>maxChannel</key>
+ <key>setupTime</key>
<value>0</value>
</entry>
<entry>
- <key>packetDescription</key>
- <value></value>
+ <key>timingUnits</key>
+ <value>Cycles</value>
</entry>
<entry>
- <key>prSafe</key>
+ <key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
- <key>readyAllowance</key>
+ <key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
- <key>readyLatency</key>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
<value>0</value>
</entry>
<entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>st_clk</name>
- <type>clock</type>
+ <name>read</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>st_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -1293,31 +1227,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>st_rst</name>
- <type>reset</type>
+ <name>readdata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>st_rst</name>
- <role>reset</role>
+ <name>coe_readdata_export</name>
+ <role>export</role>
<direction>Input</direction>
- <width>1</width>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -1327,68 +1260,30 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>st_clk</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>udp_rx_snk_in</name>
- <type>avalon_streaming</type>
+ <name>reset</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>udp_rx_siso_ready</name>
- <role>ready</role>
+ <name>coe_reset_export</name>
+ <role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
- <port>
- <name>udp_rx_sosi_data</name>
- <role>data</role>
- <direction>Input</direction>
- <width>40</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>udp_rx_sosi_empty</name>
- <role>empty</role>
- <direction>Input</direction>
- <width>2</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>udp_rx_sosi_eop</name>
- <role>endofpacket</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>udp_rx_sosi_sop</name>
- <role>startofpacket</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>udp_rx_sosi_valid</name>
- <role>valid</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
</ports>
<assignments>
<assignmentValueMap/>
@@ -1397,71 +1292,89 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>st_clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>st_rst</value>
</entry>
<entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
+ <key>prSafe</key>
<value>false</value>
</entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
<entry>
- <key>maxChannel</key>
+ <key>clockRate</key>
<value>0</value>
</entry>
<entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
+ <key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
- <key>readyAllowance</key>
- <value>0</value>
+ <key>ptfSchematicName</key>
</entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
<entry>
- <key>readyLatency</key>
- <value>0</value>
+ <key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>udp_rx_snk_in_xon</name>
+ <name>waitrequest</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>udp_rx_siso_xon</name>
- <role>xon</role>
- <direction>Output</direction>
+ <name>coe_waitrequest_export</name>
+ <role>export</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -1474,11 +1387,9 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>st_clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>st_rst</value>
</entry>
<entry>
<key>prSafe</key>
@@ -1488,53 +1399,13 @@
</parameters>
</interface>
<interface>
- <name>udp_tx_src_out</name>
- <type>avalon_streaming</type>
- <isStart>true</isStart>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
<ports>
<port>
- <name>udp_tx_siso_ready</name>
- <role>ready</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>udp_tx_sosi_data</name>
- <role>data</role>
- <direction>Output</direction>
- <width>40</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>udp_tx_sosi_empty</name>
- <role>empty</role>
- <direction>Output</direction>
- <width>2</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>udp_tx_sosi_eop</name>
- <role>endofpacket</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>udp_tx_sosi_sop</name>
- <role>startofpacket</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>udp_tx_sosi_valid</name>
- <role>valid</role>
+ <name>coe_write_export</name>
+ <role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -1548,74 +1419,29 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>st_clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>st_rst</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>udp_tx_src_out_xon</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>udp_tx_siso_xon</name>
- <role>xon</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -1625,11 +1451,9 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>st_clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>st_rst</value>
</entry>
<entry>
<key>prSafe</key>
@@ -1645,58 +1469,87 @@
<spirit:name>systemInfos</spirit:name>
<spirit:displayName>systemInfos</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
- <connPtSystemInfos/>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>10</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
</systemInfosDefinition>]]></spirit:value>
</spirit:parameter>
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="kernel_clk" altera:internal="board_ta2_unb2b_1GbE_mc.kernel_clk" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="kernel_clk" altera:internal="kernel_clk"></altera:port_mapping>
+ <altera:interface_mapping altera:name="address" altera:internal="board_reg_ta2_unb2b_jesd204b.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="board_reg_ta2_unb2b_jesd204b.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="kernel_reset" altera:internal="board_ta2_unb2b_1GbE_mc.kernel_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="kernel_reset" altera:internal="kernel_reset"></altera:port_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="board_reg_ta2_unb2b_jesd204b.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_waitrequest" altera:internal="avs_mem_waitrequest"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="kernel_snk" altera:internal="board_ta2_unb2b_1GbE_mc.kernel_snk" altera:type="avalon_streaming" altera:dir="end">
- <altera:port_mapping altera:name="kernel_snk_data" altera:internal="kernel_snk_data"></altera:port_mapping>
- <altera:port_mapping altera:name="kernel_snk_ready" altera:internal="kernel_snk_ready"></altera:port_mapping>
- <altera:port_mapping altera:name="kernel_snk_valid" altera:internal="kernel_snk_valid"></altera:port_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="board_reg_ta2_unb2b_jesd204b.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="kernel_src" altera:internal="board_ta2_unb2b_1GbE_mc.kernel_src" altera:type="avalon_streaming" altera:dir="start">
- <altera:port_mapping altera:name="kernel_src_data" altera:internal="kernel_src_data"></altera:port_mapping>
- <altera:port_mapping altera:name="kernel_src_ready" altera:internal="kernel_src_ready"></altera:port_mapping>
- <altera:port_mapping altera:name="kernel_src_valid" altera:internal="kernel_src_valid"></altera:port_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="board_reg_ta2_unb2b_jesd204b.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="st_clk" altera:internal="board_ta2_unb2b_1GbE_mc.st_clk" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="st_clk" altera:internal="st_clk"></altera:port_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="board_reg_ta2_unb2b_jesd204b.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="st_rst" altera:internal="board_ta2_unb2b_1GbE_mc.st_rst" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="st_rst" altera:internal="st_rst"></altera:port_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="board_reg_ta2_unb2b_jesd204b.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="udp_rx_snk_in" altera:internal="board_ta2_unb2b_1GbE_mc.udp_rx_snk_in" altera:type="avalon_streaming" altera:dir="end">
- <altera:port_mapping altera:name="udp_rx_siso_ready" altera:internal="udp_rx_siso_ready"></altera:port_mapping>
- <altera:port_mapping altera:name="udp_rx_sosi_data" altera:internal="udp_rx_sosi_data"></altera:port_mapping>
- <altera:port_mapping altera:name="udp_rx_sosi_empty" altera:internal="udp_rx_sosi_empty"></altera:port_mapping>
- <altera:port_mapping altera:name="udp_rx_sosi_eop" altera:internal="udp_rx_sosi_eop"></altera:port_mapping>
- <altera:port_mapping altera:name="udp_rx_sosi_sop" altera:internal="udp_rx_sosi_sop"></altera:port_mapping>
- <altera:port_mapping altera:name="udp_rx_sosi_valid" altera:internal="udp_rx_sosi_valid"></altera:port_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="board_reg_ta2_unb2b_jesd204b.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="udp_rx_snk_in_xon" altera:internal="board_ta2_unb2b_1GbE_mc.udp_rx_snk_in_xon" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="udp_rx_siso_xon" altera:internal="udp_rx_siso_xon"></altera:port_mapping>
+ <altera:interface_mapping altera:name="waitrequest" altera:internal="board_reg_ta2_unb2b_jesd204b.waitrequest" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_waitrequest_export" altera:internal="coe_waitrequest_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="udp_tx_src_out" altera:internal="board_ta2_unb2b_1GbE_mc.udp_tx_src_out" altera:type="avalon_streaming" altera:dir="start">
- <altera:port_mapping altera:name="udp_tx_siso_ready" altera:internal="udp_tx_siso_ready"></altera:port_mapping>
- <altera:port_mapping altera:name="udp_tx_sosi_data" altera:internal="udp_tx_sosi_data"></altera:port_mapping>
- <altera:port_mapping altera:name="udp_tx_sosi_empty" altera:internal="udp_tx_sosi_empty"></altera:port_mapping>
- <altera:port_mapping altera:name="udp_tx_sosi_eop" altera:internal="udp_tx_sosi_eop"></altera:port_mapping>
- <altera:port_mapping altera:name="udp_tx_sosi_sop" altera:internal="udp_tx_sosi_sop"></altera:port_mapping>
- <altera:port_mapping altera:name="udp_tx_sosi_valid" altera:internal="udp_tx_sosi_valid"></altera:port_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="board_reg_ta2_unb2b_jesd204b.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="udp_tx_src_out_xon" altera:internal="board_ta2_unb2b_1GbE_mc.udp_tx_src_out_xon" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="udp_tx_siso_xon" altera:internal="udp_tx_siso_xon"></altera:port_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="board_reg_ta2_unb2b_jesd204b.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
- <altera:altera_has_warnings>true</altera:altera_has_warnings>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
<altera:altera_has_errors>false</altera:altera_has_errors>
</spirit:vendorExtensions>
</spirit:component>
\ No newline at end of file
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_ta2_unb2b_10GbE.ip b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_ta2_unb2b_10GbE.ip
deleted file mode 100644
index 278aec03c9d63fab81dbc622548d474c91e01fe2..0000000000000000000000000000000000000000
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_ta2_unb2b_10GbE.ip
+++ /dev/null
@@ -1,1112 +0,0 @@
-<?xml version="1.0" ?>
-<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
- <spirit:vendor>Altera Corporation</spirit:vendor>
- <spirit:library>board_ta2_unb2b_10GbE</spirit:library>
- <spirit:name>board_ta2_unb2b_10GbE</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>config_reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>reset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>config_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>synchronousEdges</spirit:name>
- <spirit:displayName>Synchronous edges</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="synchronousEdges">NONE</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>kernel_clk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>clk</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_clk</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>clockRate</spirit:name>
- <spirit:displayName>Clock rate</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>externallyDriven</spirit:name>
- <spirit:displayName>Externally driven</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ptfSchematicName</spirit:name>
- <spirit:displayName>PTF schematic name</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>kernel_reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>reset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">kernel_clk</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>synchronousEdges</spirit:name>
- <spirit:displayName>Synchronous edges</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>kernel_snk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon_streaming" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>data</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_snk_data</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ready</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_snk_ready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>valid</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_snk_valid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">kernel_clk</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">kernel_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>beatsPerCycle</spirit:name>
- <spirit:displayName>Beats Per Cycle</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="beatsPerCycle">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>dataBitsPerSymbol</spirit:name>
- <spirit:displayName>Data bits per symbol</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="dataBitsPerSymbol">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>emptyWithinPacket</spirit:name>
- <spirit:displayName>emptyWithinPacket</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="emptyWithinPacket">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>errorDescriptor</spirit:name>
- <spirit:displayName>Error descriptor</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="errorDescriptor"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>firstSymbolInHighOrderBits</spirit:name>
- <spirit:displayName>First Symbol In High-Order Bits</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="firstSymbolInHighOrderBits">true</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>highOrderSymbolAtMSB</spirit:name>
- <spirit:displayName>highOrderSymbolAtMSB</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="highOrderSymbolAtMSB">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maxChannel</spirit:name>
- <spirit:displayName>Maximum channel</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maxChannel">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>packetDescription</spirit:name>
- <spirit:displayName>Packet description </spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="packetDescription"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readyAllowance</spirit:name>
- <spirit:displayName>Ready allowance</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyAllowance">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readyLatency</spirit:name>
- <spirit:displayName>Ready latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyLatency">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>symbolsPerBeat</spirit:name>
- <spirit:displayName>Symbols per beat </spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="symbolsPerBeat">1</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>kernel_src</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon_streaming" spirit:version="18.0"></spirit:busType>
- <spirit:master></spirit:master>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>data</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_src_data</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ready</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_src_ready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>valid</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_src_valid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">kernel_clk</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">kernel_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>beatsPerCycle</spirit:name>
- <spirit:displayName>Beats Per Cycle</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="beatsPerCycle">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>dataBitsPerSymbol</spirit:name>
- <spirit:displayName>Data bits per symbol</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="dataBitsPerSymbol">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>emptyWithinPacket</spirit:name>
- <spirit:displayName>emptyWithinPacket</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="emptyWithinPacket">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>errorDescriptor</spirit:name>
- <spirit:displayName>Error descriptor</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="errorDescriptor"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>firstSymbolInHighOrderBits</spirit:name>
- <spirit:displayName>First Symbol In High-Order Bits</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="firstSymbolInHighOrderBits">true</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>highOrderSymbolAtMSB</spirit:name>
- <spirit:displayName>highOrderSymbolAtMSB</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="highOrderSymbolAtMSB">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maxChannel</spirit:name>
- <spirit:displayName>Maximum channel</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maxChannel">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>packetDescription</spirit:name>
- <spirit:displayName>Packet description </spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="packetDescription"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readyAllowance</spirit:name>
- <spirit:displayName>Ready allowance</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyAllowance">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readyLatency</spirit:name>
- <spirit:displayName>Ready latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyLatency">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>symbolsPerBeat</spirit:name>
- <spirit:displayName>Symbols per beat </spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="symbolsPerBeat">1</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>refclk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>clk</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>clk_ref_r</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>clockRate</spirit:name>
- <spirit:displayName>Clock rate</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>externallyDriven</spirit:name>
- <spirit:displayName>Externally driven</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ptfSchematicName</spirit:name>
- <spirit:displayName>PTF schematic name</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>rx_serial_data</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>conduit</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>rx_serial_r</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>rx_status</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rx_status</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>rx_status</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>tx_serial_data</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>conduit</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>tx_serial_r</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- </spirit:busInterfaces>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>QUARTUS_SYNTH</spirit:name>
- <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
- <spirit:modelName>ta2_unb2b_10GbE</spirit:modelName>
- <spirit:fileSetRef>
- <spirit:localName>QUARTUS_SYNTH</spirit:localName>
- </spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>kernel_snk_data</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>71</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_snk_ready</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_snk_valid</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_src_data</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>71</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_src_ready</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_src_valid</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_clk</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>clk_ref_r</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>rx_serial_r</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>tx_serial_r</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>config_reset</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_reset</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>rx_status</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- </spirit:model>
- <spirit:vendorExtensions>
- <altera:entity_info>
- <spirit:vendor>Altera Corporation</spirit:vendor>
- <spirit:library>board_ta2_unb2b_10GbE</spirit:library>
- <spirit:name>ta2_unb2b_10GbE</spirit:name>
- <spirit:version>1.0</spirit:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <spirit:parameters></spirit:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>device</spirit:name>
- <spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceFamily</spirit:name>
- <spirit:displayName>Device family</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceSpeedGrade</spirit:name>
- <spirit:displayName>Device Speed Grade</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>generationId</spirit:name>
- <spirit:displayName>Generation Id</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bonusData</spirit:name>
- <spirit:displayName>bonusData</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
-{
-}
-</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>hideFromIPCatalog</spirit:name>
- <spirit:displayName>Hide from IP Catalog</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>lockedInterfaceDefinition</spirit:name>
- <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>config_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>config_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_snk</name>
- <type>avalon_streaming</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_snk_data</name>
- <role>data</role>
- <direction>Input</direction>
- <width>72</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_snk_ready</name>
- <role>ready</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_snk_valid</name>
- <role>valid</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_src</name>
- <type>avalon_streaming</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_src_data</name>
- <role>data</role>
- <direction>Output</direction>
- <width>72</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_src_ready</name>
- <role>ready</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_src_valid</name>
- <role>valid</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>refclk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk_ref_r</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>rx_serial_data</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>rx_serial_r</name>
- <role>conduit</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>rx_status</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>rx_status</name>
- <role>rx_status</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>tx_serial_data</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>tx_serial_r</name>
- <role>conduit</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>systemInfos</spirit:name>
- <spirit:displayName>systemInfos</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
- <connPtSystemInfos/>
-</systemInfosDefinition>]]></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="config_reset" altera:internal="board_ta2_unb2b_10GbE.config_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="config_reset" altera:internal="config_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="kernel_clk" altera:internal="board_ta2_unb2b_10GbE.kernel_clk" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="kernel_clk" altera:internal="kernel_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="kernel_reset" altera:internal="board_ta2_unb2b_10GbE.kernel_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="kernel_reset" altera:internal="kernel_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="kernel_snk" altera:internal="board_ta2_unb2b_10GbE.kernel_snk" altera:type="avalon_streaming" altera:dir="end">
- <altera:port_mapping altera:name="kernel_snk_data" altera:internal="kernel_snk_data"></altera:port_mapping>
- <altera:port_mapping altera:name="kernel_snk_ready" altera:internal="kernel_snk_ready"></altera:port_mapping>
- <altera:port_mapping altera:name="kernel_snk_valid" altera:internal="kernel_snk_valid"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="kernel_src" altera:internal="board_ta2_unb2b_10GbE.kernel_src" altera:type="avalon_streaming" altera:dir="start">
- <altera:port_mapping altera:name="kernel_src_data" altera:internal="kernel_src_data"></altera:port_mapping>
- <altera:port_mapping altera:name="kernel_src_ready" altera:internal="kernel_src_ready"></altera:port_mapping>
- <altera:port_mapping altera:name="kernel_src_valid" altera:internal="kernel_src_valid"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="refclk" altera:internal="board_ta2_unb2b_10GbE.refclk" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="clk_ref_r" altera:internal="clk_ref_r"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="rx_serial_data" altera:internal="board_ta2_unb2b_10GbE.rx_serial_data" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="rx_serial_r" altera:internal="rx_serial_r"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="rx_status" altera:internal="board_ta2_unb2b_10GbE.rx_status" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="rx_status" altera:internal="rx_status"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="tx_serial_data" altera:internal="board_ta2_unb2b_10GbE.tx_serial_data" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="tx_serial_r" altera:internal="tx_serial_r"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </spirit:vendorExtensions>
-</spirit:component>
\ No newline at end of file
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_ta2_unb2b_40GbE.ip b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_ta2_unb2b_40GbE.ip
deleted file mode 100644
index 137c3b32e9b6e19596ad6ead9a982385ac6354e1..0000000000000000000000000000000000000000
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_ta2_unb2b_40GbE.ip
+++ /dev/null
@@ -1,1201 +0,0 @@
-<?xml version="1.0" ?>
-<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
- <spirit:vendor>Altera Corporation</spirit:vendor>
- <spirit:library>board_ta2_unb2b_40GbE</spirit:library>
- <spirit:name>board_ta2_unb2b_40GbE</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>config_clk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>clk</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>config_clk</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>clockRate</spirit:name>
- <spirit:displayName>Clock rate</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>externallyDriven</spirit:name>
- <spirit:displayName>Externally driven</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ptfSchematicName</spirit:name>
- <spirit:displayName>PTF schematic name</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>config_reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>reset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>config_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">config_clk</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>synchronousEdges</spirit:name>
- <spirit:displayName>Synchronous edges</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>kernel_clk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>clk</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_clk</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>clockRate</spirit:name>
- <spirit:displayName>Clock rate</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>externallyDriven</spirit:name>
- <spirit:displayName>Externally driven</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ptfSchematicName</spirit:name>
- <spirit:displayName>PTF schematic name</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>kernel_reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>reset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">kernel_clk</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>synchronousEdges</spirit:name>
- <spirit:displayName>Synchronous edges</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>kernel_snk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon_streaming" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>data</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_snk_data</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ready</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_snk_ready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>valid</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_snk_valid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">kernel_clk</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">kernel_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>beatsPerCycle</spirit:name>
- <spirit:displayName>Beats Per Cycle</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="beatsPerCycle">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>dataBitsPerSymbol</spirit:name>
- <spirit:displayName>Data bits per symbol</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="dataBitsPerSymbol">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>emptyWithinPacket</spirit:name>
- <spirit:displayName>emptyWithinPacket</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="emptyWithinPacket">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>errorDescriptor</spirit:name>
- <spirit:displayName>Error descriptor</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="errorDescriptor"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>firstSymbolInHighOrderBits</spirit:name>
- <spirit:displayName>First Symbol In High-Order Bits</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="firstSymbolInHighOrderBits">true</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>highOrderSymbolAtMSB</spirit:name>
- <spirit:displayName>highOrderSymbolAtMSB</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="highOrderSymbolAtMSB">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maxChannel</spirit:name>
- <spirit:displayName>Maximum channel</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maxChannel">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>packetDescription</spirit:name>
- <spirit:displayName>Packet description </spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="packetDescription"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readyAllowance</spirit:name>
- <spirit:displayName>Ready allowance</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyAllowance">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readyLatency</spirit:name>
- <spirit:displayName>Ready latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyLatency">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>symbolsPerBeat</spirit:name>
- <spirit:displayName>Symbols per beat </spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="symbolsPerBeat">1</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>kernel_src</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon_streaming" spirit:version="18.0"></spirit:busType>
- <spirit:master></spirit:master>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>data</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_src_data</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ready</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_src_ready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>valid</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>kernel_src_valid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">kernel_clk</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">kernel_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>beatsPerCycle</spirit:name>
- <spirit:displayName>Beats Per Cycle</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="beatsPerCycle">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>dataBitsPerSymbol</spirit:name>
- <spirit:displayName>Data bits per symbol</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="dataBitsPerSymbol">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>emptyWithinPacket</spirit:name>
- <spirit:displayName>emptyWithinPacket</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="emptyWithinPacket">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>errorDescriptor</spirit:name>
- <spirit:displayName>Error descriptor</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="errorDescriptor"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>firstSymbolInHighOrderBits</spirit:name>
- <spirit:displayName>First Symbol In High-Order Bits</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="firstSymbolInHighOrderBits">true</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>highOrderSymbolAtMSB</spirit:name>
- <spirit:displayName>highOrderSymbolAtMSB</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="highOrderSymbolAtMSB">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maxChannel</spirit:name>
- <spirit:displayName>Maximum channel</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maxChannel">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>packetDescription</spirit:name>
- <spirit:displayName>Packet description </spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="packetDescription"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readyAllowance</spirit:name>
- <spirit:displayName>Ready allowance</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyAllowance">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readyLatency</spirit:name>
- <spirit:displayName>Ready latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readyLatency">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>symbolsPerBeat</spirit:name>
- <spirit:displayName>Symbols per beat </spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="symbolsPerBeat">1</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>refclk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>clk</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>clk_ref_r</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>clockRate</spirit:name>
- <spirit:displayName>Clock rate</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>externallyDriven</spirit:name>
- <spirit:displayName>Externally driven</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ptfSchematicName</spirit:name>
- <spirit:displayName>PTF schematic name</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>rx_serial_data</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>conduit</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>rx_serial_r</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>rx_status</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>rx_status</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>rx_status</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>tx_serial_data</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>conduit</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>tx_serial_r</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- </spirit:busInterfaces>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>QUARTUS_SYNTH</spirit:name>
- <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
- <spirit:modelName>ta2_unb2b_40GbE</spirit:modelName>
- <spirit:fileSetRef>
- <spirit:localName>QUARTUS_SYNTH</spirit:localName>
- </spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>kernel_snk_data</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>263</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_snk_ready</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_snk_valid</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_src_data</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>263</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_src_ready</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_src_valid</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>config_clk</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_clk</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>clk_ref_r</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>rx_serial_r</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>3</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>tx_serial_r</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>3</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>config_reset</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>kernel_reset</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>rx_status</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- </spirit:model>
- <spirit:vendorExtensions>
- <altera:entity_info>
- <spirit:vendor>Altera Corporation</spirit:vendor>
- <spirit:library>board_ta2_unb2b_40GbE</spirit:library>
- <spirit:name>ta2_unb2b_40GbE</spirit:name>
- <spirit:version>1.0</spirit:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <spirit:parameters></spirit:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>device</spirit:name>
- <spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceFamily</spirit:name>
- <spirit:displayName>Device family</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceSpeedGrade</spirit:name>
- <spirit:displayName>Device Speed Grade</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>generationId</spirit:name>
- <spirit:displayName>Generation Id</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bonusData</spirit:name>
- <spirit:displayName>bonusData</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
-{
-}
-</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>hideFromIPCatalog</spirit:name>
- <spirit:displayName>Hide from IP Catalog</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>lockedInterfaceDefinition</spirit:name>
- <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>config_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>config_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>config_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>config_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>config_clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_snk</name>
- <type>avalon_streaming</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_snk_data</name>
- <role>data</role>
- <direction>Input</direction>
- <width>264</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_snk_ready</name>
- <role>ready</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_snk_valid</name>
- <role>valid</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_src</name>
- <type>avalon_streaming</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_src_data</name>
- <role>data</role>
- <direction>Output</direction>
- <width>264</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_src_ready</name>
- <role>ready</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_src_valid</name>
- <role>valid</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>refclk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk_ref_r</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>rx_serial_data</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>rx_serial_r</name>
- <role>conduit</role>
- <direction>Input</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>rx_status</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>rx_status</name>
- <role>rx_status</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>tx_serial_data</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>tx_serial_r</name>
- <role>conduit</role>
- <direction>Output</direction>
- <width>4</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>systemInfos</spirit:name>
- <spirit:displayName>systemInfos</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
- <connPtSystemInfos/>
-</systemInfosDefinition>]]></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="config_clk" altera:internal="board_ta2_unb2b_40GbE.config_clk" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="config_clk" altera:internal="config_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="config_reset" altera:internal="board_ta2_unb2b_40GbE.config_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="config_reset" altera:internal="config_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="kernel_clk" altera:internal="board_ta2_unb2b_40GbE.kernel_clk" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="kernel_clk" altera:internal="kernel_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="kernel_reset" altera:internal="board_ta2_unb2b_40GbE.kernel_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="kernel_reset" altera:internal="kernel_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="kernel_snk" altera:internal="board_ta2_unb2b_40GbE.kernel_snk" altera:type="avalon_streaming" altera:dir="end">
- <altera:port_mapping altera:name="kernel_snk_data" altera:internal="kernel_snk_data"></altera:port_mapping>
- <altera:port_mapping altera:name="kernel_snk_ready" altera:internal="kernel_snk_ready"></altera:port_mapping>
- <altera:port_mapping altera:name="kernel_snk_valid" altera:internal="kernel_snk_valid"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="kernel_src" altera:internal="board_ta2_unb2b_40GbE.kernel_src" altera:type="avalon_streaming" altera:dir="start">
- <altera:port_mapping altera:name="kernel_src_data" altera:internal="kernel_src_data"></altera:port_mapping>
- <altera:port_mapping altera:name="kernel_src_ready" altera:internal="kernel_src_ready"></altera:port_mapping>
- <altera:port_mapping altera:name="kernel_src_valid" altera:internal="kernel_src_valid"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="refclk" altera:internal="board_ta2_unb2b_40GbE.refclk" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="clk_ref_r" altera:internal="clk_ref_r"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="rx_serial_data" altera:internal="board_ta2_unb2b_40GbE.rx_serial_data" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="rx_serial_r" altera:internal="rx_serial_r"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="rx_status" altera:internal="board_ta2_unb2b_40GbE.rx_status" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="rx_status" altera:internal="rx_status"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="tx_serial_data" altera:internal="board_ta2_unb2b_40GbE.tx_serial_data" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="tx_serial_r" altera:internal="tx_serial_r"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </spirit:vendorExtensions>
-</spirit:component>
\ No newline at end of file
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_ta2_unb2b_jesd204b.ip b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_ta2_unb2b_jesd204b.ip
deleted file mode 100644
index 01a10b4b68696731e8d36608d74107fb13bacdfd..0000000000000000000000000000000000000000
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_ta2_unb2b_jesd204b.ip
+++ /dev/null
@@ -1,1686 +0,0 @@
-<?xml version="1.0" ?>
-<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
- <ipxact:vendor>Altera Corporation</ipxact:vendor>
- <ipxact:library>board_ta2_unb2b_jesd204b</ipxact:library>
- <ipxact:name>board_ta2_unb2b_jesd204b</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- <ipxact:busInterfaces>
- <ipxact:busInterface>
- <ipxact:name>kernel_src</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="avalon_streaming" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="avalon_streaming" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>data</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>kernel_src_data</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>ready</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>kernel_src_ready</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>valid</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>kernel_src_valid</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:master></ipxact:master>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value>kernel_clk</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value>kernel_reset</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="beatsPerCycle" type="int">
- <ipxact:name>beatsPerCycle</ipxact:name>
- <ipxact:displayName>Beats Per Cycle</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="dataBitsPerSymbol" type="int">
- <ipxact:name>dataBitsPerSymbol</ipxact:name>
- <ipxact:displayName>Data bits per symbol</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="emptyWithinPacket" type="bit">
- <ipxact:name>emptyWithinPacket</ipxact:name>
- <ipxact:displayName>emptyWithinPacket</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="errorDescriptor" type="string">
- <ipxact:name>errorDescriptor</ipxact:name>
- <ipxact:displayName>Error descriptor</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="firstSymbolInHighOrderBits" type="bit">
- <ipxact:name>firstSymbolInHighOrderBits</ipxact:name>
- <ipxact:displayName>First Symbol In High-Order Bits</ipxact:displayName>
- <ipxact:value>true</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="highOrderSymbolAtMSB" type="bit">
- <ipxact:name>highOrderSymbolAtMSB</ipxact:name>
- <ipxact:displayName>highOrderSymbolAtMSB</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maxChannel" type="int">
- <ipxact:name>maxChannel</ipxact:name>
- <ipxact:displayName>Maximum channel</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="packetDescription" type="string">
- <ipxact:name>packetDescription</ipxact:name>
- <ipxact:displayName>Packet description </ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readyAllowance" type="int">
- <ipxact:name>readyAllowance</ipxact:name>
- <ipxact:displayName>Ready allowance</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readyLatency" type="int">
- <ipxact:name>readyLatency</ipxact:name>
- <ipxact:displayName>Ready latency</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="symbolsPerBeat" type="int">
- <ipxact:name>symbolsPerBeat</ipxact:name>
- <ipxact:displayName>Symbols per beat </ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>kernel_clk</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>kernel_clk</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="clockRate" type="longint">
- <ipxact:name>clockRate</ipxact:name>
- <ipxact:displayName>Clock rate</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="externallyDriven" type="bit">
- <ipxact:name>externallyDriven</ipxact:name>
- <ipxact:displayName>Externally driven</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ptfSchematicName" type="string">
- <ipxact:name>ptfSchematicName</ipxact:name>
- <ipxact:displayName>PTF schematic name</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>config_reset</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="reset" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>reset</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>config_reset</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="synchronousEdges" type="string">
- <ipxact:name>synchronousEdges</ipxact:name>
- <ipxact:displayName>Synchronous edges</ipxact:displayName>
- <ipxact:value>NONE</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>kernel_reset</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="reset" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>reset</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>kernel_reset</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>kernel_clk</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="synchronousEdges" type="string">
- <ipxact:name>synchronousEdges</ipxact:name>
- <ipxact:displayName>Synchronous edges</ipxact:displayName>
- <ipxact:value>DEASSERT</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>mem</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>address</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>jesd204b_mosi_address</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>writedata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>jesd204b_mosi_wrdata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>write</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>jesd204b_mosi_wr</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>read</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>jesd204b_mosi_rd</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>readdata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>jesd204b_miso_rddata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>waitrequest</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>jesd204b_miso_waitrequest</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="addressAlignment" type="string">
- <ipxact:name>addressAlignment</ipxact:name>
- <ipxact:displayName>Slave addressing</ipxact:displayName>
- <ipxact:value>DYNAMIC</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressGroup" type="int">
- <ipxact:name>addressGroup</ipxact:name>
- <ipxact:displayName>Address group</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressSpan" type="string">
- <ipxact:name>addressSpan</ipxact:name>
- <ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>1024</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressUnits" type="string">
- <ipxact:name>addressUnits</ipxact:name>
- <ipxact:displayName>Address units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
- <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
- <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>config_clk</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>Associated reset</ipxact:displayName>
- <ipxact:value>config_reset</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bitsPerSymbol" type="int">
- <ipxact:name>bitsPerSymbol</ipxact:name>
- <ipxact:displayName>Bits per symbol</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
- <ipxact:name>bridgedAddressOffset</ipxact:name>
- <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgesToMaster" type="string">
- <ipxact:name>bridgesToMaster</ipxact:name>
- <ipxact:displayName>Bridges to master</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
- <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
- <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstcountUnits" type="string">
- <ipxact:name>burstcountUnits</ipxact:name>
- <ipxact:displayName>Burstcount units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
- <ipxact:name>constantBurstBehavior</ipxact:name>
- <ipxact:displayName>Constant burst behavior</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="explicitAddressSpan" type="string">
- <ipxact:name>explicitAddressSpan</ipxact:name>
- <ipxact:displayName>Explicit address span</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="holdTime" type="int">
- <ipxact:name>holdTime</ipxact:name>
- <ipxact:displayName>Hold</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="interleaveBursts" type="bit">
- <ipxact:name>interleaveBursts</ipxact:name>
- <ipxact:displayName>Interleave bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isBigEndian" type="bit">
- <ipxact:name>isBigEndian</ipxact:name>
- <ipxact:displayName>Big endian</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isFlash" type="bit">
- <ipxact:name>isFlash</ipxact:name>
- <ipxact:displayName>Flash memory</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isMemoryDevice" type="bit">
- <ipxact:name>isMemoryDevice</ipxact:name>
- <ipxact:displayName>Memory device</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
- <ipxact:name>isNonVolatileStorage</ipxact:name>
- <ipxact:displayName>Non-volatile storage</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="linewrapBursts" type="bit">
- <ipxact:name>linewrapBursts</ipxact:name>
- <ipxact:displayName>Linewrap bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
- <ipxact:name>maximumPendingReadTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
- <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumReadLatency" type="int">
- <ipxact:name>minimumReadLatency</ipxact:name>
- <ipxact:displayName>minimumReadLatency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumResponseLatency" type="int">
- <ipxact:name>minimumResponseLatency</ipxact:name>
- <ipxact:displayName>Minimum response latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
- <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
- <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="printableDevice" type="bit">
- <ipxact:name>printableDevice</ipxact:name>
- <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readLatency" type="int">
- <ipxact:name>readLatency</ipxact:name>
- <ipxact:displayName>Read latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitStates" type="int">
- <ipxact:name>readWaitStates</ipxact:name>
- <ipxact:displayName>Read wait states</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitTime" type="int">
- <ipxact:name>readWaitTime</ipxact:name>
- <ipxact:displayName>Read wait</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
- <ipxact:name>registerIncomingSignals</ipxact:name>
- <ipxact:displayName>Register incoming signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
- <ipxact:name>registerOutgoingSignals</ipxact:name>
- <ipxact:displayName>Register outgoing signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="setupTime" type="int">
- <ipxact:name>setupTime</ipxact:name>
- <ipxact:displayName>Setup</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="timingUnits" type="string">
- <ipxact:name>timingUnits</ipxact:name>
- <ipxact:displayName>Timing units</ipxact:displayName>
- <ipxact:value>Cycles</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="transparentBridge" type="bit">
- <ipxact:name>transparentBridge</ipxact:name>
- <ipxact:displayName>Transparent bridge</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="waitrequestAllowance" type="int">
- <ipxact:name>waitrequestAllowance</ipxact:name>
- <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
- <ipxact:name>wellBehavedWaitrequest</ipxact:name>
- <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeLatency" type="int">
- <ipxact:name>writeLatency</ipxact:name>
- <ipxact:displayName>Write latency</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitStates" type="int">
- <ipxact:name>writeWaitStates</ipxact:name>
- <ipxact:displayName>Write wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitTime" type="int">
- <ipxact:name>writeWaitTime</ipxact:name>
- <ipxact:displayName>Write wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- <ipxact:vendorExtensions>
- <altera:altera_assignments>
- <ipxact:parameters>
- <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
- <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
- <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_assignments>
- </ipxact:vendorExtensions>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>config_clk</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>config_clk</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="clockRate" type="longint">
- <ipxact:name>clockRate</ipxact:name>
- <ipxact:displayName>Clock rate</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="externallyDriven" type="bit">
- <ipxact:name>externallyDriven</ipxact:name>
- <ipxact:displayName>Externally driven</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ptfSchematicName" type="string">
- <ipxact:name>ptfSchematicName</ipxact:name>
- <ipxact:displayName>PTF schematic name</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>jesd204b_refclk</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>jesd204b_refclk</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="clockRate" type="longint">
- <ipxact:name>clockRate</ipxact:name>
- <ipxact:displayName>Clock rate</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="externallyDriven" type="bit">
- <ipxact:name>externallyDriven</ipxact:name>
- <ipxact:displayName>Externally driven</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ptfSchematicName" type="string">
- <ipxact:name>ptfSchematicName</ipxact:name>
- <ipxact:displayName>PTF schematic name</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>jesd204b_sysref</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>conduit</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>jesd204b_sysref</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value>jesd204b_refclk</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value>kernel_reset</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>jesd204b_sync_n</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>conduit</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>jesd204b_sync_n_arr</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value>jesd204b_refclk</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value>kernel_reset</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>serial_rx_arr</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>conduit</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>serial_rx_arr</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value>kernel_clk</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value>kernel_reset</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- </ipxact:busInterfaces>
- <ipxact:model>
- <ipxact:views>
- <ipxact:view>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
- <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
- </ipxact:view>
- </ipxact:views>
- <ipxact:instantiations>
- <ipxact:componentInstantiation>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:moduleName>ta2_unb2b_jesd204b</ipxact:moduleName>
- <ipxact:fileSetRef>
- <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
- </ipxact:fileSetRef>
- <ipxact:parameters></ipxact:parameters>
- </ipxact:componentInstantiation>
- </ipxact:instantiations>
- <ipxact:ports>
- <ipxact:port>
- <ipxact:name>kernel_src_data</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>15</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>kernel_src_ready</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>kernel_src_valid</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>kernel_clk</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>config_reset</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>kernel_reset</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>jesd204b_mosi_address</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>7</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>jesd204b_mosi_wrdata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>jesd204b_mosi_wr</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>jesd204b_mosi_rd</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>jesd204b_miso_rddata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>jesd204b_miso_waitrequest</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>config_clk</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>jesd204b_refclk</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>jesd204b_sysref</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>jesd204b_sync_n_arr</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>serial_rx_arr</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- </ipxact:ports>
- </ipxact:model>
- <ipxact:vendorExtensions>
- <altera:entity_info>
- <ipxact:vendor>Altera Corporation</ipxact:vendor>
- <ipxact:library>board_ta2_unb2b_jesd204b</ipxact:library>
- <ipxact:name>ta2_unb2b_jesd204b</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <ipxact:parameters></ipxact:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="device" type="string">
- <ipxact:name>device</ipxact:name>
- <ipxact:displayName>Device</ipxact:displayName>
- <ipxact:value>10AX115U2F45E1SG</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceFamily" type="string">
- <ipxact:name>deviceFamily</ipxact:name>
- <ipxact:displayName>Device family</ipxact:displayName>
- <ipxact:value>Arria 10</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
- <ipxact:name>deviceSpeedGrade</ipxact:name>
- <ipxact:displayName>Device Speed Grade</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="generationId" type="int">
- <ipxact:name>generationId</ipxact:name>
- <ipxact:displayName>Generation Id</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bonusData" type="string">
- <ipxact:name>bonusData</ipxact:name>
- <ipxact:displayName>bonusData</ipxact:displayName>
- <ipxact:value>bonusData
-{
- element $system
- {
- datum _originalDeviceFamily
- {
- value = "Arria 10";
- type = "String";
- }
- }
- element board_ta2_unb2b_jesd204b
- {
- }
-}
-</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
- <ipxact:name>hideFromIPCatalog</ipxact:name>
- <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
- <ipxact:name>lockedInterfaceDefinition</ipxact:name>
- <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
- <ipxact:value><boundaryDefinition>
- <interfaces>
- <interface>
- <name>kernel_src</name>
- <type>avalon_streaming</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>kernel_src_data</name>
- <role>data</role>
- <direction>Output</direction>
- <width>16</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>kernel_src_ready</name>
- <role>ready</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>kernel_src_valid</name>
- <role>valid</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>beatsPerCycle</key>
- <value>1</value>
- </entry>
- <entry>
- <key>dataBitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>emptyWithinPacket</key>
- <value>false</value>
- </entry>
- <entry>
- <key>errorDescriptor</key>
- </entry>
- <entry>
- <key>firstSymbolInHighOrderBits</key>
- <value>true</value>
- </entry>
- <entry>
- <key>highOrderSymbolAtMSB</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maxChannel</key>
- <value>0</value>
- </entry>
- <entry>
- <key>packetDescription</key>
- <value></value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readyAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readyLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>symbolsPerBeat</key>
- <value>1</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>config_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>config_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>kernel_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>kernel_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>jesd204b_mosi_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>8</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>jesd204b_mosi_wrdata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>jesd204b_mosi_wr</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>jesd204b_mosi_rd</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>jesd204b_miso_rddata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>jesd204b_miso_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>1024</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>config_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>config_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>config_clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>config_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>jesd204b_refclk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>jesd204b_refclk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>jesd204b_sysref</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>jesd204b_sysref</name>
- <role>conduit</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>jesd204b_refclk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>jesd204b_sync_n</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>jesd204b_sync_n_arr</name>
- <role>conduit</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>jesd204b_refclk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>serial_rx_arr</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>serial_rx_arr</name>
- <role>conduit</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>kernel_clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>kernel_reset</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="systemInfos" type="string">
- <ipxact:name>systemInfos</ipxact:name>
- <ipxact:displayName>systemInfos</ipxact:displayName>
- <ipxact:value><systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x400' datawidth='32' /&gt;&lt;/address-map&gt;</value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>10</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="config_clk" altera:internal="board_ta2_unb2b_jesd204b.config_clk" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="config_clk" altera:internal="config_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="config_reset" altera:internal="board_ta2_unb2b_jesd204b.config_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="config_reset" altera:internal="config_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="jesd204b_refclk" altera:internal="board_ta2_unb2b_jesd204b.jesd204b_refclk" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="jesd204b_refclk" altera:internal="jesd204b_refclk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="jesd204b_sync_n" altera:internal="board_ta2_unb2b_jesd204b.jesd204b_sync_n" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="jesd204b_sync_n_arr" altera:internal="jesd204b_sync_n_arr"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="jesd204b_sysref" altera:internal="board_ta2_unb2b_jesd204b.jesd204b_sysref" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="jesd204b_sysref" altera:internal="jesd204b_sysref"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="kernel_clk" altera:internal="board_ta2_unb2b_jesd204b.kernel_clk" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="kernel_clk" altera:internal="kernel_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="kernel_reset" altera:internal="board_ta2_unb2b_jesd204b.kernel_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="kernel_reset" altera:internal="kernel_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="kernel_src" altera:internal="board_ta2_unb2b_jesd204b.kernel_src" altera:type="avalon_streaming" altera:dir="start">
- <altera:port_mapping altera:name="kernel_src_data" altera:internal="kernel_src_data"></altera:port_mapping>
- <altera:port_mapping altera:name="kernel_src_ready" altera:internal="kernel_src_ready"></altera:port_mapping>
- <altera:port_mapping altera:name="kernel_src_valid" altera:internal="kernel_src_valid"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="board_ta2_unb2b_jesd204b.mem" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="jesd204b_miso_rddata" altera:internal="jesd204b_miso_rddata"></altera:port_mapping>
- <altera:port_mapping altera:name="jesd204b_miso_waitrequest" altera:internal="jesd204b_miso_waitrequest"></altera:port_mapping>
- <altera:port_mapping altera:name="jesd204b_mosi_address" altera:internal="jesd204b_mosi_address"></altera:port_mapping>
- <altera:port_mapping altera:name="jesd204b_mosi_rd" altera:internal="jesd204b_mosi_rd"></altera:port_mapping>
- <altera:port_mapping altera:name="jesd204b_mosi_wr" altera:internal="jesd204b_mosi_wr"></altera:port_mapping>
- <altera:port_mapping altera:name="jesd204b_mosi_wrdata" altera:internal="jesd204b_mosi_wrdata"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="serial_rx_arr" altera:internal="board_ta2_unb2b_jesd204b.serial_rx_arr" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="serial_rx_arr" altera:internal="serial_rx_arr"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </ipxact:vendorExtensions>
-</ipxact:component>
\ No newline at end of file
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/freeze_wrapper.v b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/freeze_wrapper.v
index 22508e8dc272134ec9c5843486bf5fad137f5b34..cd44bb01ca6711a2a7a90921d76b3aab6a3799ad 100755
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/freeze_wrapper.v
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/freeze_wrapper.v
@@ -62,6 +62,20 @@ module freeze_wrapper(
output wire [263:0] board_kernel_stream_snk_40GbE_data,
output wire board_kernel_stream_snk_40GbE_valid,
input wire board_kernel_stream_snk_40GbE_ready,
+
+ input wire [263:0] board_kernel_stream_src_40GbE_ring_0_data,
+ input wire board_kernel_stream_src_40GbE_ring_0_valid,
+ output wire board_kernel_stream_src_40GbE_ring_0_ready,
+ output wire [263:0] board_kernel_stream_snk_40GbE_ring_0_data,
+ output wire board_kernel_stream_snk_40GbE_ring_0_valid,
+ input wire board_kernel_stream_snk_40GbE_ring_0_ready,
+
+ input wire [263:0] board_kernel_stream_src_40GbE_ring_1_data,
+ input wire board_kernel_stream_src_40GbE_ring_1_valid,
+ output wire board_kernel_stream_src_40GbE_ring_1_ready,
+ output wire [263:0] board_kernel_stream_snk_40GbE_ring_1_data,
+ output wire board_kernel_stream_snk_40GbE_ring_1_valid,
+ input wire board_kernel_stream_snk_40GbE_ring_1_ready,
output [6:0] board_kernel_register_mem_address,
output board_kernel_register_mem_clken,
@@ -187,28 +201,45 @@ pr_region pr_region_inst
.kernel_cra_debugaccess(board_kernel_cra_debugaccess),
-
.kernel_stream_src_40GbE_data(board_kernel_stream_src_40GbE_data),
.kernel_stream_src_40GbE_ready(board_kernel_stream_src_40GbE_ready),
.kernel_stream_src_40GbE_valid(board_kernel_stream_src_40GbE_valid),
.kernel_stream_snk_40GbE_data(board_kernel_stream_snk_40GbE_data),
.kernel_stream_snk_40GbE_ready(board_kernel_stream_snk_40GbE_ready),
.kernel_stream_snk_40GbE_valid(board_kernel_stream_snk_40GbE_valid),
+
+ .kernel_stream_src_40GbE_ring_0_data(board_kernel_stream_src_40GbE_ring_0_data),
+ .kernel_stream_src_40GbE_ring_0_ready(board_kernel_stream_src_40GbE_ring_0_ready),
+ .kernel_stream_src_40GbE_ring_0_valid(board_kernel_stream_src_40GbE_ring_0_valid),
+ .kernel_stream_snk_40GbE_ring_0_data(board_kernel_stream_snk_40GbE_ring_0_data),
+ .kernel_stream_snk_40GbE_ring_0_ready(board_kernel_stream_snk_40GbE_ring_0_ready),
+ .kernel_stream_snk_40GbE_ring_0_valid(board_kernel_stream_snk_40GbE_ring_0_valid),
+
+ .kernel_stream_src_40GbE_ring_1_data(board_kernel_stream_src_40GbE_ring_1_data),
+ .kernel_stream_src_40GbE_ring_1_ready(board_kernel_stream_src_40GbE_ring_1_ready),
+ .kernel_stream_src_40GbE_ring_1_valid(board_kernel_stream_src_40GbE_ring_1_valid),
+ .kernel_stream_snk_40GbE_ring_1_data(board_kernel_stream_snk_40GbE_ring_1_data),
+ .kernel_stream_snk_40GbE_ring_1_ready(board_kernel_stream_snk_40GbE_ring_1_ready),
+ .kernel_stream_snk_40GbE_ring_1_valid(board_kernel_stream_snk_40GbE_ring_1_valid),
+
.kernel_stream_src_10GbE_data(board_kernel_stream_src_10GbE_data),
.kernel_stream_src_10GbE_ready(board_kernel_stream_src_10GbE_ready),
.kernel_stream_src_10GbE_valid(board_kernel_stream_src_10GbE_valid),
.kernel_stream_snk_10GbE_data(board_kernel_stream_snk_10GbE_data),
.kernel_stream_snk_10GbE_ready(board_kernel_stream_snk_10GbE_ready),
.kernel_stream_snk_10GbE_valid(board_kernel_stream_snk_10GbE_valid),
+
.kernel_stream_src_1GbE_data(board_kernel_stream_src_1GbE_data),
.kernel_stream_src_1GbE_ready(board_kernel_stream_src_1GbE_ready),
.kernel_stream_src_1GbE_valid(board_kernel_stream_src_1GbE_valid),
.kernel_stream_snk_1GbE_data(board_kernel_stream_snk_1GbE_data),
.kernel_stream_snk_1GbE_ready(board_kernel_stream_snk_1GbE_ready),
.kernel_stream_snk_1GbE_valid(board_kernel_stream_snk_1GbE_valid),
+
.kernel_stream_src_ADC_data(board_kernel_stream_src_ADC_data),
.kernel_stream_src_ADC_ready(board_kernel_stream_src_ADC_ready),
.kernel_stream_src_ADC_valid(board_kernel_stream_src_ADC_valid),
+
.kernel_register_mem_address(board_kernel_register_mem_address),
.kernel_register_mem_clken(board_kernel_register_mem_clken),
.kernel_register_mem_chipselect(board_kernel_register_mem_chipselect),
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/pr_region.v b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/pr_region.v
index f0ea3b6263d151822fbc9833ec6106099fcb6893..3b9130301f30ecf2130656d039c0a91022ba6be3 100755
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/pr_region.v
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/pr_region.v
@@ -66,7 +66,21 @@ module pr_region (
output wire kernel_stream_src_40GbE_ready,
output wire [263:0] kernel_stream_snk_40GbE_data,
output wire kernel_stream_snk_40GbE_valid,
- input wire kernel_stream_snk_40GbE_ready
+ input wire kernel_stream_snk_40GbE_ready,
+
+ input wire [263:0] kernel_stream_src_40GbE_ring_0_data,
+ input wire kernel_stream_src_40GbE_ring_0_valid,
+ output wire kernel_stream_src_40GbE_ring_0_ready,
+ output wire [263:0] kernel_stream_snk_40GbE_ring_0_data,
+ output wire kernel_stream_snk_40GbE_ring_0_valid,
+ input wire kernel_stream_snk_40GbE_ring_0_ready,
+
+ input wire [263:0] kernel_stream_src_40GbE_ring_1_data,
+ input wire kernel_stream_src_40GbE_ring_1_valid,
+ output wire kernel_stream_src_40GbE_ring_1_ready,
+ output wire [263:0] kernel_stream_snk_40GbE_ring_1_data,
+ output wire kernel_stream_snk_40GbE_ring_1_valid,
+ input wire kernel_stream_snk_40GbE_ring_1_ready
// input wire kernel_mem0_waitrequest,
@@ -179,6 +193,24 @@ kernel_system kernel_system_inst
.kernel_output_40GbE_valid(kernel_stream_snk_40GbE_valid),
+ .kernel_input_40GbE_ring_0_data(kernel_stream_src_40GbE_ring_0_data),
+ .kernel_input_40GbE_ring_0_ready(kernel_stream_src_40GbE_ring_0_ready),
+ .kernel_input_40GbE_ring_0_valid(kernel_stream_src_40GbE_ring_0_valid),
+
+ .kernel_output_40GbE_ring_0_data(kernel_stream_snk_40GbE_ring_0_data),
+ .kernel_output_40GbE_ring_0_ready(kernel_stream_snk_40GbE_ring_0_ready),
+ .kernel_output_40GbE_ring_0_valid(kernel_stream_snk_40GbE_ring_0_valid),
+
+
+ .kernel_input_40GbE_ring_1_data(kernel_stream_src_40GbE_ring_1_data),
+ .kernel_input_40GbE_ring_1_ready(kernel_stream_src_40GbE_ring_1_ready),
+ .kernel_input_40GbE_ring_1_valid(kernel_stream_src_40GbE_ring_1_valid),
+
+ .kernel_output_40GbE_ring_1_data(kernel_stream_snk_40GbE_ring_1_data),
+ .kernel_output_40GbE_ring_1_ready(kernel_stream_snk_40GbE_ring_1_ready),
+ .kernel_output_40GbE_ring_1_valid(kernel_stream_snk_40GbE_ring_1_valid),
+
+
.kernel_input_10GbE_data(kernel_stream_src_10GbE_data),
.kernel_input_10GbE_ready(kernel_stream_src_10GbE_ready),
.kernel_input_10GbE_valid(kernel_stream_src_10GbE_valid),
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
index 5bde0464e46edc69ff967603b54234076eb4476d..34f7db003451ce207bfa890736f1bcd08233ac8a 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
@@ -200,7 +200,7 @@ BEGIN
dp_latency_adapter_tx_snk_in.valid <= kernel_snk_valid;
kernel_snk_ready <= dp_latency_adapter_tx_snk_out.ready; -- Flow control towards source (kernel)
- rx_status <= dp_latency_adapter_tx_snk_out.xon;
+ rx_status <= dp_xonoff_src_in.xon; -- use xonoff_src_in for status as xonoff_snk_out is always '1'
tx_serial_r <= unb2_board_front_io_serial_tx_arr(0);
unb2_board_front_io_serial_rx_arr(0) <= rx_serial_r;
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl
deleted file mode 100644
index 072933051d7ad7c7c27a27b81aa053ee01f584ac..0000000000000000000000000000000000000000
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl
+++ /dev/null
@@ -1,200 +0,0 @@
-# TCL File Generated by Component Editor 18.0
-# Mon Jan 13 11:25:28 CET 2020
-# DO NOT MODIFY
-
-
-#
-# ta2_unb2b_10GbE "ta2_unb2b_10GbE" v1.0
-# 2020.01.13.11:25:28
-#
-#
-
-#
-# request TCL package from ACDS 18.0
-#
-package require -exact qsys 18.0
-
-
-#
-# module ta2_unb2b_10GbE
-#
-set_module_property DESCRIPTION ""
-set_module_property NAME ta2_unb2b_10GbE
-set_module_property VERSION 1.0
-set_module_property INTERNAL false
-set_module_property OPAQUE_ADDRESS_MAP true
-set_module_property AUTHOR ""
-set_module_property DISPLAY_NAME ta2_unb2b_10GbE
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property EDITABLE true
-set_module_property REPORT_TO_TALKBACK false
-set_module_property ALLOW_GREYBOX_GENERATION false
-set_module_property REPORT_HIERARCHY false
-
-
-#
-# file sets
-#
-add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL ta2_unb2b_10GbE_ip_wrapper
-set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file ta2_unb2b_10GbE_ip_wrapper.vhd VHDL PATH ta2_unb2b_10GbE_ip_wrapper.vhd TOP_LEVEL_FILE
-
-
-#
-# parameters
-#
-
-
-#
-# display items
-#
-
-
-#
-# connection point kernel_snk
-#
-add_interface kernel_snk avalon_streaming end
-set_interface_property kernel_snk associatedClock kernel_clk
-set_interface_property kernel_snk associatedReset kernel_reset
-set_interface_property kernel_snk dataBitsPerSymbol 8
-set_interface_property kernel_snk errorDescriptor ""
-set_interface_property kernel_snk firstSymbolInHighOrderBits true
-set_interface_property kernel_snk maxChannel 0
-set_interface_property kernel_snk readyAllowance 0
-set_interface_property kernel_snk readyLatency 0
-set_interface_property kernel_snk ENABLED true
-set_interface_property kernel_snk EXPORT_OF ""
-set_interface_property kernel_snk PORT_NAME_MAP ""
-set_interface_property kernel_snk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_snk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_snk kernel_snk_data data Input 72
-add_interface_port kernel_snk kernel_snk_ready ready Output 1
-add_interface_port kernel_snk kernel_snk_valid valid Input 1
-
-
-#
-# connection point kernel_src
-#
-add_interface kernel_src avalon_streaming start
-set_interface_property kernel_src associatedClock kernel_clk
-set_interface_property kernel_src associatedReset kernel_reset
-set_interface_property kernel_src dataBitsPerSymbol 8
-set_interface_property kernel_src errorDescriptor ""
-set_interface_property kernel_src firstSymbolInHighOrderBits true
-set_interface_property kernel_src maxChannel 0
-set_interface_property kernel_src readyAllowance 0
-set_interface_property kernel_src readyLatency 0
-set_interface_property kernel_src ENABLED true
-set_interface_property kernel_src EXPORT_OF ""
-set_interface_property kernel_src PORT_NAME_MAP ""
-set_interface_property kernel_src CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_src SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_src kernel_src_data data Output 72
-add_interface_port kernel_src kernel_src_ready ready Input 1
-add_interface_port kernel_src kernel_src_valid valid Output 1
-
-
-#
-# connection point kernel_clk
-#
-add_interface kernel_clk clock end
-set_interface_property kernel_clk ENABLED true
-set_interface_property kernel_clk EXPORT_OF ""
-set_interface_property kernel_clk PORT_NAME_MAP ""
-set_interface_property kernel_clk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_clk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_clk kernel_clk clk Input 1
-
-
-#
-# connection point refclk
-#
-add_interface refclk clock end
-set_interface_property refclk ENABLED true
-set_interface_property refclk EXPORT_OF ""
-set_interface_property refclk PORT_NAME_MAP ""
-set_interface_property refclk CMSIS_SVD_VARIABLES ""
-set_interface_property refclk SVD_ADDRESS_GROUP ""
-
-add_interface_port refclk clk_ref_r clk Input 1
-
-
-#
-# connection point rx_serial_data
-#
-add_interface rx_serial_data conduit end
-set_interface_property rx_serial_data associatedClock ""
-set_interface_property rx_serial_data associatedReset ""
-set_interface_property rx_serial_data ENABLED true
-set_interface_property rx_serial_data EXPORT_OF ""
-set_interface_property rx_serial_data PORT_NAME_MAP ""
-set_interface_property rx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property rx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_serial_data rx_serial_r conduit Input 1
-
-
-#
-# connection point tx_serial_data
-#
-add_interface tx_serial_data conduit end
-set_interface_property tx_serial_data associatedClock ""
-set_interface_property tx_serial_data associatedReset ""
-set_interface_property tx_serial_data ENABLED true
-set_interface_property tx_serial_data EXPORT_OF ""
-set_interface_property tx_serial_data PORT_NAME_MAP ""
-set_interface_property tx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property tx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port tx_serial_data tx_serial_r conduit Output 1
-
-
-#
-# connection point config_reset
-#
-add_interface config_reset reset end
-set_interface_property config_reset associatedClock ""
-set_interface_property config_reset synchronousEdges NONE
-set_interface_property config_reset ENABLED true
-set_interface_property config_reset EXPORT_OF ""
-set_interface_property config_reset PORT_NAME_MAP ""
-set_interface_property config_reset CMSIS_SVD_VARIABLES ""
-set_interface_property config_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port config_reset config_reset reset Input 1
-
-
-#
-# connection point kernel_reset
-#
-add_interface kernel_reset reset end
-set_interface_property kernel_reset associatedClock kernel_clk
-set_interface_property kernel_reset synchronousEdges DEASSERT
-set_interface_property kernel_reset ENABLED true
-set_interface_property kernel_reset EXPORT_OF ""
-set_interface_property kernel_reset PORT_NAME_MAP ""
-set_interface_property kernel_reset CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_reset kernel_reset reset Input 1
-
-
-#
-# connection point rx_status
-#
-add_interface rx_status conduit end
-set_interface_property rx_status associatedClock ""
-set_interface_property rx_status associatedReset ""
-set_interface_property rx_status ENABLED true
-set_interface_property rx_status EXPORT_OF ""
-set_interface_property rx_status PORT_NAME_MAP ""
-set_interface_property rx_status CMSIS_SVD_VARIABLES ""
-set_interface_property rx_status SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_status rx_status rx_status Output 1
-
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl~ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl~
deleted file mode 100644
index ea4cf697bb2be70bd74b118f3e48c34e5c501cc5..0000000000000000000000000000000000000000
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl~
+++ /dev/null
@@ -1,200 +0,0 @@
-# TCL File Generated by Component Editor 18.0
-# Mon Jan 13 09:28:21 CET 2020
-# DO NOT MODIFY
-
-
-#
-# ta2_unb2b_10GbE "ta2_unb2b_10GbE" v1.0
-# 2020.01.13.09:28:21
-#
-#
-
-#
-# request TCL package from ACDS 18.0
-#
-package require -exact qsys 18.0
-
-
-#
-# module ta2_unb2b_10GbE
-#
-set_module_property DESCRIPTION ""
-set_module_property NAME ta2_unb2b_10GbE
-set_module_property VERSION 1.0
-set_module_property INTERNAL false
-set_module_property OPAQUE_ADDRESS_MAP true
-set_module_property AUTHOR ""
-set_module_property DISPLAY_NAME ta2_unb2b_10GbE
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property EDITABLE true
-set_module_property REPORT_TO_TALKBACK false
-set_module_property ALLOW_GREYBOX_GENERATION false
-set_module_property REPORT_HIERARCHY false
-
-
-#
-# file sets
-#
-add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL ta2_unb2b_10GbE_ip_wrapper
-set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file ta2_unb2b_10GbE_ip_wrapper.vhd VHDL PATH ta2_unb2b_10GbE_ip_wrapper.vhd TOP_LEVEL_FILE
-
-
-#
-# parameters
-#
-
-
-#
-# display items
-#
-
-
-#
-# connection point kernel_snk
-#
-add_interface kernel_snk avalon_streaming end
-set_interface_property kernel_snk associatedClock kernel_clk
-set_interface_property kernel_snk associatedReset kernel_reset
-set_interface_property kernel_snk dataBitsPerSymbol 8
-set_interface_property kernel_snk errorDescriptor ""
-set_interface_property kernel_snk firstSymbolInHighOrderBits true
-set_interface_property kernel_snk maxChannel 0
-set_interface_property kernel_snk readyAllowance 0
-set_interface_property kernel_snk readyLatency 0
-set_interface_property kernel_snk ENABLED true
-set_interface_property kernel_snk EXPORT_OF ""
-set_interface_property kernel_snk PORT_NAME_MAP ""
-set_interface_property kernel_snk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_snk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_snk kernel_snk_data data Input 72
-add_interface_port kernel_snk kernel_snk_ready ready Output 1
-add_interface_port kernel_snk kernel_snk_valid valid Input 1
-
-
-#
-# connection point kernel_src
-#
-add_interface kernel_src avalon_streaming start
-set_interface_property kernel_src associatedClock kernel_clk
-set_interface_property kernel_src associatedReset kernel_reset
-set_interface_property kernel_src dataBitsPerSymbol 8
-set_interface_property kernel_src errorDescriptor ""
-set_interface_property kernel_src firstSymbolInHighOrderBits true
-set_interface_property kernel_src maxChannel 0
-set_interface_property kernel_src readyAllowance 0
-set_interface_property kernel_src readyLatency 0
-set_interface_property kernel_src ENABLED true
-set_interface_property kernel_src EXPORT_OF ""
-set_interface_property kernel_src PORT_NAME_MAP ""
-set_interface_property kernel_src CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_src SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_src kernel_src_data data Output 72
-add_interface_port kernel_src kernel_src_ready ready Input 1
-add_interface_port kernel_src kernel_src_valid valid Output 1
-
-
-#
-# connection point kernel_clk
-#
-add_interface kernel_clk clock end
-set_interface_property kernel_clk ENABLED true
-set_interface_property kernel_clk EXPORT_OF ""
-set_interface_property kernel_clk PORT_NAME_MAP ""
-set_interface_property kernel_clk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_clk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_clk kernel_clk clk Input 1
-
-
-#
-# connection point refclk
-#
-add_interface refclk clock end
-set_interface_property refclk ENABLED true
-set_interface_property refclk EXPORT_OF ""
-set_interface_property refclk PORT_NAME_MAP ""
-set_interface_property refclk CMSIS_SVD_VARIABLES ""
-set_interface_property refclk SVD_ADDRESS_GROUP ""
-
-add_interface_port refclk clk_ref_r clk Input 1
-
-
-#
-# connection point rx_serial_data
-#
-add_interface rx_serial_data conduit end
-set_interface_property rx_serial_data associatedClock ""
-set_interface_property rx_serial_data associatedReset ""
-set_interface_property rx_serial_data ENABLED true
-set_interface_property rx_serial_data EXPORT_OF ""
-set_interface_property rx_serial_data PORT_NAME_MAP ""
-set_interface_property rx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property rx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_serial_data rx_serial_r conduit Input 1
-
-
-#
-# connection point tx_serial_data
-#
-add_interface tx_serial_data conduit end
-set_interface_property tx_serial_data associatedClock ""
-set_interface_property tx_serial_data associatedReset ""
-set_interface_property tx_serial_data ENABLED true
-set_interface_property tx_serial_data EXPORT_OF ""
-set_interface_property tx_serial_data PORT_NAME_MAP ""
-set_interface_property tx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property tx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port tx_serial_data tx_serial_r conduit Output 1
-
-
-#
-# connection point config_reset
-#
-add_interface config_reset reset end
-set_interface_property config_reset associatedClock ""
-set_interface_property config_reset synchronousEdges NONE
-set_interface_property config_reset ENABLED true
-set_interface_property config_reset EXPORT_OF ""
-set_interface_property config_reset PORT_NAME_MAP ""
-set_interface_property config_reset CMSIS_SVD_VARIABLES ""
-set_interface_property config_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port config_reset config_reset reset Input 1
-
-
-#
-# connection point kernel_reset
-#
-add_interface kernel_reset reset end
-set_interface_property kernel_reset associatedClock kernel_clk
-set_interface_property kernel_reset synchronousEdges DEASSERT
-set_interface_property kernel_reset ENABLED true
-set_interface_property kernel_reset EXPORT_OF ""
-set_interface_property kernel_reset PORT_NAME_MAP ""
-set_interface_property kernel_reset CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_reset kernel_reset reset Input 1
-
-
-#
-# connection point rx_status
-#
-add_interface rx_status conduit end
-set_interface_property rx_status associatedClock ""
-set_interface_property rx_status associatedReset ""
-set_interface_property rx_status ENABLED true
-set_interface_property rx_status EXPORT_OF ""
-set_interface_property rx_status PORT_NAME_MAP ""
-set_interface_property rx_status CMSIS_SVD_VARIABLES ""
-set_interface_property rx_status SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_status rx_status rx_status Output 1
-
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_ip_wrapper.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_ip_wrapper.vhd
deleted file mode 100644
index b2c09951e8034f0b8f2c32d431e902b227e38c12..0000000000000000000000000000000000000000
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_ip_wrapper.vhd
+++ /dev/null
@@ -1,114 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2019
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Author:
--- . Reinier van der Walle
--- Purpose:
--- . Instantiates ta2_unb2b_10GbE component
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY ta2_unb2b_10GbE_ip_wrapper IS
- PORT (
- --config_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
- config_reset : IN STD_LOGIC;
-
- clk_ref_r : IN STD_LOGIC; -- 644.53125MHz 10G MAC reference clock
-
- tx_serial_r : OUT STD_LOGIC; -- Serial TX lanes towards QSFP cage
- rx_serial_r : IN STD_LOGIC; -- Serial RX lanes from QSFP cage
-
- kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
- kernel_reset : IN STD_LOGIC;
-
- kernel_src_data : OUT STD_LOGIC_VECTOR(71 DOWNTO 0); -- RX Data to kernel
- kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
- kernel_src_ready : IN STD_LOGIC; -- Flow control from kernel
-
- kernel_snk_data : IN STD_LOGIC_VECTOR(71 DOWNTO 0); -- TX Data from kernel
- kernel_snk_valid : IN STD_LOGIC; -- TX data valid signal from kernel
- kernel_snk_ready : OUT STD_LOGIC; -- Flow control towards kernel
-
- rx_status : OUT STD_LOGIC -- RX status
- );
-END ta2_unb2b_10GbE_ip_wrapper;
-
-
-ARCHITECTURE str OF ta2_unb2b_10GbE_ip_wrapper IS
- ----------------------------------------------------------------------------
- -- ta2_unb2b_10GbE Component
- ----------------------------------------------------------------------------
- COMPONENT ta2_unb2b_10GbE IS
- PORT (
- --config_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
- config_reset : IN STD_LOGIC;
-
- clk_ref_r : IN STD_LOGIC; -- 644.53125MHz 10G MAC reference clock
-
- tx_serial_r : OUT STD_LOGIC; -- Serial TX lanes towards QSFP cage
- rx_serial_r : IN STD_LOGIC; -- Serial RX lanes from QSFP cage
-
- kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
- kernel_reset : IN STD_LOGIC;
-
- kernel_src_data : OUT STD_LOGIC_VECTOR(71 DOWNTO 0); -- RX Data to kernel
- kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
- kernel_src_ready : IN STD_LOGIC; -- Flow control from kernel
-
- kernel_snk_data : IN STD_LOGIC_VECTOR(71 DOWNTO 0); -- TX Data from kernel
- kernel_snk_valid : IN STD_LOGIC; -- TX data valid signal from kernel
- kernel_snk_ready : OUT STD_LOGIC; -- Flow control towards kernel
-
- rx_status : OUT STD_LOGIC -- RX status
- );
- END COMPONENT ta2_unb2b_10GbE;
-
-BEGIN
-
- u_ta2_unb2b_10GbE : ta2_unb2b_10GbE
- PORT MAP (
- --config_clk => config_clk,
- config_reset => config_reset,
-
- clk_ref_r => clk_ref_r,
-
- tx_serial_r => tx_serial_r,
- rx_serial_r => rx_serial_r,
-
- kernel_clk => kernel_clk,
- kernel_reset => kernel_reset,
-
- kernel_src_data => kernel_src_data,
- kernel_src_valid => kernel_src_valid,
- kernel_src_ready => kernel_src_ready,
-
- kernel_snk_data => kernel_snk_data,
- kernel_snk_valid => kernel_snk_valid,
- kernel_snk_ready => kernel_snk_ready,
-
- rx_status => rx_status
-
- );
-
-
-
-END str;
-
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd
index 048f57b0dcd2cbdc2d9c870312cd1fc3f58249fc..79c186c7754c16d066413a1dbe84f3d8a6042518 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd
@@ -56,22 +56,11 @@ ENTITY ta2_unb2b_1GbE_mc IS
st_rst : IN STD_LOGIC;
-- eth1g UDP streaming ports
- udp_tx_sosi_data : OUT STD_LOGIC_VECTOR(5*c_byte_w -1 DOWNTO 0);
- udp_tx_sosi_valid : OUT STD_LOGIC;
- udp_tx_sosi_sop : OUT STD_LOGIC;
- udp_tx_sosi_eop : OUT STD_LOGIC;
- udp_tx_sosi_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- udp_tx_siso_ready : IN STD_LOGIC;
- udp_tx_siso_xon : IN STD_LOGIC;
+ udp_tx_sosi : OUT t_dp_sosi;
+ udp_tx_siso : IN t_dp_siso;
+ udp_rx_sosi : IN t_dp_sosi;
+ udp_rx_siso : OUT t_dp_siso;
- udp_rx_sosi_data : IN STD_LOGIC_VECTOR(5*c_byte_w -1 DOWNTO 0);
- udp_rx_sosi_valid : IN STD_LOGIC;
- udp_rx_sosi_sop : IN STD_LOGIC;
- udp_rx_sosi_eop : IN STD_LOGIC;
- udp_rx_sosi_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- udp_rx_siso_ready : OUT STD_LOGIC;
- udp_rx_siso_xon : OUT STD_LOGIC;
-
kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
kernel_reset : IN STD_LOGIC;
@@ -109,31 +98,8 @@ ARCHITECTURE str OF ta2_unb2b_1GbE_mc IS
SIGNAL dp_xonoff_src_out : t_dp_sosi;
SIGNAL dp_xonoff_src_in : t_dp_siso;
- SIGNAL udp_tx_sosi : t_dp_sosi;
- SIGNAL udp_tx_siso : t_dp_siso;
- SIGNAL udp_rx_sosi : t_dp_sosi;
- SIGNAL udp_rx_siso : t_dp_siso;
-
BEGIN
- udp_tx_sosi_data <= udp_tx_sosi.data(39 DOWNTO 0);
- udp_tx_sosi_valid <= udp_tx_sosi.valid;
- udp_tx_sosi_sop <= udp_tx_sosi.sop;
- udp_tx_sosi_eop <= udp_tx_sosi.eop;
- udp_tx_sosi_empty <= udp_tx_sosi.empty(1 DOWNTO 0);
-
- udp_tx_siso.ready <= udp_tx_siso_ready;
- udp_tx_siso.xon <= udp_tx_siso_xon;
-
- udp_rx_sosi.data(39 DOWNTO 0) <= udp_rx_sosi_data;
- udp_rx_sosi.valid <= udp_rx_sosi_valid;
- udp_rx_sosi.sop <= udp_rx_sosi_sop;
- udp_rx_sosi.eop <= udp_rx_sosi_eop;
- udp_rx_sosi.empty(1 DOWNTO 0) <= udp_rx_sosi_empty;
-
- udp_rx_siso_ready <= udp_rx_siso.ready;
- udp_rx_siso_xon <= udp_rx_siso.xon;
-
-------------------------------------------------------
-- Mapping Data from OpenCL kernel to 1GbE Interface --
-------------------------------------------------------
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/hdllib.cfg b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..e51ddb0cc19ca1151b99ee4114e20554c1975555
--- /dev/null
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/hdllib.cfg
@@ -0,0 +1,32 @@
+hdl_lib_name = ta2_unb2b_40GbE
+hdl_library_clause_name = ta2_unb2b_40GbE_lib
+hdl_lib_uses_synth = common technology dp
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+hdl_lib_include_ip =
+
+synth_files =
+ ta2_unb2b_40GbE.vhd
+test_bench_files =
+
+regression_test_vhdl =
+
+[modelsim_project_file]
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_sdc_files =
+ $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+
+
+quartus_vhdl_files =
+
+quartus_qip_files =
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
index 83f88511933ac8ca1ce3f23600a6d8b1f5aba987..0bbee7f131573e9e8c164bf488c4d7185b05ed96 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
@@ -55,28 +55,27 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-ENTITY ta2_unb2b_40GbE IS
+ENTITY ta2_unb2b_40GbE IS
+ GENERIC (
+ g_nof_mac : NATURAL := 1
+ );
PORT (
config_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
config_reset : IN STD_LOGIC;
clk_ref_r : IN STD_LOGIC; -- 644.53125MHz 40G MAC reference clock
- tx_serial_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- Serial TX lanes towards QSFP cage
- rx_serial_r : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Serial RX lanes from QSFP cage
+ tx_serial_r : OUT STD_LOGIC_VECTOR(4*g_nof_mac-1 DOWNTO 0); -- Serial TX lanes towards QSFP cage
+ rx_serial_r : IN STD_LOGIC_VECTOR(4*g_nof_mac-1 DOWNTO 0); -- Serial RX lanes from QSFP cage
kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
kernel_reset : IN STD_LOGIC;
- kernel_src_data : OUT STD_LOGIC_VECTOR(263 DOWNTO 0); -- RX Data to kernel
- kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
- kernel_src_ready : IN STD_LOGIC; -- Flow control from kernel
-
- kernel_snk_data : IN STD_LOGIC_VECTOR(263 DOWNTO 0); -- TX Data from kernel
- kernel_snk_valid : IN STD_LOGIC; -- TX data valid signal from kernel
- kernel_snk_ready : OUT STD_LOGIC; -- Flow control towards kernel
-
- rx_status : OUT STD_LOGIC -- RX status
+ src_out_arr : OUT t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ src_in_arr : IN t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
+ snk_out_arr : OUT t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
+ snk_in_arr : IN t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0)
+
);
END ta2_unb2b_40GbE;
@@ -93,74 +92,64 @@ ARCHITECTURE str OF ta2_unb2b_40GbE IS
----------------------------------------------------------------------------
-- Reset signals
----------------------------------------------------------------------------
- SIGNAL rst_txmac : STD_LOGIC;
- SIGNAL rst_rxmac : STD_LOGIC;
+ SIGNAL rst_txmac_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0);
+ SIGNAL rst_rxmac_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- dp_xonoff
----------------------------------------------------------------------------
- SIGNAL dp_xonoff_src_out : t_dp_sosi;
- SIGNAL dp_xonoff_src_in : t_dp_siso;
+ SIGNAL dp_xonoff_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_xonoff_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- Latency adapter tx a
----------------------------------------------------------------------------
- SIGNAL dp_latency_adapter_tx_a_src_out : t_dp_sosi;
- SIGNAL dp_latency_adapter_tx_a_src_in : t_dp_siso;
- SIGNAL dp_latency_adapter_tx_a_snk_in : t_dp_sosi;
- SIGNAL dp_latency_adapter_tx_a_snk_out : t_dp_siso;
+ SIGNAL dp_latency_adapter_tx_a_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_tx_a_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_tx_a_snk_in_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_tx_a_snk_out_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- Latency adapter tx b
----------------------------------------------------------------------------
- SIGNAL dp_latency_adapter_tx_b_src_out : t_dp_sosi;
- SIGNAL dp_latency_adapter_tx_b_src_in : t_dp_siso;
+ SIGNAL dp_latency_adapter_tx_b_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_tx_b_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- Latency adapter rx
----------------------------------------------------------------------------
- SIGNAL dp_latency_adapter_rx_src_out : t_dp_sosi;
- SIGNAL dp_latency_adapter_rx_src_in : t_dp_siso;
+ SIGNAL dp_latency_adapter_rx_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_rx_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- TX FIFO
----------------------------------------------------------------------------
- SIGNAL dp_fifo_fill_eop_src_out : t_dp_sosi;
- SIGNAL dp_fifo_fill_eop_src_in : t_dp_siso;
+ SIGNAL dp_fifo_fill_eop_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_fifo_fill_eop_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- 40G MAC IP
----------------------------------------------------------------------------
- SIGNAL serial_clk : STD_LOGIC;
- SIGNAL serial_clk_arr : STD_LOGIC_VECTOR(3 DOWNTO 0);
+ SIGNAL serial_clk_2arr : t_slv_4_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL serial_clk_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0);
- SIGNAL pll_locked : STD_LOGIC;
+ SIGNAL pll_locked_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0);
- SIGNAL tx_lanes_stable : STD_LOGIC;
- SIGNAL rx_pcs_ready : STD_LOGIC;
+ SIGNAL rx_pcs_ready_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0);
- SIGNAL clk_txmac : STD_LOGIC; -- MAC + PCS clock - at least 312.5Mhz
- SIGNAL clk_rxmac : STD_LOGIC; -- MAC + PCS clock - at least 312.5Mhz
+ SIGNAL clk_txmac_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0); -- MAC + PCS clock - at least 312.5Mhz
+ SIGNAL clk_rxmac_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0); -- MAC + PCS clock - at least 312.5Mhz
- SIGNAL l4_tx_data : STD_LOGIC_VECTOR(255 DOWNTO 0);
- SIGNAL l4_tx_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
- SIGNAL l4_tx_endofpacket : STD_LOGIC;
- SIGNAL l4_tx_ready : STD_LOGIC;
- SIGNAL l4_tx_startofpacket : STD_LOGIC;
- SIGNAL l4_tx_valid : STD_LOGIC;
- SIGNAL l4_rx_data : STD_LOGIC_VECTOR(255 DOWNTO 0);
- SIGNAL l4_rx_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
- SIGNAL l4_rx_endofpacket : STD_LOGIC;
- SIGNAL l4_rx_startofpacket : STD_LOGIC;
- SIGNAL l4_rx_valid : STD_LOGIC;
+ SIGNAL l4_tx_sosi_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL l4_tx_siso_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL l4_rx_sosi_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL l4_rx_siso_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- RX FIFO
----------------------------------------------------------------------------
- SIGNAL dp_fifo_dc_snk_in : t_dp_sosi;
-
- SIGNAL dp_fifo_dc_src_out : t_dp_sosi;
- SIGNAL dp_fifo_dc_src_in : t_dp_siso;
+ SIGNAL dp_fifo_dc_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_fifo_dc_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- ATX PLL Component
@@ -284,333 +273,321 @@ ARCHITECTURE str OF ta2_unb2b_40GbE IS
BEGIN
- ----------------------------------------------------------------------------
- -- Data mapping
- ----------------------------------------------------------------------------
- -- Reverse byte order
- gen_tx_bytes: FOR I IN 0 TO 31 GENERATE
- dp_latency_adapter_tx_a_snk_in.data(8*(32-I) -1 DOWNTO 8*(31-I)) <= kernel_snk_data(8*(I+1) -1 DOWNTO 8*I);
- END GENERATE;
+ gen_mac: FOR mac IN 0 TO g_nof_mac-1 GENERATE
+ ----------------------------------------------------------------------------
+ -- Data mapping
+ ----------------------------------------------------------------------------
+ -- Reverse byte order
+ gen_tx_bytes: FOR I IN 0 TO 31 GENERATE
+ dp_latency_adapter_tx_a_snk_in_arr(mac).data(8*(32-I) -1 DOWNTO 8*(31-I)) <= snk_in_arr(mac).data(8*(I+1) -1 DOWNTO 8*I);
+ END GENERATE;
+
+ -- Assign correct data fields to control signals.
+ dp_latency_adapter_tx_a_snk_in_arr(mac).sop <= snk_in_arr(mac).data(256);
+ dp_latency_adapter_tx_a_snk_in_arr(mac).eop <= snk_in_arr(mac).data(257);
+ dp_latency_adapter_tx_a_snk_in_arr(mac).empty(4 DOWNTO 0) <= snk_in_arr(mac).data(263 DOWNTO 259);
+ dp_latency_adapter_tx_a_snk_in_arr(mac).valid <= snk_in_arr(mac).valid;
+ snk_out_arr(mac).ready <= dp_latency_adapter_tx_a_snk_out_arr(mac).ready; -- Flow control towards source (kernel)
+ snk_out_arr(mac).xon <= rx_pcs_ready_arr(mac);
+
+ ----------------------------------------------------------------------------
+ -- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (downstream).
+ ----------------------------------------------------------------------------
+ u_dp_latency_adapter_tx_a : ENTITY dp_lib.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 0,
+ g_out_latency => 1
+ )
+ PORT MAP (
+ clk => kernel_clk,
+ rst => kernel_reset,
- -- Assign correct data fields to control signals.
- dp_latency_adapter_tx_a_snk_in.sop <= kernel_snk_data(256);
- dp_latency_adapter_tx_a_snk_in.eop <= kernel_snk_data(257);
- dp_latency_adapter_tx_a_snk_in.empty(4 DOWNTO 0) <= kernel_snk_data(263 DOWNTO 259);
+ snk_in => dp_latency_adapter_tx_a_snk_in_arr(mac),
+ snk_out => dp_latency_adapter_tx_a_snk_out_arr(mac),
- dp_latency_adapter_tx_a_snk_in.valid <= kernel_snk_valid;
- kernel_snk_ready <= dp_latency_adapter_tx_a_snk_out.ready; -- Flow control towards source (kernel)
+ src_out => dp_latency_adapter_tx_a_src_out_arr(mac),
+ src_in => dp_latency_adapter_tx_a_src_in_arr(mac)
+ );
+
+ ----------------------------------------------------------------------------
+ -- dp_xonoff: discard all TX frames until 40G MAC TX side is ready
+ ----------------------------------------------------------------------------
+ u_dp_xonoff : ENTITY dp_lib.dp_xonoff
+ PORT MAP (
+ clk => kernel_clk,
+ rst => kernel_reset,
+ in_sosi => dp_latency_adapter_tx_a_src_out_arr(mac),
+ in_siso => dp_latency_adapter_tx_a_src_in_arr(mac),
- ----------------------------------------------------------------------------
- -- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (downstream).
- ----------------------------------------------------------------------------
- u_dp_latency_adapter_tx_a : ENTITY dp_lib.dp_latency_adapter
- GENERIC MAP (
- g_in_latency => 0,
- g_out_latency => 1
- )
- PORT MAP (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_latency_adapter_tx_a_snk_in,
- snk_out => dp_latency_adapter_tx_a_snk_out,
-
- src_out => dp_latency_adapter_tx_a_src_out,
- src_in => dp_latency_adapter_tx_a_src_in
- );
-
- ----------------------------------------------------------------------------
- -- dp_xonoff: discard all TX frames until 40G MAC TX side is ready
- ----------------------------------------------------------------------------
- u_dp_xonoff : ENTITY dp_lib.dp_xonoff
- PORT MAP (
- clk => kernel_clk,
- rst => kernel_reset,
+ out_sosi => dp_xonoff_src_out_arr(mac),
+ out_siso => dp_xonoff_src_in_arr(mac) -- flush control via out_siso.xon
+ );
- in_sosi => dp_latency_adapter_tx_a_src_out,
- in_siso => dp_latency_adapter_tx_a_src_in,
+ ----------------------------------------------------------------------------
+ -- TX FIFO
+ ----------------------------------------------------------------------------
+ u_dp_fifo_fill_eop : ENTITY dp_lib.dp_fifo_fill_eop
+ GENERIC MAP (
+ g_data_w => c_data_w,
+ g_use_dual_clock => TRUE,
+ g_empty_w => 8,
+ g_use_empty => TRUE,
+ g_use_bsn => FALSE,
+ g_bsn_w => 64,
+ g_use_channel => FALSE,
+ g_use_sync => FALSE,
+ g_fifo_size => c_tx_fifo_size,
+ g_fifo_fill => c_tx_fifo_fill
+ )
+ PORT MAP (
+ wr_clk => kernel_clk,
+ wr_rst => kernel_reset,
- out_sosi => dp_xonoff_src_out,
- out_siso => dp_xonoff_src_in -- flush control via out_siso.xon
- );
+ rd_clk => clk_txmac_arr(mac),
+ rd_rst => rst_txmac_arr(mac),
- ----------------------------------------------------------------------------
- -- TX FIFO
- ----------------------------------------------------------------------------
- u_dp_fifo_fill_eop : ENTITY dp_lib.dp_fifo_fill_eop
- GENERIC MAP (
- g_data_w => c_data_w,
- g_use_dual_clock => TRUE,
- g_empty_w => 8,
- g_use_empty => TRUE,
- g_use_bsn => FALSE,
- g_bsn_w => 64,
- g_use_channel => FALSE,
- g_use_sync => FALSE,
- g_fifo_size => c_tx_fifo_size,
- g_fifo_fill => c_tx_fifo_fill
- )
- PORT MAP (
- wr_clk => kernel_clk,
- wr_rst => kernel_reset,
-
- rd_clk => clk_txmac,
- rd_rst => rst_txmac,
-
- snk_in => dp_xonoff_src_out,
- snk_out => dp_xonoff_src_in,
-
- src_out => dp_fifo_fill_eop_src_out,
- src_in => dp_fifo_fill_eop_src_in
- );
+ snk_in => dp_xonoff_src_out_arr(mac),
+ snk_out => dp_xonoff_src_in_arr(mac),
- ----------------------------------------------------------------------------
- -- Latency adapter: adapt RL=1 (upstream) to RL=0 (MAC TX interface).
- ----------------------------------------------------------------------------
- u_dp_latency_adapter_tx_b : ENTITY dp_lib.dp_latency_adapter
- GENERIC MAP (
- g_in_latency => 1,
- g_out_latency => 0
- )
- PORT MAP (
- clk => clk_txmac,
- rst => rst_txmac,
-
- snk_in => dp_fifo_fill_eop_src_out,
- snk_out => dp_fifo_fill_eop_src_in,
-
- src_out => dp_latency_adapter_tx_b_src_out,
- src_in => dp_latency_adapter_tx_b_src_in
- );
+ src_out => dp_fifo_fill_eop_src_out_arr(mac),
+ src_in => dp_fifo_fill_eop_src_in_arr(mac)
+ );
- ----------------------------------------------------------------------------
- -- 40G MAC IP
- ----------------------------------------------------------------------------
- l4_tx_data <= dp_latency_adapter_tx_b_src_out.data(c_data_w-1 DOWNTO 0);
- l4_tx_valid <= dp_latency_adapter_tx_b_src_out.valid;
- l4_tx_empty <= dp_latency_adapter_tx_b_src_out.empty(4 DOWNTO 0);
- l4_tx_startofpacket <= dp_latency_adapter_tx_b_src_out.sop;
- l4_tx_endofpacket <= dp_latency_adapter_tx_b_src_out.eop;
+ ----------------------------------------------------------------------------
+ -- Latency adapter: adapt RL=1 (upstream) to RL=0 (MAC TX interface).
+ ----------------------------------------------------------------------------
+ u_dp_latency_adapter_tx_b : ENTITY dp_lib.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ PORT MAP (
+ clk => clk_txmac_arr(mac),
+ rst => rst_txmac_arr(mac),
- dp_latency_adapter_tx_b_src_in.ready <= l4_tx_ready;
- dp_latency_adapter_tx_b_src_in.xon <= tx_lanes_stable;
+ snk_in => dp_fifo_fill_eop_src_out_arr(mac),
+ snk_out => dp_fifo_fill_eop_src_in_arr(mac),
- u_arria10_40g_mac : arria10_40g_mac
- PORT MAP (
- reset_async(0) => config_reset,
- clk_txmac(0) => clk_txmac, -- MAC + PCS clock - at least 312.5Mhz
- clk_rxmac(0) => clk_rxmac, -- MAC + PCS clock - at least 312.5Mhz
- clk_ref(0) => clk_ref_r,
- rx_pcs_ready(0) => rx_pcs_ready,
-
- tx_serial_clk => serial_clk_arr,
- tx_pll_locked(0) => pll_locked,
-
- clk_status(0) => config_clk,
- reset_status(0) => config_reset,
- status_addr => (OTHERS=>'0'),
- status_read => (OTHERS=>'0'),
- status_write => (OTHERS=>'0'),
- status_writedata => (OTHERS=>'0'),
+ src_out => dp_latency_adapter_tx_b_src_out_arr(mac),
+ src_in => dp_latency_adapter_tx_b_src_in_arr(mac)
+ );
+
+ ----------------------------------------------------------------------------
+ -- 40G MAC IP
+ ----------------------------------------------------------------------------
+ l4_tx_sosi_arr(mac) <= dp_latency_adapter_tx_b_src_out_arr(mac);
+ dp_latency_adapter_tx_b_src_in_arr(mac) <= l4_tx_siso_arr(mac);
+
+ u_arria10_40g_mac : arria10_40g_mac
+ PORT MAP (
+ reset_async(0) => config_reset,
+ clk_txmac(0) => clk_txmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
+ clk_rxmac(0) => clk_rxmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
+ clk_ref(0) => clk_ref_r,
+ rx_pcs_ready(0) => rx_pcs_ready_arr(mac),
+
+ tx_serial_clk => serial_clk_2arr(mac),
+ tx_pll_locked(0) => pll_locked_arr(mac),
+
+ clk_status(0) => config_clk,
+ reset_status(0) => config_reset,
+ status_addr => (OTHERS=>'0'),
+ status_read => (OTHERS=>'0'),
+ status_write => (OTHERS=>'0'),
+ status_writedata => (OTHERS=>'0'),
-- status_readdata => status_readdata_eth,
-- status_read_timeout => status_read_timeout,
-- status_readdata_valid => status_readdata_valid_eth,
-
- reconfig_clk(0) => config_clk,
- reconfig_reset(0) => config_reset,
- reconfig_write => (OTHERS=>'0'),
- reconfig_read => (OTHERS=>'0'),
- reconfig_address => (OTHERS=>'0'),
- reconfig_writedata => (OTHERS=>'0'),
+
+ reconfig_clk(0) => config_clk,
+ reconfig_reset(0) => config_reset,
+ reconfig_write => (OTHERS=>'0'),
+ reconfig_read => (OTHERS=>'0'),
+ reconfig_address => (OTHERS=>'0'),
+ reconfig_writedata => (OTHERS=>'0'),
-- reconfig_readdata => reco_readdata[31:0],
-- reconfig_waitrequest => reco_waitrequest,
-
- l4_tx_data => l4_tx_data,
- l4_tx_empty => l4_tx_empty,
- l4_tx_startofpacket => l4_tx_startofpacket,
- l4_tx_endofpacket => l4_tx_endofpacket,
- l4_tx_ready => l4_tx_ready,
- l4_tx_valid => l4_tx_valid,
- l4_tx_error => '0',
-
- l4_rx_data => l4_rx_data,
- l4_rx_empty => l4_rx_empty,
- l4_rx_startofpacket => l4_rx_startofpacket,
- l4_rx_endofpacket => l4_rx_endofpacket,
--- l4_rx_error => ,
- l4_rx_valid => l4_rx_valid,
-
--- l4_rx_status (),
--- l4_rx_fcs_error (),
--- l4_rx_fcs_valid (),
--- rx_inc_octetsOK (),
--- rx_inc_octetsOK_valid (),
--- rx_inc_runt (),
--- rx_inc_64 (),
--- rx_inc_127 (),
--- rx_inc_255 (),
--- rx_inc_511 (),
--- rx_inc_1023 (),
--- rx_inc_1518 (),
--- rx_inc_max (),
--- rx_inc_over (),
--- rx_inc_mcast_data_err (),
--- rx_inc_mcast_data_ok (),
--- rx_inc_bcast_data_err (),
--- rx_inc_bcast_data_ok (),
--- rx_inc_ucast_data_err (),
--- rx_inc_ucast_data_ok (),
--- rx_inc_mcast_ctrl (),
--- rx_inc_bcast_ctrl (),
--- rx_inc_ucast_ctrl (),
--- rx_inc_pause (),
--- rx_inc_fcs_err (),
--- rx_inc_fragment (),
--- rx_inc_jabber (),
--- rx_inc_sizeok_fcserr (),
--- rx_inc_pause_ctrl_err (),
--- rx_inc_mcast_ctrl_err (),
--- rx_inc_bcast_ctrl_err (),
--- rx_inc_ucast_ctrl_err (),
--- status_waitrequest (),
- tx_lanes_stable(0) => tx_lanes_stable,
--- tx_inc_octetsOK (),
--- tx_inc_octetsOK_valid (),
--- tx_inc_64 (),
--- tx_inc_127 (),
--- tx_inc_255 (),
--- tx_inc_511 (),
--- tx_inc_1023 (),
--- tx_inc_1518 (),
--- tx_inc_max (),
--- tx_inc_over (),
--- tx_inc_mcast_data_err (),
--- tx_inc_mcast_data_ok (),
--- tx_inc_bcast_data_err (),
--- tx_inc_bcast_data_ok (),
--- tx_inc_ucast_data_err (),
--- tx_inc_ucast_data_ok (),
--- tx_inc_mcast_ctrl (),
--- tx_inc_bcast_ctrl (),
--- tx_inc_ucast_ctrl (),
--- tx_inc_pause (),
--- tx_inc_fcs_err (),
--- tx_inc_fragment (),
--- tx_inc_jabber (),
--- tx_inc_sizeok_fcserr (),
-
- tx_serial => tx_serial_r,
- rx_serial => rx_serial_r
- );
+
+ l4_tx_data => l4_tx_sosi_arr(mac).data(255 DOWNTO 0),
+ l4_tx_empty => l4_tx_sosi_arr(mac).empty(4 DOWNTO 0),
+ l4_tx_startofpacket => l4_tx_sosi_arr(mac).sop,
+ l4_tx_endofpacket => l4_tx_sosi_arr(mac).eop,
+ l4_tx_ready => l4_tx_siso_arr(mac).ready,
+ l4_tx_valid => l4_tx_sosi_arr(mac).valid,
+ l4_tx_error => '0',
+
+ l4_rx_data => l4_rx_sosi_arr(mac).data(255 DOWNTO 0),
+ l4_rx_empty => l4_rx_sosi_arr(mac).empty(4 DOWNTO 0),
+ l4_rx_startofpacket => l4_rx_sosi_arr(mac).sop,
+ l4_rx_endofpacket => l4_rx_sosi_arr(mac).eop,
+ -- l4_rx_error => ,
+ l4_rx_valid => l4_rx_sosi_arr(mac).valid,
+
+ -- l4_rx_status (),
+ -- l4_rx_fcs_error (),
+ -- l4_rx_fcs_valid (),
+ -- rx_inc_octetsOK (),
+ -- rx_inc_octetsOK_valid (),
+ -- rx_inc_runt (),
+ -- rx_inc_64 (),
+ -- rx_inc_127 (),
+ -- rx_inc_255 (),
+ -- rx_inc_511 (),
+ -- rx_inc_1023 (),
+ -- rx_inc_1518 (),
+ -- rx_inc_max (),
+ -- rx_inc_over (),
+ -- rx_inc_mcast_data_err (),
+ -- rx_inc_mcast_data_ok (),
+ -- rx_inc_bcast_data_err (),
+ -- rx_inc_bcast_data_ok (),
+ -- rx_inc_ucast_data_err (),
+ -- rx_inc_ucast_data_ok (),
+ -- rx_inc_mcast_ctrl (),
+ -- rx_inc_bcast_ctrl (),
+ -- rx_inc_ucast_ctrl (),
+ -- rx_inc_pause (),
+ -- rx_inc_fcs_err (),
+ -- rx_inc_fragment (),
+ -- rx_inc_jabber (),
+ -- rx_inc_sizeok_fcserr (),
+ -- rx_inc_pause_ctrl_err (),
+ -- rx_inc_mcast_ctrl_err (),
+ -- rx_inc_bcast_ctrl_err (),
+ -- rx_inc_ucast_ctrl_err (),
+ -- status_waitrequest (),
+ tx_lanes_stable(0) => l4_tx_siso_arr(mac).xon,
+ -- tx_inc_octetsOK (),
+ -- tx_inc_octetsOK_valid (),
+ -- tx_inc_64 (),
+ -- tx_inc_127 (),
+ -- tx_inc_255 (),
+ -- tx_inc_511 (),
+ -- tx_inc_1023 (),
+ -- tx_inc_1518 (),
+ -- tx_inc_max (),
+ -- tx_inc_over (),
+ -- tx_inc_mcast_data_err (),
+ -- tx_inc_mcast_data_ok (),
+ -- tx_inc_bcast_data_err (),
+ -- tx_inc_bcast_data_ok (),
+ -- tx_inc_ucast_data_err (),
+ -- tx_inc_ucast_data_ok (),
+ -- tx_inc_mcast_ctrl (),
+ -- tx_inc_bcast_ctrl (),
+ -- tx_inc_ucast_ctrl (),
+ -- tx_inc_pause (),
+ -- tx_inc_fcs_err (),
+ -- tx_inc_fragment (),
+ -- tx_inc_jabber (),
+ -- tx_inc_sizeok_fcserr (),
+
+ tx_serial => tx_serial_r(4*(mac+1)-1 DOWNTO 4*mac),
+ rx_serial => rx_serial_r(4*(mac+1)-1 DOWNTO 4*mac)
+ );
+
+
+ -- No latency adapter needed as the RX MAC does not have a ready input
+ ----------------------------------------------------------------------------
+ -- RX FIFO
+ ----------------------------------------------------------------------------
+ rst_rxmac_arr(mac) <= NOT rx_pcs_ready_arr(mac);
+ u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc
+ GENERIC MAP (
+ g_data_w => c_data_w,
+ g_empty_w => 8,
+ g_use_empty => TRUE,
+ g_use_bsn => FALSE,
+ g_bsn_w => 64,
+ g_use_channel => FALSE,
+ g_use_sync => FALSE,
+ g_fifo_size => c_rx_fifo_size
+ )
+ PORT MAP (
+ wr_clk => clk_rxmac_arr(mac),
+ wr_rst => rst_rxmac_arr(mac),
+ rd_clk => kernel_clk,
+ rd_rst => kernel_reset,
- -- No latency adapter needed as the RX MAC does not have a ready input
- ----------------------------------------------------------------------------
- -- RX FIFO
- ----------------------------------------------------------------------------
- rst_rxmac <= NOT rx_pcs_ready;
- rx_status <= rx_pcs_ready;
-
- dp_fifo_dc_snk_in.data(c_data_w-1 DOWNTO 0) <= l4_rx_data;
- dp_fifo_dc_snk_in.valid <= l4_rx_valid;
- dp_fifo_dc_snk_in.sop <= l4_rx_startofpacket;
- dp_fifo_dc_snk_in.eop <= l4_rx_endofpacket;
- dp_fifo_dc_snk_in.empty(4 DOWNTO 0) <= l4_rx_empty;
-
- u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc
- GENERIC MAP (
- g_data_w => c_data_w,
- g_empty_w => 8,
- g_use_empty => TRUE,
- g_use_bsn => FALSE,
- g_bsn_w => 64,
- g_use_channel => FALSE,
- g_use_sync => FALSE,
- g_fifo_size => c_rx_fifo_size
- )
- PORT MAP (
- wr_clk => clk_rxmac,
- wr_rst => rst_rxmac,
-
- rd_clk => kernel_clk,
- rd_rst => kernel_reset,
-
- snk_in => dp_fifo_dc_snk_in,
- snk_out => OPEN,
-
- src_out => dp_fifo_dc_src_out,
- src_in => dp_fifo_dc_src_in
- );
+ snk_in => l4_rx_sosi_arr(mac),
+ snk_out => OPEN,
+ src_out => dp_fifo_dc_src_out_arr(mac),
+ src_in => dp_fifo_dc_src_in_arr(mac)
+ );
- ----------------------------------------------------------------------------
- -- Latency adapter: adapt RL=1 (dp_fifo_dc) to RL=0 (OpenCL kernel).
- ----------------------------------------------------------------------------
- u_dp_latency_adapter_rx : ENTITY dp_lib.dp_latency_adapter
- GENERIC MAP (
- g_in_latency => 1,
- g_out_latency => 0
- )
- PORT MAP (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_fifo_dc_src_out,
- snk_out => dp_fifo_dc_src_in,
-
- src_out => dp_latency_adapter_rx_src_out,
- src_in => dp_latency_adapter_rx_src_in
- );
- ----------------------------------------------------------------------------
- -- Data mapping
- ----------------------------------------------------------------------------
- -- Reverse byte order
- gen_rx_bytes: FOR I IN 0 TO 31 GENERATE
- kernel_src_data(8*(32-I) -1 DOWNTO 8*(31-I)) <= dp_latency_adapter_rx_src_out.data(8*(I+1) -1 DOWNTO 8*I);
- END GENERATE;
+ ----------------------------------------------------------------------------
+ -- Latency adapter: adapt RL=1 (dp_fifo_dc) to RL=0 (OpenCL kernel).
+ ----------------------------------------------------------------------------
+ u_dp_latency_adapter_rx : ENTITY dp_lib.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ PORT MAP (
+ clk => kernel_clk,
+ rst => kernel_reset,
+
+ snk_in => dp_fifo_dc_src_out_arr(mac),
+ snk_out => dp_fifo_dc_src_in_arr(mac),
+
+ src_out => dp_latency_adapter_rx_src_out_arr(mac),
+ src_in => dp_latency_adapter_rx_src_in_arr(mac)
+ );
- -- Assign control signals to correct data fields.
- kernel_src_data(256) <= dp_latency_adapter_rx_src_out.sop;
- kernel_src_data(257) <= dp_latency_adapter_rx_src_out.eop;
- kernel_src_data(263 DOWNTO 259) <= dp_latency_adapter_rx_src_out.empty(4 DOWNTO 0);
+ ----------------------------------------------------------------------------
+ -- Data mapping
+ ----------------------------------------------------------------------------
+ -- Reverse byte order
+ gen_rx_bytes: FOR I IN 0 TO 31 GENERATE
+ src_out_arr(mac).data(8*(32-I) -1 DOWNTO 8*(31-I)) <= dp_latency_adapter_rx_src_out_arr(mac).data(8*(I+1) -1 DOWNTO 8*I);
+ END GENERATE;
+
+ -- Assign control signals to correct data fields.
+ src_out_arr(mac).data(256) <= dp_latency_adapter_rx_src_out_arr(mac).sop;
+ src_out_arr(mac).data(257) <= dp_latency_adapter_rx_src_out_arr(mac).eop;
+ src_out_arr(mac).data(263 DOWNTO 259) <= dp_latency_adapter_rx_src_out_arr(mac).empty(4 DOWNTO 0);
+ src_out_arr(mac).valid <= dp_latency_adapter_rx_src_out_arr(mac).valid;
+ dp_latency_adapter_rx_src_in_arr(mac).ready <= src_in_arr(mac).ready;
+ dp_latency_adapter_rx_src_in_arr(mac).xon <= '1';
+
+ -------------------------------------------------------------------------------
+ -- Reset signal generation
+ -------------------------------------------------------------------------------
+ u_common_areset_txmac : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1',
+ g_delay_len => 3
+ )
+ PORT MAP (
+ in_rst => kernel_reset,
+ clk => clk_txmac_arr(mac),
+ out_rst => rst_txmac_arr(mac)
+ );
- kernel_src_valid <= dp_latency_adapter_rx_src_out.valid;
- dp_latency_adapter_rx_src_in.ready <= kernel_src_ready;
- dp_latency_adapter_rx_src_in.xon <= '1';
-
- -------------------------------------------------------------------------------
- -- PLL for clock generation
- -------------------------------------------------------------------------------
- u_arria10_40g_atx_pll : arria10_40g_atx_pll
- port map (
- pll_cal_busy => OPEN,
- pll_locked => pll_locked,
- pll_powerdown => config_reset,
- pll_refclk0 => clk_ref_r,
- tx_serial_clk => serial_clk
- );
- gen_serial_clk_arr : FOR i IN 0 TO 3 GENERATE
- serial_clk_arr(i) <= serial_clk;
+ -------------------------------------------------------------------------------
+ -- PLL for clock generation, every mac needs its own, due to clock nework limitations
+ -------------------------------------------------------------------------------
+ u_arria10_40g_atx_pll : arria10_40g_atx_pll
+ port map (
+ pll_cal_busy => OPEN,
+ pll_locked => pll_locked_arr(mac),
+ pll_powerdown => config_reset,
+ pll_refclk0 => clk_ref_r,
+ tx_serial_clk => serial_clk_arr(mac)
+ );
+
+ gen_serial_clk_arr : FOR i IN 0 TO 3 GENERATE
+ serial_clk_2arr(mac)(i) <= serial_clk_arr(mac);
+ END GENERATE;
+
END GENERATE;
- -------------------------------------------------------------------------------
- -- Reset signal generation
- -------------------------------------------------------------------------------
-
- u_common_areset_txmac : ENTITY common_lib.common_areset
- GENERIC MAP (
- g_rst_level => '1',
- g_delay_len => 3
- )
- PORT MAP (
- in_rst => kernel_reset,
- clk => clk_txmac,
- out_rst => rst_txmac
- );
END str;
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl
deleted file mode 100644
index 255db44967490e52c662c30bd7a3ddd147f66720..0000000000000000000000000000000000000000
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl
+++ /dev/null
@@ -1,213 +0,0 @@
-# TCL File Generated by Component Editor 18.0
-# Fri Jan 10 16:11:08 CET 2020
-# DO NOT MODIFY
-
-
-#
-# ta2_unb2b_40GbE "ta2_unb2b_40GbE" v1.0
-# 2020.01.10.16:11:08
-#
-#
-
-#
-# request TCL package from ACDS 18.0
-#
-package require -exact qsys 18.0
-
-
-#
-# module ta2_unb2b_40GbE
-#
-set_module_property DESCRIPTION ""
-set_module_property NAME ta2_unb2b_40GbE
-set_module_property VERSION 1.0
-set_module_property INTERNAL false
-set_module_property OPAQUE_ADDRESS_MAP true
-set_module_property AUTHOR ""
-set_module_property DISPLAY_NAME ta2_unb2b_40GbE
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property EDITABLE true
-set_module_property REPORT_TO_TALKBACK false
-set_module_property ALLOW_GREYBOX_GENERATION false
-set_module_property REPORT_HIERARCHY false
-
-
-#
-# file sets
-#
-add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL ta2_unb2b_40GbE_ip_wrapper
-set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file ta2_unb2b_40GbE_ip_wrapper.vhd VHDL PATH ta2_unb2b_40GbE_ip_wrapper.vhd TOP_LEVEL_FILE
-
-
-#
-# parameters
-#
-
-
-#
-# display items
-#
-
-
-#
-# connection point kernel_snk
-#
-add_interface kernel_snk avalon_streaming end
-set_interface_property kernel_snk associatedClock kernel_clk
-set_interface_property kernel_snk associatedReset kernel_reset
-set_interface_property kernel_snk dataBitsPerSymbol 8
-set_interface_property kernel_snk errorDescriptor ""
-set_interface_property kernel_snk firstSymbolInHighOrderBits true
-set_interface_property kernel_snk maxChannel 0
-set_interface_property kernel_snk readyAllowance 0
-set_interface_property kernel_snk readyLatency 0
-set_interface_property kernel_snk ENABLED true
-set_interface_property kernel_snk EXPORT_OF ""
-set_interface_property kernel_snk PORT_NAME_MAP ""
-set_interface_property kernel_snk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_snk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_snk kernel_snk_data data Input 264
-add_interface_port kernel_snk kernel_snk_ready ready Output 1
-add_interface_port kernel_snk kernel_snk_valid valid Input 1
-
-
-#
-# connection point kernel_src
-#
-add_interface kernel_src avalon_streaming start
-set_interface_property kernel_src associatedClock kernel_clk
-set_interface_property kernel_src associatedReset kernel_reset
-set_interface_property kernel_src dataBitsPerSymbol 8
-set_interface_property kernel_src errorDescriptor ""
-set_interface_property kernel_src firstSymbolInHighOrderBits true
-set_interface_property kernel_src maxChannel 0
-set_interface_property kernel_src readyAllowance 0
-set_interface_property kernel_src readyLatency 0
-set_interface_property kernel_src ENABLED true
-set_interface_property kernel_src EXPORT_OF ""
-set_interface_property kernel_src PORT_NAME_MAP ""
-set_interface_property kernel_src CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_src SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_src kernel_src_data data Output 264
-add_interface_port kernel_src kernel_src_ready ready Input 1
-add_interface_port kernel_src kernel_src_valid valid Output 1
-
-
-#
-# connection point config_clk
-#
-add_interface config_clk clock end
-set_interface_property config_clk ENABLED true
-set_interface_property config_clk EXPORT_OF ""
-set_interface_property config_clk PORT_NAME_MAP ""
-set_interface_property config_clk CMSIS_SVD_VARIABLES ""
-set_interface_property config_clk SVD_ADDRESS_GROUP ""
-
-add_interface_port config_clk config_clk clk Input 1
-
-
-#
-# connection point kernel_clk
-#
-add_interface kernel_clk clock end
-set_interface_property kernel_clk ENABLED true
-set_interface_property kernel_clk EXPORT_OF ""
-set_interface_property kernel_clk PORT_NAME_MAP ""
-set_interface_property kernel_clk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_clk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_clk kernel_clk clk Input 1
-
-
-#
-# connection point refclk
-#
-add_interface refclk clock end
-set_interface_property refclk ENABLED true
-set_interface_property refclk EXPORT_OF ""
-set_interface_property refclk PORT_NAME_MAP ""
-set_interface_property refclk CMSIS_SVD_VARIABLES ""
-set_interface_property refclk SVD_ADDRESS_GROUP ""
-
-add_interface_port refclk clk_ref_r clk Input 1
-
-
-#
-# connection point rx_serial_data
-#
-add_interface rx_serial_data conduit end
-set_interface_property rx_serial_data associatedClock ""
-set_interface_property rx_serial_data associatedReset ""
-set_interface_property rx_serial_data ENABLED true
-set_interface_property rx_serial_data EXPORT_OF ""
-set_interface_property rx_serial_data PORT_NAME_MAP ""
-set_interface_property rx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property rx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_serial_data rx_serial_r conduit Input 4
-
-
-#
-# connection point tx_serial_data
-#
-add_interface tx_serial_data conduit end
-set_interface_property tx_serial_data associatedClock ""
-set_interface_property tx_serial_data associatedReset ""
-set_interface_property tx_serial_data ENABLED true
-set_interface_property tx_serial_data EXPORT_OF ""
-set_interface_property tx_serial_data PORT_NAME_MAP ""
-set_interface_property tx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property tx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port tx_serial_data tx_serial_r conduit Output 4
-
-
-#
-# connection point config_reset
-#
-add_interface config_reset reset end
-set_interface_property config_reset associatedClock config_clk
-set_interface_property config_reset synchronousEdges DEASSERT
-set_interface_property config_reset ENABLED true
-set_interface_property config_reset EXPORT_OF ""
-set_interface_property config_reset PORT_NAME_MAP ""
-set_interface_property config_reset CMSIS_SVD_VARIABLES ""
-set_interface_property config_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port config_reset config_reset reset Input 1
-
-
-#
-# connection point kernel_reset
-#
-add_interface kernel_reset reset end
-set_interface_property kernel_reset associatedClock kernel_clk
-set_interface_property kernel_reset synchronousEdges DEASSERT
-set_interface_property kernel_reset ENABLED true
-set_interface_property kernel_reset EXPORT_OF ""
-set_interface_property kernel_reset PORT_NAME_MAP ""
-set_interface_property kernel_reset CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_reset kernel_reset reset Input 1
-
-
-#
-# connection point rx_status
-#
-add_interface rx_status conduit end
-set_interface_property rx_status associatedClock ""
-set_interface_property rx_status associatedReset ""
-set_interface_property rx_status ENABLED true
-set_interface_property rx_status EXPORT_OF ""
-set_interface_property rx_status PORT_NAME_MAP ""
-set_interface_property rx_status CMSIS_SVD_VARIABLES ""
-set_interface_property rx_status SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_status rx_status rx_status Output 1
-
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl~ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl~
deleted file mode 100644
index 169117a331eac1ca345c42d509fd27d289c490c8..0000000000000000000000000000000000000000
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl~
+++ /dev/null
@@ -1,213 +0,0 @@
-# TCL File Generated by Component Editor 18.0
-# Fri Jan 10 15:53:26 CET 2020
-# DO NOT MODIFY
-
-
-#
-# ta2_unb2b_40GbE "ta2_unb2b_40GbE" v1.0
-# 2020.01.10.15:53:26
-#
-#
-
-#
-# request TCL package from ACDS 18.0
-#
-package require -exact qsys 18.0
-
-
-#
-# module ta2_unb2b_40GbE
-#
-set_module_property DESCRIPTION ""
-set_module_property NAME ta2_unb2b_40GbE
-set_module_property VERSION 1.0
-set_module_property INTERNAL false
-set_module_property OPAQUE_ADDRESS_MAP true
-set_module_property AUTHOR ""
-set_module_property DISPLAY_NAME ta2_unb2b_40GbE
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property EDITABLE true
-set_module_property REPORT_TO_TALKBACK false
-set_module_property ALLOW_GREYBOX_GENERATION false
-set_module_property REPORT_HIERARCHY false
-
-
-#
-# file sets
-#
-add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL ta2_unb2b_40GbE_ip_wrapper
-set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file ta2_unb2b_40GbE_ip_wrapper.vhd VHDL PATH ta2_unb2b_40GbE_ip_wrapper.vhd TOP_LEVEL_FILE
-
-
-#
-# parameters
-#
-
-
-#
-# display items
-#
-
-
-#
-# connection point kernel_snk
-#
-add_interface kernel_snk avalon_streaming end
-set_interface_property kernel_snk associatedClock kernel_clk
-set_interface_property kernel_snk associatedReset kernel_reset
-set_interface_property kernel_snk dataBitsPerSymbol 8
-set_interface_property kernel_snk errorDescriptor ""
-set_interface_property kernel_snk firstSymbolInHighOrderBits true
-set_interface_property kernel_snk maxChannel 0
-set_interface_property kernel_snk readyAllowance 0
-set_interface_property kernel_snk readyLatency 0
-set_interface_property kernel_snk ENABLED true
-set_interface_property kernel_snk EXPORT_OF ""
-set_interface_property kernel_snk PORT_NAME_MAP ""
-set_interface_property kernel_snk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_snk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_snk kernel_snk_data data Input 264
-add_interface_port kernel_snk kernel_snk_ready ready Output 1
-add_interface_port kernel_snk kernel_snk_valid valid Input 1
-
-
-#
-# connection point kernel_src
-#
-add_interface kernel_src avalon_streaming start
-set_interface_property kernel_src associatedClock kernel_clk
-set_interface_property kernel_src associatedReset kernel_reset
-set_interface_property kernel_src dataBitsPerSymbol 8
-set_interface_property kernel_src errorDescriptor ""
-set_interface_property kernel_src firstSymbolInHighOrderBits true
-set_interface_property kernel_src maxChannel 0
-set_interface_property kernel_src readyAllowance 0
-set_interface_property kernel_src readyLatency 0
-set_interface_property kernel_src ENABLED true
-set_interface_property kernel_src EXPORT_OF ""
-set_interface_property kernel_src PORT_NAME_MAP ""
-set_interface_property kernel_src CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_src SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_src kernel_src_data data Output 264
-add_interface_port kernel_src kernel_src_ready ready Input 1
-add_interface_port kernel_src kernel_src_valid valid Output 1
-
-
-#
-# connection point config_clk
-#
-add_interface config_clk clock end
-set_interface_property config_clk ENABLED true
-set_interface_property config_clk EXPORT_OF ""
-set_interface_property config_clk PORT_NAME_MAP ""
-set_interface_property config_clk CMSIS_SVD_VARIABLES ""
-set_interface_property config_clk SVD_ADDRESS_GROUP ""
-
-add_interface_port config_clk config_clk clk Input 1
-
-
-#
-# connection point kernel_clk
-#
-add_interface kernel_clk clock end
-set_interface_property kernel_clk ENABLED true
-set_interface_property kernel_clk EXPORT_OF ""
-set_interface_property kernel_clk PORT_NAME_MAP ""
-set_interface_property kernel_clk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_clk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_clk kernel_clk clk Input 1
-
-
-#
-# connection point refclk
-#
-add_interface refclk clock end
-set_interface_property refclk ENABLED true
-set_interface_property refclk EXPORT_OF ""
-set_interface_property refclk PORT_NAME_MAP ""
-set_interface_property refclk CMSIS_SVD_VARIABLES ""
-set_interface_property refclk SVD_ADDRESS_GROUP ""
-
-add_interface_port refclk clk_ref_r clk Input 1
-
-
-#
-# connection point rx_serial_data
-#
-add_interface rx_serial_data conduit end
-set_interface_property rx_serial_data associatedClock ""
-set_interface_property rx_serial_data associatedReset ""
-set_interface_property rx_serial_data ENABLED true
-set_interface_property rx_serial_data EXPORT_OF ""
-set_interface_property rx_serial_data PORT_NAME_MAP ""
-set_interface_property rx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property rx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_serial_data rx_serial_r conduit Input 4
-
-
-#
-# connection point tx_serial_data
-#
-add_interface tx_serial_data conduit end
-set_interface_property tx_serial_data associatedClock ""
-set_interface_property tx_serial_data associatedReset ""
-set_interface_property tx_serial_data ENABLED true
-set_interface_property tx_serial_data EXPORT_OF ""
-set_interface_property tx_serial_data PORT_NAME_MAP ""
-set_interface_property tx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property tx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port tx_serial_data tx_serial_r conduit Output 4
-
-
-#
-# connection point config_reset
-#
-add_interface config_reset reset end
-set_interface_property config_reset associatedClock config_clk
-set_interface_property config_reset synchronousEdges DEASSERT
-set_interface_property config_reset ENABLED true
-set_interface_property config_reset EXPORT_OF ""
-set_interface_property config_reset PORT_NAME_MAP ""
-set_interface_property config_reset CMSIS_SVD_VARIABLES ""
-set_interface_property config_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port config_reset config_reset reset Input 1
-
-
-#
-# connection point kernel_reset
-#
-add_interface kernel_reset reset end
-set_interface_property kernel_reset associatedClock kernel_clk
-set_interface_property kernel_reset synchronousEdges DEASSERT
-set_interface_property kernel_reset ENABLED true
-set_interface_property kernel_reset EXPORT_OF ""
-set_interface_property kernel_reset PORT_NAME_MAP ""
-set_interface_property kernel_reset CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_reset kernel_reset reset Input 1
-
-
-#
-# connection point rx_status
-#
-add_interface rx_status conduit end
-set_interface_property rx_status associatedClock ""
-set_interface_property rx_status associatedReset ""
-set_interface_property rx_status ENABLED true
-set_interface_property rx_status EXPORT_OF ""
-set_interface_property rx_status PORT_NAME_MAP ""
-set_interface_property rx_status CMSIS_SVD_VARIABLES ""
-set_interface_property rx_status SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_status rx_status rx_status Output 1
-
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_ip_wrapper.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_ip_wrapper.vhd
deleted file mode 100644
index c6c086f03bf3f2c3bf9b62969cb2f2059608b16b..0000000000000000000000000000000000000000
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_ip_wrapper.vhd
+++ /dev/null
@@ -1,114 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2019
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Author:
--- . Reinier van der Walle
--- Purpose:
--- . Instantiates ta2_unb2b_40GbE component
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY ta2_unb2b_40GbE_ip_wrapper IS
- PORT (
- config_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
- config_reset : IN STD_LOGIC;
-
- clk_ref_r : IN STD_LOGIC; -- 644.53125MHz 40G MAC reference clock
-
- tx_serial_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- Serial TX lanes towards QSFP cage
- rx_serial_r : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Serial RX lanes from QSFP cage
-
- kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
- kernel_reset : IN STD_LOGIC;
-
- kernel_src_data : OUT STD_LOGIC_VECTOR(263 DOWNTO 0); -- RX Data to kernel
- kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
- kernel_src_ready : IN STD_LOGIC; -- Flow control from kernel
-
- kernel_snk_data : IN STD_LOGIC_VECTOR(263 DOWNTO 0); -- TX Data from kernel
- kernel_snk_valid : IN STD_LOGIC; -- TX data valid signal from kernel
- kernel_snk_ready : OUT STD_LOGIC; -- Flow control towards kernel
-
- rx_status : OUT STD_LOGIC -- RX status
- );
-END ta2_unb2b_40GbE_ip_wrapper;
-
-
-ARCHITECTURE str OF ta2_unb2b_40GbE_ip_wrapper IS
- ----------------------------------------------------------------------------
- -- ta2_unb2b_40GbE Component
- ----------------------------------------------------------------------------
- COMPONENT ta2_unb2b_40GbE IS
- PORT (
- config_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
- config_reset : IN STD_LOGIC;
-
- clk_ref_r : IN STD_LOGIC; -- 644.53125MHz 40G MAC reference clock
-
- tx_serial_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- Serial TX lanes towards QSFP cage
- rx_serial_r : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Serial RX lanes from QSFP cage
-
- kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
- kernel_reset : IN STD_LOGIC;
-
- kernel_src_data : OUT STD_LOGIC_VECTOR(263 DOWNTO 0); -- RX Data to kernel
- kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
- kernel_src_ready : IN STD_LOGIC; -- Flow control from kernel
-
- kernel_snk_data : IN STD_LOGIC_VECTOR(263 DOWNTO 0); -- TX Data from kernel
- kernel_snk_valid : IN STD_LOGIC; -- TX data valid signal from kernel
- kernel_snk_ready : OUT STD_LOGIC; -- Flow control towards kernel
-
- rx_status : OUT STD_LOGIC -- RX status
- );
- END COMPONENT ta2_unb2b_40GbE;
-
-BEGIN
-
- u_ta2_unb2b_40GbE : ta2_unb2b_40GbE
- PORT MAP (
- config_clk => config_clk,
- config_reset => config_reset,
-
- clk_ref_r => clk_ref_r,
-
- tx_serial_r => tx_serial_r,
- rx_serial_r => rx_serial_r,
-
- kernel_clk => kernel_clk,
- kernel_reset => kernel_reset,
-
- kernel_src_data => kernel_src_data,
- kernel_src_valid => kernel_src_valid,
- kernel_src_ready => kernel_src_ready,
-
- kernel_snk_data => kernel_snk_data,
- kernel_snk_valid => kernel_snk_valid,
- kernel_snk_ready => kernel_snk_ready,
-
- rx_status => rx_status
-
- );
-
-
-
-END str;
-
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
index c2a6e2194b51b16200d0d0345f8a284cca003f31..506ffc71d94f343ad02865d95cf65149dc0b9eb6 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
@@ -55,12 +55,8 @@ ENTITY ta2_unb2b_jesd204b IS
config_reset : IN STD_LOGIC;
-- MM Control
- jesd204b_mosi_address : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- jesd204b_mosi_wrdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- jesd204b_mosi_wr : IN STD_LOGIC;
- jesd204b_mosi_rd : IN STD_LOGIC;
- jesd204b_miso_rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- jesd204b_miso_waitrequest : OUT STD_LOGIC;
+ jesd204b_mosi : IN t_mem_mosi;
+ jesd204b_miso : OUT t_mem_miso;
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
@@ -101,20 +97,10 @@ ARCHITECTURE str OF ta2_unb2b_jesd204b IS
SIGNAL jesd204b_frame_clk : STD_LOGIC;
SIGNAL jesd204b_rx_src_out_flat_w_sync : t_dp_sosi;
- SIGNAL jesd204b_mosi : t_mem_mosi;
- SIGNAL jesd204b_miso : t_mem_miso;
-
SIGNAL i_jesd204b_sync_n_arr : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
SIGNAL jesd204b_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
- jesd204b_mosi.address(7 DOWNTO 0) <= jesd204b_mosi_address;
- jesd204b_mosi.wrdata(31 DOWNTO 0) <= jesd204b_mosi_wrdata;
- jesd204b_mosi.wr <= jesd204b_mosi_wr;
- jesd204b_mosi.rd <= jesd204b_mosi_rd;
- jesd204b_miso_rddata <= jesd204b_miso.rddata(31 DOWNTO 0);
- jesd204b_miso_waitrequest <= jesd204b_miso.waitrequest;
-
jesd204b_sync_n_arr <= i_jesd204b_sync_n_arr(c_nof_connected_streams_jesd204b -1 DOWNTO 0);
jesd204b_serial_rx_arr(c_nof_connected_streams_jesd204b -1 DOWNTO 0) <= serial_rx_arr;
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/opencl_bsp_ip.qsf b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/opencl_bsp_ip.qsf
index f8d1dd23856996aa7799cf161a78991ff2ebb659..f0b654c9aa8384792f6d19eb249c928cb45079a4 100755
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/opencl_bsp_ip.qsf
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/opencl_bsp_ip.qsf
@@ -24,6 +24,7 @@ source device.tcl
#============================================================
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VHDL_FILE top_components_pkg.vhd
set_global_assignment -name VHDL_FILE top.vhd
set_global_assignment -name VERILOG_FILE ip/freeze_wrapper.v
set_global_assignment -name VERILOG_FILE ip/pr_region.v
@@ -37,6 +38,12 @@ set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 4
set_global_assignment -name QSYS_FILE board.qsys
+
+set_global_assignment -name VHDL_FILE ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
+set_global_assignment -name VHDL_FILE ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
+set_global_assignment -name VHDL_FILE ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd
+set_global_assignment -name VHDL_FILE ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
+
set_global_assignment -name IP_FILE ip/board/board_reg_unb_pmbus.ip
set_global_assignment -name IP_FILE ip/board/board_kernel_clk_gen.ip
set_global_assignment -name IP_FILE ip/board/board_reg_epcs.ip
@@ -62,4 +69,4 @@ set_global_assignment -name IP_FILE ip/board/board_reg_remu.ip
set_global_assignment -name IP_FILE ip/board/board_jtag_uart_0.ip
set_global_assignment -name IP_FILE ip/board/board_kernel_clk.ip
set_global_assignment -name IP_FILE ip/board/board_onchip_memory.ip
-
+set_global_assignment -name IP_FILE ip/board/board_reg_ta2_unb2b_jesd204b.ip
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top.vhd
index 187413cc2d03e4331d1800312741b9f029b8e17c..42ce5312d6c10011c424f7e1faef891ed146a9e0 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top.vhd
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
+USE work.top_components_pkg.ALL;
ENTITY top IS
GENERIC (
@@ -74,10 +75,16 @@ ENTITY top IS
SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
-- front transceivers
- QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+
+ -- ring transceivers
+ RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0) := (OTHERS => '0');
+ RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0);
+ RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0);
-- back transceivers
BCK_RX : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
@@ -105,7 +112,13 @@ ARCHITECTURE str OF top IS
-- 10GbE
CONSTANT c_nof_qsfp_bus : NATURAL := 2;
- CONSTANT c_nof_streams_qsfp : NATURAL := c_quad*c_nof_qsfp_bus;
+ CONSTANT c_nof_ring_bus : NATURAL := 2;
+ CONSTANT c_ring_bus_w : NATURAL := c_unb2b_board_tr_ring.bus_w;
+ CONSTANT c_nof_streams_qsfp : NATURAL := c_unb2b_board_tr_qsfp.bus_w*c_nof_qsfp_bus;
+ CONSTANT c_nof_streams_ring : NATURAL := c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus;
+
+ -- 40GbE
+ CONSTANT c_nof_40GbE_IP : NATURAL := 3;
-- System
SIGNAL cs_sim : STD_LOGIC;
@@ -185,27 +198,37 @@ ARCHITECTURE str OF top IS
SIGNAL reg_remu_mosi : t_mem_mosi;
SIGNAL reg_remu_miso : t_mem_miso;
+ -- JESD204b
+ SIGNAL reg_ta2_unb2b_jesd204b_mosi : t_mem_mosi;
+ SIGNAL reg_ta2_unb2b_jesd204b_miso : t_mem_miso;
+
-- 10GbE
SIGNAL i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
SIGNAL i_QSFP_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
-
+
+ SIGNAL i_RING_TX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ SIGNAL i_RING_RX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+
SIGNAL unb2b_board_front_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL unb2b_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
+
+ SIGNAL unb2b_board_ring_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL unb2b_board_ring_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_ring-1 DOWNTO 0);
-- QSFP leds
- SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_nof_qsfp_bus-1 DOWNTO 0);
- SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_nof_qsfp_bus-1 DOWNTO 0);
- SIGNAL unb2b_board_qsfp_leds_tx_src_in_arr : t_dp_siso_arr(c_nof_qsfp_bus*c_quad-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_nof_qsfp_bus+c_nof_ring_bus-1 DOWNTO 0);
+ SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_nof_qsfp_bus+c_nof_ring_bus-1 DOWNTO 0);
+ --SIGNAL unb2b_board_qsfp_leds_tx_src_in_arr : t_dp_siso_arr(c_nof_qsfp_bus*c_quad-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL unb2b_board_qsfp_leds_tx_src_in_arr : t_dp_siso_arr((c_nof_qsfp_bus+c_nof_qsfp_bus)*c_quad-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL i_reset_n : STD_LOGIC;
-
-
+ SIGNAL i_kernel_rst : STD_LOGIC;
-- OpenCL kernel
-
SIGNAL board_kernel_clk_clk : std_logic;
SIGNAL board_kernel_clk2x_clk : std_logic;
SIGNAL board_kernel_reset_reset_n : std_logic;
+ SIGNAL board_kernel_reset_reset_n_in : std_logic;
SIGNAL board_kernel_cra_waitrequest : std_logic;
SIGNAL board_kernel_cra_readdata : std_logic_vector(63 downto 0);
@@ -228,13 +251,12 @@ ARCHITECTURE str OF top IS
SIGNAL board_kernel_register_mem_writedata : std_logic_vector(255 downto 0); -- := (others => 'X'); -- writedata
SIGNAL board_kernel_register_mem_byteenable : std_logic_vector(31 downto 0); -- := (others => 'X'); -- byteenable
- SIGNAL board_kernel_stream_snk_40GbE_data : std_logic_vector(263 downto 0) := (others => 'X'); -- data
- SIGNAL board_kernel_stream_snk_40GbE_ready : std_logic; -- ready
- SIGNAL board_kernel_stream_snk_40GbE_valid : std_logic := 'X'; -- valid
- SIGNAL board_kernel_stream_src_40GbE_data : std_logic_vector(263 downto 0); -- data
- SIGNAL board_kernel_stream_src_40GbE_ready : std_logic := 'X'; -- ready
- SIGNAL board_kernel_stream_src_40GbE_valid : std_logic; -- valid
- SIGNAL ta2_unb2b_40gbe_rx_status_rx_status : std_logic; -- rx_status
+ SIGNAL ta2_unb2b_40GbE_src_out_arr : t_dp_sosi_arr(c_nof_40GbE_IP-1 DOWNTO 0);
+ SIGNAL ta2_unb2b_40GbE_src_in_arr : t_dp_siso_arr(c_nof_40GbE_IP-1 DOWNTO 0);
+ SIGNAL ta2_unb2b_40GbE_snk_out_arr : t_dp_siso_arr(c_nof_40GbE_IP-1 DOWNTO 0);
+ SIGNAL ta2_unb2b_40GbE_snk_in_arr : t_dp_sosi_arr(c_nof_40GbE_IP-1 DOWNTO 0);
+ SIGNAL ta2_unb2b_40GbE_tx_serial_r : STD_LOGIC_VECTOR(4*c_nof_40GbE_IP -1 DOWNTO 0);
+ SIGNAL ta2_unb2b_40GbE_rx_serial_r : STD_LOGIC_VECTOR(4*c_nof_40GbE_IP -1 DOWNTO 0);
SIGNAL board_kernel_stream_src_10GbE_data : std_logic_vector(71 downto 0);
SIGNAL board_kernel_stream_src_10GbE_valid : std_logic;
@@ -244,7 +266,6 @@ ARCHITECTURE str OF top IS
SIGNAL board_kernel_stream_snk_10GbE_ready : std_logic;
SIGNAL ta2_unb2b_10gbe_rx_status_rx_status : std_logic; -- rx_status
-
SIGNAL board_kernel_stream_src_1GbE_data : std_logic_vector(39 downto 0);
SIGNAL board_kernel_stream_src_1GbE_valid : std_logic;
SIGNAL board_kernel_stream_src_1GbE_ready : std_logic;
@@ -256,263 +277,287 @@ ARCHITECTURE str OF top IS
SIGNAL board_kernel_stream_src_ADC_valid : std_logic;
SIGNAL board_kernel_stream_src_ADC_ready : std_logic;
- component board is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- kernel_clk_clk : out std_logic; -- clk
- kernel_clk2x_clk : out std_logic; -- clk
- kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
- kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
- kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
- kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
- kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
- kernel_cra_address : out std_logic_vector(29 downto 0); -- address
- kernel_cra_write : out std_logic; -- write
- kernel_cra_read : out std_logic; -- read
- kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
- kernel_cra_debugaccess : out std_logic; -- debugaccess
- kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
- kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
- kernel_reset_reset_n : out std_logic; -- reset_n
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- kernel_register_mem_address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address
- kernel_register_mem_clken : in std_logic := 'X'; -- clken
- kernel_register_mem_chipselect : in std_logic := 'X'; -- chipselect
- kernel_register_mem_write : in std_logic := 'X'; -- write
- kernel_register_mem_readdata : out std_logic_vector(255 downto 0); -- readdata
- kernel_register_mem_writedata : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
- kernel_register_mem_byteenable : in std_logic_vector(31 downto 0) := (others => 'X'); -- byteenable
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- ta2_unb2b_10gbe_kernel_snk_data : in std_logic_vector(71 downto 0) := (others => 'X'); -- data
- ta2_unb2b_10gbe_kernel_snk_ready : out std_logic; -- ready
- ta2_unb2b_10gbe_kernel_snk_valid : in std_logic := 'X'; -- valid
- ta2_unb2b_10gbe_kernel_src_data : out std_logic_vector(71 downto 0); -- data
- ta2_unb2b_10gbe_kernel_src_ready : in std_logic := 'X'; -- ready
- ta2_unb2b_10gbe_kernel_src_valid : out std_logic; -- valid
- ta2_unb2b_10gbe_refclk_clk : in std_logic := 'X'; -- clk
- ta2_unb2b_10gbe_rx_serial_data_conduit : in std_logic := 'X'; -- conduit
- ta2_unb2b_10gbe_rx_status_rx_status : out std_logic; -- rx_status
- ta2_unb2b_10gbe_tx_serial_data_conduit : out std_logic; -- conduit
- ta2_unb2b_40gbe_kernel_snk_data : in std_logic_vector(263 downto 0) := (others => 'X'); -- data
- ta2_unb2b_40gbe_kernel_snk_ready : out std_logic; -- ready
- ta2_unb2b_40gbe_kernel_snk_valid : in std_logic := 'X'; -- valid
- ta2_unb2b_40gbe_kernel_src_data : out std_logic_vector(263 downto 0); -- data
- ta2_unb2b_40gbe_kernel_src_ready : in std_logic := 'X'; -- ready
- ta2_unb2b_40gbe_kernel_src_valid : out std_logic; -- valid
- ta2_unb2b_40gbe_refclk_clk : in std_logic := 'X'; -- clk
- ta2_unb2b_40gbe_rx_serial_data_conduit : in std_logic_vector(3 downto 0) := (others => 'X'); -- conduit
- ta2_unb2b_40gbe_rx_status_rx_status : out std_logic; -- rx_status
- ta2_unb2b_40gbe_tx_serial_data_conduit : out std_logic_vector(3 downto 0); -- conduit
-
- ta2_unb2b_1gbe_mc_kernel_snk_data : in std_logic_vector(39 downto 0) := (others => 'X'); -- data
- ta2_unb2b_1gbe_mc_kernel_snk_ready : out std_logic; -- ready
- ta2_unb2b_1gbe_mc_kernel_snk_valid : in std_logic := 'X'; -- valid
- ta2_unb2b_1gbe_mc_kernel_src_data : out std_logic_vector(39 downto 0); -- data
- ta2_unb2b_1gbe_mc_kernel_src_ready : in std_logic := 'X'; -- ready
- ta2_unb2b_1gbe_mc_kernel_src_valid : out std_logic; -- valid
- ta2_unb2b_1gbe_mc_st_clk_clk : in std_logic := 'X'; -- clk
- ta2_unb2b_1gbe_mc_st_rst_reset : in std_logic := 'X'; -- reset
- ta2_unb2b_1gbe_mc_udp_rx_snk_in_ready : out std_logic; -- ready
- ta2_unb2b_1gbe_mc_udp_rx_snk_in_data : in std_logic_vector(39 downto 0) := (others => 'X'); -- data
- ta2_unb2b_1gbe_mc_udp_rx_snk_in_empty : in std_logic_vector(1 downto 0) := (others => 'X'); -- empty
- ta2_unb2b_1gbe_mc_udp_rx_snk_in_endofpacket : in std_logic := 'X'; -- endofpacket
- ta2_unb2b_1gbe_mc_udp_rx_snk_in_startofpacket : in std_logic := 'X'; -- startofpacket
- ta2_unb2b_1gbe_mc_udp_rx_snk_in_valid : in std_logic := 'X'; -- valid
- ta2_unb2b_1gbe_mc_udp_rx_snk_in_xon_xon : out std_logic; -- xon
- ta2_unb2b_1gbe_mc_udp_tx_src_out_ready : in std_logic := 'X'; -- ready
- ta2_unb2b_1gbe_mc_udp_tx_src_out_data : out std_logic_vector(39 downto 0); -- data
- ta2_unb2b_1gbe_mc_udp_tx_src_out_empty : out std_logic_vector(1 downto 0); -- empty
- ta2_unb2b_1gbe_mc_udp_tx_src_out_endofpacket : out std_logic; -- endofpacket
- ta2_unb2b_1gbe_mc_udp_tx_src_out_startofpacket : out std_logic; -- startofpacket
- ta2_unb2b_1gbe_mc_udp_tx_src_out_valid : out std_logic; -- valid
- ta2_unb2b_1gbe_mc_udp_tx_src_out_xon_xon : in std_logic := 'X'; -- xon
-
- ta2_unb2b_jesd204b_kernel_src_data : out std_logic_vector(15 downto 0); -- data
- ta2_unb2b_jesd204b_kernel_src_ready : in std_logic := 'X'; -- ready
- ta2_unb2b_jesd204b_kernel_src_valid : out std_logic; -- valid
- ta2_unb2b_jesd204b_jesd204b_refclk_clk : in std_logic := 'X'; -- clk
- ta2_unb2b_jesd204b_jesd204b_sysref_conduit : in std_logic := 'X'; -- conduit
- ta2_unb2b_jesd204b_jesd204b_sync_n_conduit : out std_logic_vector(0 downto 0); -- conduit
- ta2_unb2b_jesd204b_serial_rx_arr_conduit : in std_logic_vector(0 downto 0) := (others => 'X') -- conduit
-
- );
- end component board;
-
- component freeze_wrapper is
- port (
- board_kernel_clk_clk : in std_logic; --input
- board_kernel_clk2x_clk : in std_logic; --input
- board_kernel_reset_reset_n : in std_logic; --input
- board_kernel_irq_irq : out std_logic_vector(0 downto 0); --output [0:0]
- board_kernel_cra_waitrequest : out std_logic; --output
- board_kernel_cra_readdata : out std_logic_vector(63 downto 0); --output [63:0]
- board_kernel_cra_readdatavalid : out std_logic; --output
- board_kernel_cra_burstcount : in std_logic_vector(0 downto 0); --input [0:0]
- board_kernel_cra_writedata : in std_logic_vector(63 downto 0); --input [63:0]
- board_kernel_cra_address : in std_logic_vector(29 downto 0); --input [29:0]
- board_kernel_cra_write : in std_logic; --input
- board_kernel_cra_read : in std_logic; --input
- board_kernel_cra_byteenable : in std_logic_vector(7 downto 0); --input [7:0]
- board_kernel_cra_debugaccess : in std_logic; --input
-
- board_kernel_register_mem_address : out std_logic_vector(6 downto 0); -- := (others => 'X'); -- address
- board_kernel_register_mem_clken : out std_logic; -- := 'X'; -- clken
- board_kernel_register_mem_chipselect : out std_logic; -- := 'X'; -- chipselect
- board_kernel_register_mem_write : out std_logic; -- := 'X'; -- write
- board_kernel_register_mem_readdata : in std_logic_vector(255 downto 0); -- readdata
- board_kernel_register_mem_writedata : out std_logic_vector(255 downto 0); -- := (others => 'X'); -- writedata
- board_kernel_register_mem_byteenable : out std_logic_vector(31 downto 0); -- := (others => 'X'); -- byteenable
-
- board_kernel_stream_src_40GbE_data : in std_logic_vector(263 downto 0);
- board_kernel_stream_src_40GbE_valid : in std_logic;
- board_kernel_stream_src_40GbE_ready : out std_logic;
- board_kernel_stream_snk_40GbE_data : out std_logic_vector(263 downto 0);
- board_kernel_stream_snk_40GbE_valid : out std_logic;
- board_kernel_stream_snk_40GbE_ready : in std_logic;
-
- board_kernel_stream_src_10GbE_data : in std_logic_vector(71 downto 0);
- board_kernel_stream_src_10GbE_valid : in std_logic;
- board_kernel_stream_src_10GbE_ready : out std_logic;
- board_kernel_stream_snk_10GbE_data : out std_logic_vector(71 downto 0);
- board_kernel_stream_snk_10GbE_valid : out std_logic;
- board_kernel_stream_snk_10GbE_ready : in std_logic;
-
- board_kernel_stream_src_1GbE_data : in std_logic_vector(39 downto 0);
- board_kernel_stream_src_1GbE_valid : in std_logic;
- board_kernel_stream_src_1GbE_ready : out std_logic;
- board_kernel_stream_snk_1GbE_data : out std_logic_vector(39 downto 0);
- board_kernel_stream_snk_1GbE_valid : out std_logic;
- board_kernel_stream_snk_1GbE_ready : in std_logic;
-
- board_kernel_stream_src_ADC_data : in std_logic_vector(15 downto 0);
- board_kernel_stream_src_ADC_valid : in std_logic;
- board_kernel_stream_src_ADC_ready : out std_logic
-
- );
- end component freeze_wrapper;
+BEGIN
+ ------------
+ -- Front IO
+ ------------
+ -- put the QSFP_TX/RX ports into arrays
+ i_QSFP_RX(0) <= QSFP_0_RX;
+ i_QSFP_RX(1) <= QSFP_1_RX;
+ QSFP_0_TX <= i_QSFP_TX(0);
+ QSFP_1_TX <= i_QSFP_TX(1);
-BEGIN
+ u_unb2b_board_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io
+ GENERIC MAP (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ PORT MAP (
+ serial_tx_arr => unb2b_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2b_board_front_io_serial_rx_arr,
+
+ --green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ --red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX --,
+
+ --QSFP_LED => QSFP_LED
+ );
+
+ ------------------------
+ -- qsfp LEDs controller
+ ------------------------
+ unb2b_board_qsfp_leds_tx_src_in_arr(0).xon <= ta2_unb2b_10gbe_rx_status_rx_status;
+ unb2b_board_qsfp_leds_tx_src_in_arr(4).xon <= ta2_unb2b_40GbE_snk_out_arr(0).xon;
+ -- ring LED indicator
+ unb2b_board_qsfp_leds_tx_src_in_arr(8).xon <= ta2_unb2b_40GbE_snk_out_arr(1).xon;
+ unb2b_board_qsfp_leds_tx_src_in_arr(12).xon <= ta2_unb2b_40GbE_snk_out_arr(2).xon;
+
+ u_unb2b_board_qsfp_leds : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus+c_nof_ring_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ PORT MAP (
+ rst => mm_rst,
+ clk => mm_clk,
+
+ tx_siso_arr => unb2b_board_qsfp_leds_tx_src_in_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus+c_nof_ring_bus-1 DOWNTO 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus+c_nof_ring_bus-1 DOWNTO 0)
+ );
+
+ gen_leds : FOR i IN 0 TO c_nof_qsfp_bus+c_nof_ring_bus-1 GENERATE
+ QSFP_LED(i*2) <= qsfp_green_led_arr(i);
+ QSFP_LED(i*2+1) <= qsfp_red_led_arr(i);
+ END GENERATE;
+
+
+
+ ------------
+ -- RING IO
+ ------------
+ i_RING_RX(0) <= RING_0_RX;
+ i_RING_RX(1) <= RING_1_RX;
+ RING_0_TX <= i_RING_TX(0);
+ RING_1_TX <= i_RING_TX(1);
+
+ u_ring_io : ENTITY unb2b_board_lib.unb2b_board_ring_io
+ GENERIC MAP (
+ g_nof_ring_bus => c_nof_ring_bus
+ )
+ PORT MAP (
+ serial_tx_arr => unb2b_board_ring_io_serial_tx_arr,
+ serial_rx_arr => unb2b_board_ring_io_serial_rx_arr,
+ RING_RX => i_RING_RX,
+ RING_TX => i_RING_TX
+ );
+
+ ---------
+ -- 40GbE
+ ---------
+ -- Front QSFP 1 40GbE Interface, IP index = 0
+ unb2b_board_front_io_serial_tx_arr(7 DOWNTO 4) <= ta2_unb2b_40GbE_tx_serial_r(3 DOWNTO 0);
+ ta2_unb2b_40GbE_rx_serial_r(3 DOWNTO 0) <= unb2b_board_front_io_serial_rx_arr(7 DOWNTO 4);
+
+ -- Ring 0 (to the left), IP index = 1
+ unb2b_board_ring_io_serial_tx_arr(3 DOWNTO 0) <= ta2_unb2b_40GbE_tx_serial_r(7 DOWNTO 4);
+ ta2_unb2b_40GbE_rx_serial_r(7 DOWNTO 4) <= unb2b_board_ring_io_serial_rx_arr(3 DOWNTO 0);
+
+ -- Ring 1 (to the right), IP index = 2
+ unb2b_board_ring_io_serial_tx_arr(3+c_ring_bus_w DOWNTO c_ring_bus_w) <= ta2_unb2b_40GbE_tx_serial_r(11 DOWNTO 8);
+ ta2_unb2b_40GbE_rx_serial_r(11 DOWNTO 8) <= unb2b_board_ring_io_serial_rx_arr(3+c_ring_bus_w DOWNTO c_ring_bus_w);
+
+ u_ta2_unb2b_40GbE : ENTITY work.ta2_unb2b_40GbE
+ GENERIC MAP (
+ g_nof_mac => c_nof_40GbE_IP
+ )
+ PORT MAP (
+ config_clk => mm_clk,
+ config_reset => mm_rst,
+
+ clk_ref_r => SA_CLK,
+
+ tx_serial_r => ta2_unb2b_40GbE_tx_serial_r,
+ rx_serial_r => ta2_unb2b_40GbE_rx_serial_r,
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ src_out_arr => ta2_unb2b_40GbE_src_out_arr,
+ src_in_arr => ta2_unb2b_40GbE_src_in_arr,
+ snk_out_arr => ta2_unb2b_40GbE_snk_out_arr,
+ snk_in_arr => ta2_unb2b_40GbE_snk_in_arr
+ );
+
+ ----------
+ -- 10GbE
+ ----------
+ u_ta2_unb2b_10GbE : ENTITY work.ta2_unb2b_10GbE
+ PORT MAP (
+ config_reset => mm_rst,
+
+ clk_ref_r => SA_CLK,
+
+ tx_serial_r => unb2b_board_front_io_serial_tx_arr(0),
+ rx_serial_r => unb2b_board_front_io_serial_rx_arr(0),
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ kernel_src_data => board_kernel_stream_src_10GbE_data,
+ kernel_src_valid => board_kernel_stream_src_10GbE_valid,
+ kernel_src_ready => board_kernel_stream_src_10GbE_ready,
+
+ kernel_snk_data => board_kernel_stream_snk_10GbE_data,
+ kernel_snk_valid => board_kernel_stream_snk_10GbE_valid,
+ kernel_snk_ready => board_kernel_stream_snk_10GbE_ready,
+
+ rx_status => ta2_unb2b_10gbe_rx_status_rx_status
+ );
+
+
+ -----------------------------
+ -- 1GbE Monitoring & Control
+ -----------------------------
+ u_ta2_unb2b_1GbE_mc : ENTITY work.ta2_unb2b_1GbE_mc
+ PORT MAP (
+ st_clk => st_clk,
+ st_rst => st_rst,
+
+ udp_tx_sosi => eth1g_udp_tx_sosi_arr(0),
+ udp_tx_siso => eth1g_udp_tx_siso_arr(0),
+ udp_rx_sosi => eth1g_udp_rx_sosi_arr(0),
+ udp_rx_siso => eth1g_udp_rx_siso_arr(0),
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ kernel_src_data => board_kernel_stream_src_1GbE_data,
+ kernel_src_valid => board_kernel_stream_src_1GbE_valid,
+ kernel_src_ready => board_kernel_stream_src_1GbE_ready,
+ kernel_snk_data => board_kernel_stream_snk_1GbE_data,
+ kernel_snk_valid => board_kernel_stream_snk_1GbE_valid,
+ kernel_snk_ready => board_kernel_stream_snk_1GbE_ready
+
+ );
+
+ ----------
+ -- ADC
+ ----------
+ u_ta2_unb2b_jesd204b : ENTITY work.ta2_unb2b_jesd204b
+ PORT MAP(
+ config_clk => mm_clk,
+ config_reset => mm_rst,
+
+ jesd204b_mosi => reg_ta2_unb2b_jesd204b_mosi,
+ jesd204b_miso => reg_ta2_unb2b_jesd204b_miso,
+
+ -- JESD204B external signals
+ jesd204b_refclk => BCK_REF_CLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n_arr => JESD204B_SYNC,
+
+ serial_rx_arr => BCK_RX,
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ kernel_src_data => board_kernel_stream_src_ADC_data,
+ kernel_src_valid => board_kernel_stream_src_ADC_valid,
+ kernel_src_ready => board_kernel_stream_src_ADC_ready
+
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Freeze wrapper instantiation
+ -----------------------------------------------------------------------------
+ freeze_wrapper_inst : freeze_wrapper
+ PORT MAP(
+ board_kernel_clk_clk => board_kernel_clk_clk,
+ board_kernel_clk2x_clk => board_kernel_clk2x_clk,
+ board_kernel_reset_reset_n => board_kernel_reset_reset_n_in,
+ board_kernel_irq_irq => board_kernel_irq_irq,
+ board_kernel_cra_waitrequest => board_kernel_cra_waitrequest,
+ board_kernel_cra_readdata => board_kernel_cra_readdata,
+ board_kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
+ board_kernel_cra_burstcount => board_kernel_cra_burstcount,
+ board_kernel_cra_writedata => board_kernel_cra_writedata,
+ board_kernel_cra_address => board_kernel_cra_address,
+ board_kernel_cra_write => board_kernel_cra_write,
+ board_kernel_cra_read => board_kernel_cra_read,
+ board_kernel_cra_byteenable => board_kernel_cra_byteenable,
+ board_kernel_cra_debugaccess => board_kernel_cra_debugaccess,
+ board_kernel_register_mem_address => board_kernel_register_mem_address,
+ board_kernel_register_mem_clken => board_kernel_register_mem_clken,
+ board_kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
+ board_kernel_register_mem_write => board_kernel_register_mem_write,
+ board_kernel_register_mem_readdata => board_kernel_register_mem_readdata,
+ board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
+ board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
+
+ board_kernel_stream_src_40GbE_data => ta2_unb2b_40GbE_src_out_arr(0).data(263 DOWNTO 0),
+ board_kernel_stream_src_40GbE_valid => ta2_unb2b_40GbE_src_out_arr(0).valid,
+ board_kernel_stream_src_40GbE_ready => ta2_unb2b_40GbE_src_in_arr(0).ready,
+ board_kernel_stream_snk_40GbE_data => ta2_unb2b_40GbE_snk_in_arr(0).data(263 DOWNTO 0),
+ board_kernel_stream_snk_40GbE_valid => ta2_unb2b_40GbE_snk_in_arr(0).valid,
+ board_kernel_stream_snk_40GbE_ready => ta2_unb2b_40GbE_snk_out_arr(0).ready,
+
+ board_kernel_stream_src_40GbE_ring_0_data => ta2_unb2b_40GbE_src_out_arr(1).data(263 DOWNTO 0),
+ board_kernel_stream_src_40GbE_ring_0_valid => ta2_unb2b_40GbE_src_out_arr(1).valid,
+ board_kernel_stream_src_40GbE_ring_0_ready => ta2_unb2b_40GbE_src_in_arr(1).ready,
+ board_kernel_stream_snk_40GbE_ring_0_data => ta2_unb2b_40GbE_snk_in_arr(1).data(263 DOWNTO 0),
+ board_kernel_stream_snk_40GbE_ring_0_valid => ta2_unb2b_40GbE_snk_in_arr(1).valid,
+ board_kernel_stream_snk_40GbE_ring_0_ready => ta2_unb2b_40GbE_snk_out_arr(1).ready,
+
+ board_kernel_stream_src_40GbE_ring_1_data => ta2_unb2b_40GbE_src_out_arr(2).data(263 DOWNTO 0),
+ board_kernel_stream_src_40GbE_ring_1_valid => ta2_unb2b_40GbE_src_out_arr(2).valid,
+ board_kernel_stream_src_40GbE_ring_1_ready => ta2_unb2b_40GbE_src_in_arr(2).ready,
+ board_kernel_stream_snk_40GbE_ring_1_data => ta2_unb2b_40GbE_snk_in_arr(2).data(263 DOWNTO 0),
+ board_kernel_stream_snk_40GbE_ring_1_valid => ta2_unb2b_40GbE_snk_in_arr(2).valid,
+ board_kernel_stream_snk_40GbE_ring_1_ready => ta2_unb2b_40GbE_snk_out_arr(2).ready,
+
+ board_kernel_stream_src_10GbE_data => board_kernel_stream_src_10GbE_data,
+ board_kernel_stream_src_10GbE_valid => board_kernel_stream_src_10GbE_valid,
+ board_kernel_stream_src_10GbE_ready => board_kernel_stream_src_10GbE_ready,
+ board_kernel_stream_snk_10GbE_data => board_kernel_stream_snk_10GbE_data,
+ board_kernel_stream_snk_10GbE_valid => board_kernel_stream_snk_10GbE_valid,
+ board_kernel_stream_snk_10GbE_ready => board_kernel_stream_snk_10GbE_ready,
+
+ board_kernel_stream_src_1GbE_data => board_kernel_stream_src_1GbE_data,
+ board_kernel_stream_src_1GbE_valid => board_kernel_stream_src_1GbE_valid,
+ board_kernel_stream_src_1GbE_ready => board_kernel_stream_src_1GbE_ready,
+ board_kernel_stream_snk_1GbE_data => board_kernel_stream_snk_1GbE_data,
+ board_kernel_stream_snk_1GbE_valid => board_kernel_stream_snk_1GbE_valid,
+ board_kernel_stream_snk_1GbE_ready => board_kernel_stream_snk_1GbE_ready,
+
+ board_kernel_stream_src_ADC_data => board_kernel_stream_src_ADC_data,
+ board_kernel_stream_src_ADC_valid => board_kernel_stream_src_ADC_valid,
+ board_kernel_stream_src_ADC_ready => board_kernel_stream_src_ADC_ready
+
+ );
i_reset_n <= NOT mm_rst;
+ i_kernel_rst <= NOT board_kernel_reset_reset_n;
+
+ -- Kernel should start later than BSP
+ u_common_areset : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '0',
+ g_delay_len => 9
+ )
+ PORT MAP (
+ in_rst => i_kernel_rst,
+ clk => board_kernel_clk_clk,
+ out_rst => board_kernel_reset_reset_n_in
+ );
+
-----------------------------------------------------------------------------
-- General control function
@@ -644,58 +689,6 @@ BEGIN
);
- ------------
- -- Front IO
- ------------
-
- -- put the QSFP_TX/RX ports into arrays
- i_QSFP_RX(0) <= QSFP_0_RX;
- i_QSFP_RX(1) <= QSFP_1_RX;
-
- QSFP_0_TX <= i_QSFP_TX(0);
- QSFP_1_TX <= i_QSFP_TX(1);
-
- u_unb2b_board_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io
- GENERIC MAP (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- PORT MAP (
- serial_tx_arr => unb2b_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2b_board_front_io_serial_rx_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
-
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
-
- QSFP_LED => QSFP_LED
- );
-
- ------------------------
- -- qsfp LEDs controller
- ------------------------
- unb2b_board_qsfp_leds_tx_src_in_arr(4).xon <= ta2_unb2b_40gbe_rx_status_rx_status;
- unb2b_board_qsfp_leds_tx_src_in_arr(0).xon <= ta2_unb2b_10gbe_rx_status_rx_status;
- u_unb2b_board_qsfp_leds : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds
- GENERIC MAP (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- PORT MAP (
- rst => mm_rst,
- clk => mm_clk,
-
- tx_siso_arr => unb2b_board_qsfp_leds_tx_src_in_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0)
- );
-
-
-
-----------------------------------------------------------------------------
-- Board qsys
-----------------------------------------------------------------------------
@@ -816,6 +809,13 @@ BEGIN
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_ta2_unb2b_jesd204b_address_export => reg_ta2_unb2b_jesd204b_mosi.address(7 DOWNTO 0),
+ reg_ta2_unb2b_jesd204b_read_export => reg_ta2_unb2b_jesd204b_mosi.rd,
+ reg_ta2_unb2b_jesd204b_readdata_export => reg_ta2_unb2b_jesd204b_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_ta2_unb2b_jesd204b_write_export => reg_ta2_unb2b_jesd204b_mosi.wr,
+ reg_ta2_unb2b_jesd204b_writedata_export => reg_ta2_unb2b_jesd204b_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_ta2_unb2b_jesd204b_waitrequest_export => reg_ta2_unb2b_jesd204b_miso.waitrequest,
+
kernel_cra_waitrequest => board_kernel_cra_waitrequest,
kernel_cra_readdata => board_kernel_cra_readdata,
kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
@@ -835,120 +835,9 @@ BEGIN
kernel_register_mem_write => board_kernel_register_mem_write,
kernel_register_mem_readdata => board_kernel_register_mem_readdata,
kernel_register_mem_writedata => board_kernel_register_mem_writedata,
- kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
-
- ta2_unb2b_10gbe_kernel_snk_data => board_kernel_stream_snk_10GbE_data,
- ta2_unb2b_10gbe_kernel_snk_ready => board_kernel_stream_snk_10GbE_ready,
- ta2_unb2b_10gbe_kernel_snk_valid => board_kernel_stream_snk_10GbE_valid,
- ta2_unb2b_10gbe_kernel_src_data => board_kernel_stream_src_10GbE_data,
- ta2_unb2b_10gbe_kernel_src_ready => board_kernel_stream_src_10GbE_ready,
- ta2_unb2b_10gbe_kernel_src_valid => board_kernel_stream_src_10GbE_valid,
- ta2_unb2b_10gbe_refclk_clk => SA_CLK,
- ta2_unb2b_10gbe_rx_serial_data_conduit => unb2b_board_front_io_serial_rx_arr(0),
- ta2_unb2b_10gbe_rx_status_rx_status => ta2_unb2b_10gbe_rx_status_rx_status,
- ta2_unb2b_10gbe_tx_serial_data_conduit => unb2b_board_front_io_serial_tx_arr(0),
-
- ta2_unb2b_40gbe_kernel_snk_data => board_kernel_stream_snk_40GbE_data,
- ta2_unb2b_40gbe_kernel_snk_ready => board_kernel_stream_snk_40GbE_ready,
- ta2_unb2b_40gbe_kernel_snk_valid => board_kernel_stream_snk_40GbE_valid,
- ta2_unb2b_40gbe_kernel_src_data => board_kernel_stream_src_40GbE_data,
- ta2_unb2b_40gbe_kernel_src_ready => board_kernel_stream_src_40GbE_ready,
- ta2_unb2b_40gbe_kernel_src_valid => board_kernel_stream_src_40GbE_valid,
- ta2_unb2b_40gbe_refclk_clk => SA_CLK,
- ta2_unb2b_40gbe_rx_serial_data_conduit => unb2b_board_front_io_serial_rx_arr(7 DOWNTO 4),
- ta2_unb2b_40gbe_rx_status_rx_status => ta2_unb2b_40gbe_rx_status_rx_status,
- ta2_unb2b_40gbe_tx_serial_data_conduit => unb2b_board_front_io_serial_tx_arr(7 DOWNTO 4),
-
- ta2_unb2b_1gbe_mc_kernel_snk_data => board_kernel_stream_snk_1GbE_data,
- ta2_unb2b_1gbe_mc_kernel_snk_ready => board_kernel_stream_snk_1GbE_ready,
- ta2_unb2b_1gbe_mc_kernel_snk_valid => board_kernel_stream_snk_1GbE_valid,
- ta2_unb2b_1gbe_mc_kernel_src_data => board_kernel_stream_src_1GbE_data,
- ta2_unb2b_1gbe_mc_kernel_src_ready => board_kernel_stream_src_1GbE_ready,
- ta2_unb2b_1gbe_mc_kernel_src_valid => board_kernel_stream_src_1GbE_valid,
-
- ta2_unb2b_1gbe_mc_st_clk_clk => st_clk,
- ta2_unb2b_1gbe_mc_st_rst_reset => st_rst,
-
- ta2_unb2b_1gbe_mc_udp_rx_snk_in_data => eth1g_udp_rx_sosi_arr(0).data(39 DOWNTO 0),
- ta2_unb2b_1gbe_mc_udp_rx_snk_in_empty => eth1g_udp_rx_sosi_arr(0).empty(1 DOWNTO 0),
- ta2_unb2b_1gbe_mc_udp_rx_snk_in_endofpacket => eth1g_udp_rx_sosi_arr(0).eop,
- ta2_unb2b_1gbe_mc_udp_rx_snk_in_startofpacket => eth1g_udp_rx_sosi_arr(0).sop,
- ta2_unb2b_1gbe_mc_udp_rx_snk_in_valid => eth1g_udp_rx_sosi_arr(0).valid,
- ta2_unb2b_1gbe_mc_udp_rx_snk_in_ready => eth1g_udp_rx_siso_arr(0).ready,
- ta2_unb2b_1gbe_mc_udp_rx_snk_in_xon_xon => eth1g_udp_rx_siso_arr(0).xon,
- ta2_unb2b_1gbe_mc_udp_tx_src_out_data => eth1g_udp_tx_sosi_arr(0).data(39 DOWNTO 0),
- ta2_unb2b_1gbe_mc_udp_tx_src_out_empty => eth1g_udp_tx_sosi_arr(0).empty(1 DOWNTO 0),
- ta2_unb2b_1gbe_mc_udp_tx_src_out_endofpacket => eth1g_udp_tx_sosi_arr(0).eop,
- ta2_unb2b_1gbe_mc_udp_tx_src_out_startofpacket => eth1g_udp_tx_sosi_arr(0).sop,
- ta2_unb2b_1gbe_mc_udp_tx_src_out_valid => eth1g_udp_tx_sosi_arr(0).valid,
- ta2_unb2b_1gbe_mc_udp_tx_src_out_ready => eth1g_udp_tx_siso_arr(0).ready,
- ta2_unb2b_1gbe_mc_udp_tx_src_out_xon_xon => eth1g_udp_tx_siso_arr(0).xon,
-
- ta2_unb2b_jesd204b_kernel_src_data => board_kernel_stream_src_ADC_data,
- ta2_unb2b_jesd204b_kernel_src_ready => board_kernel_stream_src_ADC_ready,
- ta2_unb2b_jesd204b_kernel_src_valid => board_kernel_stream_src_ADC_valid,
- ta2_unb2b_jesd204b_jesd204b_refclk_clk => BCK_REF_CLK,
- ta2_unb2b_jesd204b_jesd204b_sysref_conduit => JESD204B_SYSREF,
- ta2_unb2b_jesd204b_jesd204b_sync_n_conduit => JESD204B_SYNC,
- ta2_unb2b_jesd204b_serial_rx_arr_conduit => BCK_RX
-
-
- );
-
- -----------------------------------------------------------------------------
- -- Freeze wrapper instantiation
- -----------------------------------------------------------------------------
- freeze_wrapper_inst : freeze_wrapper
- PORT MAP(
- board_kernel_clk_clk => board_kernel_clk_clk,
- board_kernel_clk2x_clk => board_kernel_clk2x_clk,
- board_kernel_reset_reset_n => board_kernel_reset_reset_n,
- board_kernel_irq_irq => board_kernel_irq_irq,
- board_kernel_cra_waitrequest => board_kernel_cra_waitrequest,
- board_kernel_cra_readdata => board_kernel_cra_readdata,
- board_kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
- board_kernel_cra_burstcount => board_kernel_cra_burstcount,
- board_kernel_cra_writedata => board_kernel_cra_writedata,
- board_kernel_cra_address => board_kernel_cra_address,
- board_kernel_cra_write => board_kernel_cra_write,
- board_kernel_cra_read => board_kernel_cra_read,
- board_kernel_cra_byteenable => board_kernel_cra_byteenable,
- board_kernel_cra_debugaccess => board_kernel_cra_debugaccess,
- board_kernel_register_mem_address => board_kernel_register_mem_address,
- board_kernel_register_mem_clken => board_kernel_register_mem_clken,
- board_kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
- board_kernel_register_mem_write => board_kernel_register_mem_write,
- board_kernel_register_mem_readdata => board_kernel_register_mem_readdata,
- board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
- board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
-
- board_kernel_stream_src_40GbE_data => board_kernel_stream_src_40GbE_data,
- board_kernel_stream_src_40GbE_valid => board_kernel_stream_src_40GbE_valid,
- board_kernel_stream_src_40GbE_ready => board_kernel_stream_src_40GbE_ready,
- board_kernel_stream_snk_40GbE_data => board_kernel_stream_snk_40GbE_data,
- board_kernel_stream_snk_40GbE_valid => board_kernel_stream_snk_40GbE_valid,
- board_kernel_stream_snk_40GbE_ready => board_kernel_stream_snk_40GbE_ready,
-
- board_kernel_stream_src_10GbE_data => board_kernel_stream_src_10GbE_data,
- board_kernel_stream_src_10GbE_valid => board_kernel_stream_src_10GbE_valid,
- board_kernel_stream_src_10GbE_ready => board_kernel_stream_src_10GbE_ready,
- board_kernel_stream_snk_10GbE_data => board_kernel_stream_snk_10GbE_data,
- board_kernel_stream_snk_10GbE_valid => board_kernel_stream_snk_10GbE_valid,
- board_kernel_stream_snk_10GbE_ready => board_kernel_stream_snk_10GbE_ready,
-
- board_kernel_stream_src_1GbE_data => board_kernel_stream_src_1GbE_data,
- board_kernel_stream_src_1GbE_valid => board_kernel_stream_src_1GbE_valid,
- board_kernel_stream_src_1GbE_ready => board_kernel_stream_src_1GbE_ready,
- board_kernel_stream_snk_1GbE_data => board_kernel_stream_snk_1GbE_data,
- board_kernel_stream_snk_1GbE_valid => board_kernel_stream_snk_1GbE_valid,
- board_kernel_stream_snk_1GbE_ready => board_kernel_stream_snk_1GbE_ready,
-
- board_kernel_stream_src_ADC_data => board_kernel_stream_src_ADC_data,
- board_kernel_stream_src_ADC_valid => board_kernel_stream_src_ADC_valid,
- board_kernel_stream_src_ADC_ready => board_kernel_stream_src_ADC_ready
+ kernel_register_mem_byteenable => board_kernel_register_mem_byteenable
);
-
END str;
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top_components_pkg.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top_components_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a84c59fdcd5c8bc1feffe28f49568958f6933a33
--- /dev/null
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top_components_pkg.vhd
@@ -0,0 +1,253 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+PACKAGE top_components_pkg IS
+
+ component board is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ kernel_clk_clk : out std_logic; -- clk
+ kernel_clk2x_clk : out std_logic; -- clk
+ kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
+ kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
+ kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
+ kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
+ kernel_cra_address : out std_logic_vector(29 downto 0); -- address
+ kernel_cra_write : out std_logic; -- write
+ kernel_cra_read : out std_logic; -- read
+ kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
+ kernel_cra_debugaccess : out std_logic; -- debugaccess
+ kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
+ kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
+ kernel_register_mem_address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address
+ kernel_register_mem_clken : in std_logic := 'X'; -- clken
+ kernel_register_mem_chipselect : in std_logic := 'X'; -- chipselect
+ kernel_register_mem_write : in std_logic := 'X'; -- write
+ kernel_register_mem_readdata : out std_logic_vector(255 downto 0); -- readdata
+ kernel_register_mem_writedata : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
+ kernel_register_mem_byteenable : in std_logic_vector(31 downto 0) := (others => 'X'); -- byteenable
+ kernel_reset_reset_n : out std_logic; -- reset_n
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_jesd204b_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_ta2_unb2b_jesd204b_clk_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_read_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ta2_unb2b_jesd204b_reset_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_waitrequest_export : in std_logic := 'X'; -- export
+ reg_ta2_unb2b_jesd204b_write_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component board;
+
+
+ component freeze_wrapper is
+ port (
+ board_kernel_clk_clk : in std_logic; --input
+ board_kernel_clk2x_clk : in std_logic; --input
+ board_kernel_reset_reset_n : in std_logic; --input
+ board_kernel_irq_irq : out std_logic_vector(0 downto 0); --output [0:0]
+ board_kernel_cra_waitrequest : out std_logic; --output
+ board_kernel_cra_readdata : out std_logic_vector(63 downto 0); --output [63:0]
+ board_kernel_cra_readdatavalid : out std_logic; --output
+ board_kernel_cra_burstcount : in std_logic_vector(0 downto 0); --input [0:0]
+ board_kernel_cra_writedata : in std_logic_vector(63 downto 0); --input [63:0]
+ board_kernel_cra_address : in std_logic_vector(29 downto 0); --input [29:0]
+ board_kernel_cra_write : in std_logic; --input
+ board_kernel_cra_read : in std_logic; --input
+ board_kernel_cra_byteenable : in std_logic_vector(7 downto 0); --input [7:0]
+ board_kernel_cra_debugaccess : in std_logic; --input
+
+ board_kernel_register_mem_address : out std_logic_vector(6 downto 0); -- := (others => 'X'); -- address
+ board_kernel_register_mem_clken : out std_logic; -- := 'X'; -- clken
+ board_kernel_register_mem_chipselect : out std_logic; -- := 'X'; -- chipselect
+ board_kernel_register_mem_write : out std_logic; -- := 'X'; -- write
+ board_kernel_register_mem_readdata : in std_logic_vector(255 downto 0); -- readdata
+ board_kernel_register_mem_writedata : out std_logic_vector(255 downto 0); -- := (others => 'X'); -- writedata
+ board_kernel_register_mem_byteenable : out std_logic_vector(31 downto 0); -- := (others => 'X'); -- byteenable
+
+ board_kernel_stream_src_40GbE_data : in std_logic_vector(263 downto 0);
+ board_kernel_stream_src_40GbE_valid : in std_logic;
+ board_kernel_stream_src_40GbE_ready : out std_logic;
+ board_kernel_stream_snk_40GbE_data : out std_logic_vector(263 downto 0);
+ board_kernel_stream_snk_40GbE_valid : out std_logic;
+ board_kernel_stream_snk_40GbE_ready : in std_logic;
+
+ board_kernel_stream_src_40GbE_ring_0_data : in std_logic_vector(263 downto 0);
+ board_kernel_stream_src_40GbE_ring_0_valid : in std_logic;
+ board_kernel_stream_src_40GbE_ring_0_ready : out std_logic;
+ board_kernel_stream_snk_40GbE_ring_0_data : out std_logic_vector(263 downto 0);
+ board_kernel_stream_snk_40GbE_ring_0_valid : out std_logic;
+ board_kernel_stream_snk_40GbE_ring_0_ready : in std_logic;
+
+ board_kernel_stream_src_40GbE_ring_1_data : in std_logic_vector(263 downto 0);
+ board_kernel_stream_src_40GbE_ring_1_valid : in std_logic;
+ board_kernel_stream_src_40GbE_ring_1_ready : out std_logic;
+ board_kernel_stream_snk_40GbE_ring_1_data : out std_logic_vector(263 downto 0);
+ board_kernel_stream_snk_40GbE_ring_1_valid : out std_logic;
+ board_kernel_stream_snk_40GbE_ring_1_ready : in std_logic;
+
+ board_kernel_stream_src_10GbE_data : in std_logic_vector(71 downto 0);
+ board_kernel_stream_src_10GbE_valid : in std_logic;
+ board_kernel_stream_src_10GbE_ready : out std_logic;
+ board_kernel_stream_snk_10GbE_data : out std_logic_vector(71 downto 0);
+ board_kernel_stream_snk_10GbE_valid : out std_logic;
+ board_kernel_stream_snk_10GbE_ready : in std_logic;
+
+ board_kernel_stream_src_1GbE_data : in std_logic_vector(39 downto 0);
+ board_kernel_stream_src_1GbE_valid : in std_logic;
+ board_kernel_stream_src_1GbE_ready : out std_logic;
+ board_kernel_stream_snk_1GbE_data : out std_logic_vector(39 downto 0);
+ board_kernel_stream_snk_1GbE_valid : out std_logic;
+ board_kernel_stream_snk_1GbE_ready : in std_logic;
+
+ board_kernel_stream_src_ADC_data : in std_logic_vector(15 downto 0);
+ board_kernel_stream_src_ADC_valid : in std_logic;
+ board_kernel_stream_src_ADC_ready : out std_logic
+
+ );
+ end component freeze_wrapper;
+
+END top_components_pkg;
+
+
diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg
index df646d9c66c8a5c163941d091858556656929887..c7c3d8323ed975947cecfff9b124f78a0391aa0a 100644
--- a/libraries/base/common/hdllib.cfg
+++ b/libraries/base/common/hdllib.cfg
@@ -109,8 +109,6 @@ synth_files =
src/vhdl/common_fifo_rd.vhd
src/vhdl/common_blockreg.vhd
src/vhdl/common_fifo_dc_lock_control.vhd
- src/vhdl/common_mem_master_mux.vhd
- src/vhdl/common_mem_bus.vhd
src/vhdl/common_mem_mux.vhd
src/vhdl/common_mem_demux.vhd
src/vhdl/common_reg_cross_domain.vhd
@@ -164,8 +162,6 @@ test_bench_files =
tb/vhdl/tb_common_init.vhd
tb/vhdl/tb_common_int2float.vhd
tb/vhdl/tb_common_led_controller.vhd
- tb/vhdl/tb_common_mem_master_mux.vhd
- tb/vhdl/tb_common_mem_bus.vhd
tb/vhdl/tb_common_mem_mux.vhd
tb/vhdl/tb_common_multiplexer.vhd
tb/vhdl/tb_common_operation_tree.vhd
@@ -197,7 +193,6 @@ test_bench_files =
tb/vhdl/tb_tb_common_add_sub.vhd
tb/vhdl/tb_tb_common_adder_tree.vhd
- tb/vhdl/tb_tb_common_mem_bus.vhd
tb/vhdl/tb_tb_common_fanout_tree.vhd
tb/vhdl/tb_tb_common_multiplexer.vhd
tb/vhdl/tb_tb_common_operation_tree.vhd
@@ -210,7 +205,6 @@ test_bench_files =
regression_test_vhdl =
tb/vhdl/tb_common_fifo_rd.vhd
- tb/vhdl/tb_common_mem_master_mux.vhd
tb/vhdl/tb_common_mem_mux.vhd
tb/vhdl/tb_common_paged_ram_crw_crw.vhd
tb/vhdl/tb_common_pulser_us_ms_s.vhd
@@ -225,7 +219,6 @@ regression_test_vhdl =
tb/vhdl/tb_tb_common_adder_tree.vhd
tb/vhdl/tb_tb_common_add_sub.vhd
- tb/vhdl/tb_tb_common_mem_bus.vhd
tb/vhdl/tb_tb_common_fanout_tree.vhd
tb/vhdl/tb_tb_common_multiplexer.vhd
tb/vhdl/tb_tb_common_operation_tree.vhd
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 98601eaeae2dc0f4bb68c75d90f245efba85e8d1..750cd5e6bebe818c7667deffa69778c34d2f8426 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -124,8 +124,8 @@ PACKAGE common_pkg IS
TYPE t_slv_512_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(511 DOWNTO 0);
TYPE t_slv_1024_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(1023 DOWNTO 0);
- CONSTANT c_boolean_arr : t_boolean_arr := (TRUE, FALSE); -- array all possible values that can be iterated over
- CONSTANT c_nat_boolean_arr : t_nat_boolean_arr := (TRUE, FALSE); -- array all possible values that can be iterated over
+ CONSTANT c_boolean_arr : t_boolean_arr := (TRUE, FALSE); -- array the two possible boolean values that can be iterated over
+ CONSTANT c_nat_boolean_arr : t_nat_boolean_arr := (TRUE, FALSE); -- array the two possible boolean values that can be iterated over
TYPE t_integer_matrix IS ARRAY (INTEGER RANGE <>, INTEGER RANGE <>) OF INTEGER;
TYPE t_boolean_matrix IS ARRAY (INTEGER RANGE <>, INTEGER RANGE <>) OF BOOLEAN;
@@ -207,6 +207,9 @@ PACKAGE common_pkg IS
FUNCTION orv( slv : STD_LOGIC_VECTOR) RETURN STD_LOGIC; -- alias of vector_or
FUNCTION xorv(slv : STD_LOGIC_VECTOR) RETURN STD_LOGIC; -- alias of vector_xor
+ FUNCTION array_and(arr : t_nat_boolean_arr) RETURN BOOLEAN;
+ FUNCTION array_or( arr : t_nat_boolean_arr) RETURN BOOLEAN;
+
FUNCTION matrix_and(mat : t_sl_matrix; wi, wj : NATURAL) RETURN STD_LOGIC; -- '1' when all matrix bits are '1' else '0'
FUNCTION matrix_or( mat : t_sl_matrix; wi, wj : NATURAL) RETURN STD_LOGIC; -- '0' when all matrix bits are '0' else '1'
@@ -297,6 +300,7 @@ PACKAGE common_pkg IS
FUNCTION sel_n(sel : NATURAL; a, b, c, d, e, f, g, h, i, j : STRING) RETURN STRING; -- 10
FUNCTION array_init(init : STD_LOGIC; nof : NATURAL) RETURN STD_LOGIC_VECTOR; -- useful to init a unconstrained array of size 1
+ FUNCTION array_init(init : BOOLEAN; nof : NATURAL) RETURN t_nat_boolean_arr; -- useful to init a unconstrained array of size 1
FUNCTION array_init(init, nof : NATURAL) RETURN t_natural_arr; -- useful to init a unconstrained array of size 1
FUNCTION array_init(init, nof : NATURAL) RETURN t_nat_natural_arr; -- useful to init a unconstrained array of size 1
FUNCTION array_init(init, nof, incr : NATURAL) RETURN t_natural_arr; -- useful to init an array with incrementing numbers
@@ -310,12 +314,21 @@ PACKAGE common_pkg IS
FUNCTION init_slv_64_matrix(nof_a, nof_b, k : INTEGER) RETURN t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
-- Concatenate two or more STD_LOGIC_VECTORs into a single STD_LOGIC_VECTOR or extract one of them from a concatenated STD_LOGIC_VECTOR
+ -- . Note that using func_slv_concat() without the BOOLEAN use_* is equivalent to using the
+ -- slv concatenation operator & directly. However this overloaded func_slv_concat() is
+ -- still nice to have, because it shows the relation with the inverse func_slv_extract().
FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a, b, c, d, e, f : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e : BOOLEAN; a, b, c, d, e : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
FUNCTION func_slv_concat( use_a, use_b, use_c, use_d : BOOLEAN; a, b, c, d : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
FUNCTION func_slv_concat( use_a, use_b, use_c : BOOLEAN; a, b, c : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
FUNCTION func_slv_concat( use_a, use_b : BOOLEAN; a, b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c, d, e, f : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c, d, e : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c, d : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL) RETURN NATURAL;
FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w : NATURAL) RETURN NATURAL;
FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : BOOLEAN; a_w, b_w, c_w, d_w, e_w : NATURAL) RETURN NATURAL;
@@ -328,6 +341,12 @@ PACKAGE common_pkg IS
FUNCTION func_slv_extract( use_a, use_b, use_c, use_d : BOOLEAN; a_w, b_w, c_w, d_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
FUNCTION func_slv_extract( use_a, use_b, use_c : BOOLEAN; a_w, b_w, c_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
FUNCTION func_slv_extract( use_a, use_b : BOOLEAN; a_w, b_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w, f_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w, d_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
FUNCTION TO_UINT(vec : STD_LOGIC_VECTOR) RETURN NATURAL; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
FUNCTION TO_SINT(vec : STD_LOGIC_VECTOR) RETURN INTEGER;
@@ -743,6 +762,20 @@ PACKAGE BODY common_pkg IS
RETURN vector_tree(slv, "XOR");
END;
+ FUNCTION array_and(arr : t_nat_boolean_arr) RETURN BOOLEAN IS
+ VARIABLE v_slv : STD_LOGIC_VECTOR(arr'RANGE);
+ BEGIN
+ FOR I IN arr'RANGE LOOP v_slv(I) := sel_a_b(arr(I), '1', '0'); END LOOP; -- wire map boolean arr to slv
+ RETURN sel_a_b(vector_and(v_slv) = '1', TRUE, FALSE); -- use vector_tree to determine result
+ END;
+
+ FUNCTION array_or(arr : t_nat_boolean_arr) RETURN BOOLEAN IS
+ VARIABLE v_slv : STD_LOGIC_VECTOR(arr'RANGE);
+ BEGIN
+ FOR I IN arr'RANGE LOOP v_slv(I) := sel_a_b(arr(I), '1', '0'); END LOOP; -- wire map boolean arr to slv
+ RETURN sel_a_b(vector_or(v_slv) = '1', TRUE, FALSE); -- use vector_tree to determine result
+ END;
+
FUNCTION matrix_and(mat : t_sl_matrix; wi, wj : NATURAL) RETURN STD_LOGIC IS
VARIABLE v_mat : t_sl_matrix(0 TO wi-1, 0 TO wj-1) := mat; -- map to fixed range
VARIABLE v_result : STD_LOGIC := '1';
@@ -1311,6 +1344,15 @@ PACKAGE BODY common_pkg IS
RETURN v_arr;
END;
+ FUNCTION array_init(init : BOOLEAN; nof : NATURAL) RETURN t_nat_boolean_arr IS
+ VARIABLE v_arr : t_nat_boolean_arr(0 TO nof-1);
+ BEGIN
+ FOR I IN v_arr'RANGE LOOP
+ v_arr(I) := init;
+ END LOOP;
+ RETURN v_arr;
+ END;
+
FUNCTION array_init(init, nof : NATURAL) RETURN t_natural_arr IS
VARIABLE v_arr : t_natural_arr(0 TO nof-1);
BEGIN
@@ -1460,6 +1502,36 @@ PACKAGE BODY common_pkg IS
RETURN func_slv_concat(use_a, use_b, FALSE, FALSE, FALSE, FALSE, FALSE, a, b, "0", "0", "0", "0", "0");
END func_slv_concat;
+ FUNCTION func_slv_concat(a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_concat(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, a, b, c, d, e, f, g);
+ END func_slv_concat;
+
+ FUNCTION func_slv_concat(a, b, c, d, e, f : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_concat(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, a, b, c, d, e, f);
+ END func_slv_concat;
+
+ FUNCTION func_slv_concat(a, b, c, d, e: STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_concat(TRUE, TRUE, TRUE, TRUE, TRUE, a, b, c, d, e);
+ END func_slv_concat;
+
+ FUNCTION func_slv_concat(a, b, c, d : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_concat(TRUE, TRUE, TRUE, TRUE, a, b, c, d);
+ END func_slv_concat;
+
+ FUNCTION func_slv_concat(a, b, c : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_concat(TRUE, TRUE, TRUE, a, b, c);
+ END func_slv_concat;
+
+ FUNCTION func_slv_concat(a, b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_concat(TRUE, TRUE, a, b);
+ END func_slv_concat;
+
FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL) RETURN NATURAL IS
VARIABLE v_len : NATURAL := 0;
BEGIN
@@ -1570,6 +1642,36 @@ PACKAGE BODY common_pkg IS
RETURN func_slv_extract(use_a, use_b, FALSE, FALSE, FALSE, FALSE, FALSE, a_w, b_w, 0, 0, 0, 0, 0, vec, sel);
END func_slv_extract;
+ FUNCTION func_slv_extract(a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_extract(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, a_w, b_w, c_w, d_w, e_w, f_w, g_w, vec, sel);
+ END func_slv_extract;
+
+ FUNCTION func_slv_extract(a_w, b_w, c_w, d_w, e_w, f_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_extract(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, a_w, b_w, c_w, d_w, e_w, f_w, vec, sel);
+ END func_slv_extract;
+
+ FUNCTION func_slv_extract(a_w, b_w, c_w, d_w, e_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_extract(TRUE, TRUE, TRUE, TRUE, TRUE, a_w, b_w, c_w, d_w, e_w, vec, sel);
+ END func_slv_extract;
+
+ FUNCTION func_slv_extract(a_w, b_w, c_w, d_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_extract(TRUE, TRUE, TRUE, TRUE, a_w, b_w, c_w, d_w, vec, sel);
+ END func_slv_extract;
+
+ FUNCTION func_slv_extract(a_w, b_w, c_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_extract(TRUE, TRUE, TRUE, a_w, b_w, c_w, vec, sel);
+ END func_slv_extract;
+
+ FUNCTION func_slv_extract(a_w, b_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_extract(TRUE, TRUE, a_w, b_w, vec, sel);
+ END func_slv_extract;
+
FUNCTION TO_UINT(vec : STD_LOGIC_VECTOR) RETURN NATURAL IS
BEGIN
diff --git a/libraries/base/common/tb/vhdl/tb_common_mem_bus.vhd b/libraries/base/common/tb/vhdl/tb_common_mem_bus.vhd
deleted file mode 100644
index ed4bb56f4d0a4556f216165683a8dd45b02a8c9d..0000000000000000000000000000000000000000
--- a/libraries/base/common/tb/vhdl/tb_common_mem_bus.vhd
+++ /dev/null
@@ -1,177 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright 2020
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- Licensed under the Apache License, Version 2.0 (the "License");
--- you may not use this file except in compliance with the License.
--- You may obtain a copy of the License at
---
--- http://www.apache.org/licenses/LICENSE-2.0
---
--- Unless required by applicable law or agreed to in writing, software
--- distributed under the License is distributed on an "AS IS" BASIS,
--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--- See the License for the specific language governing permissions and
--- limitations under the License.
---
--------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------
---
--- Author: E. Kooistra
--- Purpose: Test bench for common_mem_bus.vhd
--- Remark:
--- . This test bench covers:
--- . g_nof_slaves >= 1
--- . g_pipeline_mosi, g_pipeline_miso
--- . g_rd_latency >= 1 (using 0 is supported by common_mem_bus, but not by
--- the common_ram_r_w in u_slaves)
--- . same g_rd_latency for all slaves
--- . same g_width for all slaves
--- . regular base address spacing of slaves in c_base_arr
--- . The common_mem_bus.vhd can support a list of arbitrary width slaves, but
--- this tb_common_mem_bus test bench uses an array of fixed width slaves.
--- It is considered sufficient coverage for this tb and the corresponding
--- multi tb_tb to also only support regular c_base_arr, same g_rd_latency,
--- and same g_width for all slaves. The tb_common_mem_master_mux also uses a
--- common_mem_bus.vhd and the tb_common_mem_master_mux does uses an array of
--- arbitrary width slaves.
---
--------------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE work.common_pkg.ALL;
-USE work.common_mem_pkg.ALL;
-USE work.tb_common_pkg.ALL;
-USE work.tb_common_mem_pkg.ALL;
-
-ENTITY tb_common_mem_bus IS
- GENERIC (
- g_nof_slaves : POSITIVE := 2; -- Number of slave memory interfaces on the MM bus array.
- g_base_offset : NATURAL := 0; -- Address of first slave on the MM bus
- g_width_w : POSITIVE := 4; -- Address width of each slave memory in the MM bus array.
- g_rd_latency : NATURAL := 1; -- Read latency of the slaves slave
- g_pipeline_mosi : BOOLEAN := FALSE;
- g_pipeline_miso : BOOLEAN := TRUE
- );
-END tb_common_mem_bus;
-
--- Usage:
--- > as 10
--- > run -all
-
-
-ARCHITECTURE tb OF tb_common_mem_bus IS
-
- CONSTANT mm_clk_period : TIME := 10 ns;
-
- CONSTANT c_slave_span : NATURAL := 2**g_width_w;
- CONSTANT c_base_arr : t_nat_natural_arr := array_init(g_base_offset, g_nof_slaves, c_slave_span); -- Address base per slave
- CONSTANT c_width_arr : t_nat_natural_arr := array_init( g_width_w, g_nof_slaves); -- Address width per slave
- CONSTANT c_rd_latency_arr : t_nat_natural_arr := array_init( g_rd_latency, g_nof_slaves); -- Read latency per slave
-
- CONSTANT c_mosi_latency : NATURAL := sel_a_b(g_pipeline_mosi, 1, 0);
- CONSTANT c_miso_latency : NATURAL := sel_a_b(g_pipeline_miso, 1, 0);
- CONSTANT c_read_latency : NATURAL := c_mosi_latency + g_rd_latency + c_miso_latency;
-
- CONSTANT c_data_w : NATURAL := 32;
- CONSTANT c_test_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => g_width_w,
- dat_w => c_data_w,
- nof_dat => 2**g_width_w,
- init_sl => '0');
- SIGNAL mm_rst : STD_LOGIC;
- SIGNAL mm_clk : STD_LOGIC := '1';
- SIGNAL tb_end : STD_LOGIC;
-
- SIGNAL mosi_arr : t_mem_mosi_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_mosi_rst);
- SIGNAL miso_arr : t_mem_miso_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_miso_rst);
- SIGNAL mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL miso : t_mem_miso := c_mem_miso_rst;
-
- -- Debug signals for monitoring in simulation Wave window
- SIGNAL dbg_c_base_arr : t_nat_natural_arr(0 TO g_nof_slaves-1) := c_base_arr;
- SIGNAL dbg_c_width_arr : t_nat_natural_arr(0 TO g_nof_slaves-1) := c_width_arr;
- SIGNAL dbg_c_rd_latency_arr : t_nat_natural_arr(0 TO g_nof_slaves-1) := c_rd_latency_arr;
-
-BEGIN
-
- mm_clk <= NOT mm_clk OR tb_end AFTER mm_clk_period/2;
- mm_rst <= '1', '0' AFTER mm_clk_period*5;
-
- p_stimuli : PROCESS
- VARIABLE v_data : INTEGER;
- BEGIN
- tb_end <= '0';
- mosi <= c_mem_mosi_rst;
-
- -- Wait until reset is released
- proc_common_wait_until_low(mm_clk, mm_rst);
- proc_common_wait_some_cycles(mm_clk, 10);
-
- -- Write the whole memory range
- FOR I IN 0 TO g_nof_slaves-1 LOOP
- FOR J IN 0 TO 2**g_width_w-1 LOOP
- proc_mem_mm_bus_wr(g_base_offset + I*2**g_width_w + J, I+J, mm_clk, mosi);
- END LOOP;
- END LOOP;
-
- -- Read back the whole range and check if data is as expected
- FOR I IN 0 TO g_nof_slaves-1 LOOP
- FOR J IN 0 TO 2**g_width_w-1 LOOP
- proc_mem_mm_bus_rd(g_base_offset + I*2**g_width_w + J, mm_clk, mosi);
- proc_common_wait_some_cycles(mm_clk, c_read_latency);
- v_data := TO_UINT(miso.rddata(31 DOWNTO 0));
- IF v_data /= I+J THEN
- REPORT "Error! Readvalue is not as expected" SEVERITY ERROR;
- END IF;
- END LOOP;
- END LOOP;
-
- proc_common_wait_some_cycles(mm_clk, 10);
- tb_end <= '1';
- WAIT;
- END PROCESS;
-
- u_slaves : FOR I IN 0 TO g_nof_slaves-1 GENERATE
- u_ram : ENTITY work.common_ram_r_w
- GENERIC MAP (
- g_ram => c_test_ram,
- g_init_file => "UNUSED"
- )
- PORT MAP (
- rst => mm_rst,
- clk => mm_clk,
- clken => '1',
- wr_en => mosi_arr(I).wr,
- wr_adr => mosi_arr(I).address(g_width_w-1 DOWNTO 0),
- wr_dat => mosi_arr(I).wrdata(c_data_w-1 DOWNTO 0),
- rd_en => mosi_arr(I).rd,
- rd_adr => mosi_arr(I).address(g_width_w-1 DOWNTO 0),
- rd_dat => miso_arr(I).rddata(c_data_w-1 DOWNTO 0),
- rd_val => miso_arr(I).rdval
- );
- END GENERATE;
-
- d_dut: ENTITY work.common_mem_bus
- GENERIC MAP (
- g_nof_slaves => g_nof_slaves,
- g_base_arr => c_base_arr,
- g_width_arr => c_width_arr,
- g_rd_latency_arr => c_rd_latency_arr,
- g_pipeline_mosi => g_pipeline_mosi,
- g_pipeline_miso => g_pipeline_miso
- )
- PORT MAP (
- mm_clk => mm_clk,
- master_mosi => mosi,
- master_miso => miso,
- slave_mosi_arr => mosi_arr,
- slave_miso_arr => miso_arr
- );
-
-END tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_mem_master_mux.vhd b/libraries/base/common/tb/vhdl/tb_common_mem_master_mux.vhd
deleted file mode 100644
index bab3efcee8670c745fb3cfedd34c336f3fc0fac2..0000000000000000000000000000000000000000
--- a/libraries/base/common/tb/vhdl/tb_common_mem_master_mux.vhd
+++ /dev/null
@@ -1,196 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright 2020
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- Licensed under the Apache License, Version 2.0 (the "License");
--- you may not use this file except in compliance with the License.
--- You may obtain a copy of the License at
---
--- http://www.apache.org/licenses/LICENSE-2.0
---
--- Unless required by applicable law or agreed to in writing, software
--- distributed under the License is distributed on an "AS IS" BASIS,
--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--- See the License for the specific language governing permissions and
--- limitations under the License.
---
--------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------
---
--- Author: E. Kooistra
--- Purpose: Test bench for common_mem_master_mux.vhd and also common_mem_bus
--- Description:
--- The test bench uses common_mem_master_mux to access a RAM via an array of
--- masters. The array of masters is modelled using a stimuli from a single
--- master that get demultiplexed to the array of masters using
--- common_mem_bus. The address space of the RAM is defined by the g_base_arr
--- and g_width_arr that define the common_mem_bus. Therefore this test bench
--- implicitely also verifies common_mem_bus.vhd.
---
--- stimuli master mux
--- mosi mosi_arr mosi
--- p_stimuli ----------> common -----------> common --------> RAM
--- mem mem
--- bus master
--- mux
---
--- Remark:
--- In an application it is typical to use common_mem_master_mux to connect
--- mulitple masters to multiple slabes via a common_mem_bus MM bus.
--------------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE work.common_pkg.ALL;
-USE work.common_mem_pkg.ALL;
-USE work.tb_common_pkg.ALL;
-USE work.tb_common_mem_pkg.ALL;
-
-ENTITY tb_common_mem_master_mux IS
- GENERIC (
- g_nof_masters : POSITIVE := 2; -- Number of master memory interfaces on the MM bus array.
- g_base_arr : t_nat_natural_arr := (0, 256); -- Address base per slave port of common_mem_bus
- g_width_arr : t_nat_natural_arr := (4, 8); -- Address width per slave port of common_mem_bus
- g_pipeline_bus_mosi : BOOLEAN := FALSE;
- g_pipeline_bus_miso : BOOLEAN := FALSE
- );
-END tb_common_mem_master_mux;
-
--- Usage:
--- > as 10
--- > run -all
-
-
-ARCHITECTURE tb OF tb_common_mem_master_mux IS
-
- CONSTANT mm_clk_period : TIME := 10 ns;
-
- CONSTANT c_bus_mosi_latency : NATURAL := sel_a_b(g_pipeline_bus_mosi, 1, 0);
- CONSTANT c_bus_miso_latency : NATURAL := sel_a_b(g_pipeline_bus_miso, 1, 0);
- CONSTANT c_ram_rd_latency : NATURAL := 1;
- CONSTANT c_ram_rd_latency_arr : t_nat_natural_arr := array_init(c_ram_rd_latency, g_nof_masters);
-
- CONSTANT c_read_latency : NATURAL := c_bus_mosi_latency + c_ram_rd_latency + c_bus_miso_latency;
-
- CONSTANT c_addr_w : NATURAL := largest(ceil_log2(largest(g_base_arr)), largest(g_width_arr)) + 1;
- CONSTANT c_data_w : NATURAL := 32;
- CONSTANT c_test_ram : t_c_mem := (latency => c_ram_rd_latency,
- adr_w => c_addr_w,
- dat_w => c_data_w,
- nof_dat => 2**c_addr_w,
- init_sl => '0');
- SIGNAL mm_rst : STD_LOGIC;
- SIGNAL mm_clk : STD_LOGIC := '1';
- SIGNAL tb_end : STD_LOGIC;
-
- SIGNAL stimuli_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL stimuli_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL master_mosi_arr : t_mem_mosi_arr(0 TO g_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
- SIGNAL master_miso_arr : t_mem_miso_arr(0 TO g_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
- SIGNAL mux_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL mux_miso : t_mem_miso := c_mem_miso_rst;
-
-BEGIN
-
- mm_clk <= NOT mm_clk OR tb_end AFTER mm_clk_period/2;
- mm_rst <= '1', '0' AFTER mm_clk_period*5;
-
- p_stimuli : PROCESS
- VARIABLE v_base : NATURAL;
- VARIABLE v_span : NATURAL;
- VARIABLE v_data : INTEGER;
- BEGIN
- tb_end <= '0';
- stimuli_mosi <= c_mem_mosi_rst;
-
- -- Wait until reset is released
- proc_common_wait_until_low(mm_clk, mm_rst);
- proc_common_wait_some_cycles(mm_clk, 10);
-
- -- Repeat twice to have wr all, rd all, wr all, rd all
- FOR R IN 0 TO 1 LOOP
- -- Write the whole memory range
- FOR I IN 0 TO g_nof_masters-1 LOOP
- v_base := g_base_arr(I);
- v_span := 2**g_width_arr(I);
- FOR J IN 0 TO v_span-1 LOOP
- proc_mem_mm_bus_wr(v_base + J, R+J, mm_clk, stimuli_mosi);
- END LOOP;
- END LOOP;
-
- -- Read back the whole range in reverse order and check if data is as expected
- FOR I IN g_nof_masters-1 DOWNTO 0 LOOP
- v_base := g_base_arr(I);
- v_span := 2**g_width_arr(I);
- FOR J IN v_span-1 DOWNTO 0 LOOP
- proc_mem_mm_bus_rd(v_base + J, mm_clk, stimuli_mosi);
- proc_common_wait_some_cycles(mm_clk, c_read_latency);
- v_data := TO_UINT(stimuli_miso.rddata(31 DOWNTO 0));
- IF v_data /= R+J THEN
- REPORT "Error! Readvalue is not as expected" SEVERITY ERROR;
- END IF;
- END LOOP;
- END LOOP;
- END LOOP;
-
- proc_common_wait_some_cycles(mm_clk, 10);
- tb_end <= '1';
- WAIT;
- END PROCESS;
-
- -- Model multiple masters using stimuli from a single master
- u_masters : ENTITY work.common_mem_bus
- GENERIC MAP (
- g_nof_slaves => g_nof_masters,
- g_base_arr => g_base_arr,
- g_width_arr => g_width_arr,
- g_rd_latency_arr => c_ram_rd_latency_arr,
- g_pipeline_mosi => g_pipeline_bus_mosi,
- g_pipeline_miso => g_pipeline_bus_miso
- )
- PORT MAP (
- mm_clk => mm_clk,
- master_mosi => stimuli_mosi,
- master_miso => stimuli_miso,
- slave_mosi_arr => master_mosi_arr,
- slave_miso_arr => master_miso_arr
- );
-
- -- DUT = device under test
- u_dut: ENTITY work.common_mem_master_mux
- GENERIC MAP (
- g_nof_masters => g_nof_masters,
- g_rd_latency_min => c_read_latency
- )
- PORT MAP (
- mm_clk => mm_clk,
- master_mosi_arr => master_mosi_arr,
- master_miso_arr => master_miso_arr,
- mux_mosi => mux_mosi,
- mux_miso => mux_miso
- );
-
- -- Model master access to MM bus with multiple slaves using a single RAM
- u_ram : ENTITY work.common_ram_r_w
- GENERIC MAP (
- g_ram => c_test_ram,
- g_init_file => "UNUSED"
- )
- PORT MAP (
- rst => mm_rst,
- clk => mm_clk,
- wr_en => mux_mosi.wr,
- wr_adr => mux_mosi.address(c_addr_w-1 DOWNTO 0),
- wr_dat => mux_mosi.wrdata(c_data_w-1 DOWNTO 0),
- rd_en => mux_mosi.rd,
- rd_adr => mux_mosi.address(c_addr_w-1 DOWNTO 0),
- rd_dat => mux_miso.rddata(c_data_w-1 DOWNTO 0),
- rd_val => mux_miso.rdval
- );
-
-
-END tb;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_mem_bus.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_mem_bus.vhd
deleted file mode 100644
index 2a98bc21908d137d16e330aee1f6889ab95bd884..0000000000000000000000000000000000000000
--- a/libraries/base/common/tb/vhdl/tb_tb_common_mem_bus.vhd
+++ /dev/null
@@ -1,54 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright 2020
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- Licensed under the Apache License, Version 2.0 (the "License");
--- you may not use this file except in compliance with the License.
--- You may obtain a copy of the License at
---
--- http://www.apache.org/licenses/LICENSE-2.0
---
--- Unless required by applicable law or agreed to in writing, software
--- distributed under the License is distributed on an "AS IS" BASIS,
--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--- See the License for the specific language governing permissions and
--- limitations under the License.
---
--------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------
---
--- Author: E. Kooistra
--- Purpose: Multi test bench for common_mem_bus.vhd
---
--------------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE work.common_pkg.ALL;
-
-ENTITY tb_tb_common_mem_bus IS
-END tb_tb_common_mem_bus;
-
-ARCHITECTURE tb OF tb_tb_common_mem_bus IS
- SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-BEGIN
- -- Usage:
- -- > as 4
- -- > run -all
-
- -- g_nof_slaves : POSITIVE := 2; -- Number of slave memory interfaces on the MM bus array.
- -- g_base_offset : NATURAL := 0; -- Address of first slave on the MM bus
- -- g_width_w : POSITIVE := 4; -- Address width of each slave memory in the MM bus array.
- -- g_rd_latency : NATURAL := 1; -- Read latency of the slaves slave
- -- g_pipeline_mosi : BOOLEAN := FALSE;
- -- g_pipeline_miso : BOOLEAN := FALSE
-
- u_rd_latency_1 : ENTITY work.tb_common_mem_bus GENERIC MAP (16, 0, 3, 1, FALSE, FALSE);
- u_base_offset : ENTITY work.tb_common_mem_bus GENERIC MAP (16, 3*2**4, 4, 1, FALSE, FALSE);
- u_pipeline_mosi : ENTITY work.tb_common_mem_bus GENERIC MAP ( 3, 0, 4, 1, TRUE, FALSE);
- u_pipeline_mosi_miso : ENTITY work.tb_common_mem_bus GENERIC MAP ( 3, 0, 4, 1, TRUE, TRUE);
-
-END tb;
diff --git a/libraries/base/mm/hdllib.cfg b/libraries/base/mm/hdllib.cfg
index b3180241c7a1cc59125c22d754d1cd75fd96bd30..cd1b224af35e9aa0140662040d39fa5723b74aea 100644
--- a/libraries/base/mm/hdllib.cfg
+++ b/libraries/base/mm/hdllib.cfg
@@ -8,21 +8,39 @@ synth_files =
src/vhdl/mm_fields.vhd
tb/vhdl/mm_file_pkg.vhd
tb/vhdl/mm_file_unb_pkg.vhd
+
src/verilog/timeout.v
src/verilog/wbs_arbiter.v
src/vhdl/mm_arbiter.vhd
+
+ src/vhdl/mm_pipeline.vhd
+ src/vhdl/mm_latency_adapter.vhd
+ src/vhdl/mm_slave_enable.vhd
+ src/vhdl/mm_bus_comb.vhd
+ src/vhdl/mm_bus_pipe.vhd
+ src/vhdl/mm_bus.vhd
+ src/vhdl/mm_master_mux.vhd
+ src/vhdl/mm_slave_mux.vhd
test_bench_files =
tb/vhdl/mm_file.vhd
tb/vhdl/tb_mm_file.vhd
+
+ tb/vhdl/mm_waitrequest_model.vhd
+ tb/vhdl/tb_mm_bus.vhd
+ tb/vhdl/tb_mm_master_mux.vhd
+
tb/vhdl/tb_tb_mm_file.vhd
+ tb/vhdl/tb_tb_mm_bus.vhd
+ tb/vhdl/tb_tb_mm_master_mux.vhd
regression_test_vhdl =
tb/vhdl/tb_tb_mm_file.vhd
+ tb/vhdl/tb_tb_mm_bus.vhd
+ tb/vhdl/tb_tb_mm_master_mux.vhd
[modelsim_project_file]
[quartus_project_file]
-
diff --git a/libraries/base/mm/src/vhdl/mm_bus.vhd b/libraries/base/mm/src/vhdl/mm_bus.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0b447521408adcd9d45d60cdb8cd48983c5acfa1
--- /dev/null
+++ b/libraries/base/mm/src/vhdl/mm_bus.vhd
@@ -0,0 +1,183 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Connect a single MM master interface to a list of MM slave
+-- interfaces using mm_bus_pipe.
+-- Description:
+-- In addition to mm_bus_pipe this mm_bus takes care of:
+-- - not connected slaves
+-- - slaves that do not need flow control
+--
+-- FOR g_nof_slaves:
+-- g_slave_enable_arr
+-- g_waitrequest_arr
+-- g_rd_latency_arr
+-- | |
+-- | |
+-- g_base_arr | |
+-- g_width_arr | |
+-- g_pipeline_mosi | |
+-- g_pipeline_miso_rdval | |
+-- g_pipeline_miso_wait | |
+-- | | |
+-- __v___v_ ____v___
+-- master_miso <-------| mm_bus |<--| mm |<-- slave_miso_arr
+-- master_mosi ------->| pipe |-->| slave |--> slave_mosi_arr
+-- |________| | enable |
+-- |________|
+-- The mm_bus_comb takes care of:
+-- - MM bus multiplexer between master and slaves
+-- - MM slave address allocation on the MM bus
+-- The mm_bus_pipe takes care of:
+-- - Pipelining the MM bus, the mm_bus_comb and mm_slave_enable are
+-- combinatorial.
+--
+-- Usage:
+-- The ascii drawing shows how this mm_bus can be used in combination
+-- with other MM bus components to create an memory mapped bus:
+--
+-- . mm_bus : connects a master to multiple independent slaves
+-- . mm_slave_mux : connects an array of slave to a single slave port
+-- . mm_master_mux : connects mulitple masters to a single slave
+--
+-- mm_slave_mux
+-- mm_bus |---S
+-- |-------|---S
+-- |---S |---S
+-- M ---|
+-- |---S
+-- |---S
+-- |-------|
+-- |---S |---S
+-- |
+-- M -----------|
+-- mm_master_mux
+--
+-- The mm_slave_mux and mm_master_mux should typically be combinatorial,
+-- because all MM bus pipelining is concentrated in mm_bus_pipe.
+--
+-- * The mm_slave_mux is useful to present an array of equal slave MM
+-- ports via a single port on the MM bus. Otherwise the mm_bus could
+-- instead directly present each slave MM array port.
+-- The mm_slave_mux introduces hierarchy in the MM bus structure. This
+-- can help to influcence the timing closure. Using only mm_bus or
+-- the a combination of mm_bus and mm_slave_mux can help to steer
+-- where pipelining is inserted in the MM bus.
+-- * The MM bus based on mm_bus could be automatically generated by ARGS
+-- based on a set of MM slave ports described in YAML configuration
+-- files.
+--
+-- Limitations --> see mm_bus_comb
+--
+-- Todo (only if necessary):
+-- * The mm_bus assumes that the MM slave will eventually acknowledge an
+-- mosi.wr or rd access by pulling miso.waitrequest low. If the MM slave
+-- malfunctions then the MM bus access will stall. Therefore a MM slave
+-- port that uses mosi flow control should also support a waitrequest
+-- timeout mechanism. Such a waitrequest timeout mechanism could be made
+-- part of mm_slave_enable.
+-- * The master can then be informed about a failing mosi access using
+-- the miso.response field of the Avalon bus. A failing mosi access can
+-- be due to a not connected slave, an out-of-range address, a slave that
+-- times out on flow control.
+--
+-------------------------------------------------------------------------------
+
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+ENTITY mm_bus IS
+ GENERIC (
+ g_nof_slaves : POSITIVE; -- Number of MM slave interfaces on the bus
+ g_base_arr : t_nat_natural_arr; -- Address base per slave
+ g_width_arr : t_nat_natural_arr; -- Address width per slave
+ g_rd_latency_arr : t_nat_natural_arr; -- Read latency per slave
+ g_slave_enable_arr : t_nat_boolean_arr; -- Use FALSE for not connected slaves, else TRUE
+ g_waitrequest_arr : t_nat_boolean_arr; -- Enable waitrequest flow control per slave, else fixed '0'
+ g_pipeline_mosi : BOOLEAN := FALSE; -- Pipeline MM access (wr, rd)
+ g_pipeline_miso_rdval : BOOLEAN := FALSE; -- Pipeline MM read (rdval)
+ g_pipeline_miso_wait : BOOLEAN := FALSE -- Pipeline MM access flow control (waitrequest)
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC := '0';
+ mm_clk : IN STD_LOGIC := '0';
+ master_mosi : IN t_mem_mosi;
+ master_miso : OUT t_mem_miso;
+ slave_mosi_arr : OUT t_mem_mosi_arr(0 TO g_nof_slaves-1);
+ slave_miso_arr : IN t_mem_miso_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_miso_rst)
+ );
+END mm_bus;
+
+ARCHITECTURE str OF mm_bus IS
+
+ SIGNAL bus_mosi_arr : t_mem_mosi_arr(0 TO g_nof_slaves-1);
+ SIGNAL bus_miso_arr : t_mem_miso_arr(0 TO g_nof_slaves-1);
+
+BEGIN
+
+ -- MM bus
+ u_mm_bus_pipe : ENTITY work.mm_bus_pipe
+ GENERIC MAP (
+ g_nof_slaves => g_nof_slaves,
+ g_base_arr => g_base_arr,
+ g_width_arr => g_width_arr,
+ g_rd_latency_arr => g_rd_latency_arr,
+ g_waitrequest_arr => g_waitrequest_arr,
+ g_pipeline_mosi => g_pipeline_mosi,
+ g_pipeline_miso_rdval => g_pipeline_miso_rdval,
+ g_pipeline_miso_wait => g_pipeline_miso_wait
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ master_mosi => master_mosi,
+ master_miso => master_miso,
+ slave_mosi_arr => bus_mosi_arr,
+ slave_miso_arr => bus_miso_arr
+ );
+
+ -- The MM bus interface with the MM slaves
+ gen_slave_ports : FOR I IN 0 TO g_nof_slaves-1 GENERATE
+ -- Rewire not connected slaves and slave that do not need mosi flow control via miso.waitrequest
+ u_slave_enable : ENTITY work.mm_slave_enable
+ GENERIC MAP (
+ g_enable => g_slave_enable_arr(I),
+ g_waitrequest => g_waitrequest_arr(I),
+ g_rd_latency => g_rd_latency_arr(I)
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ -- MM input RL = 1
+ in_mosi => bus_mosi_arr(I),
+ in_miso => bus_miso_arr(I),
+ -- MM output RL = 0
+ out_mosi => slave_mosi_arr(I),
+ out_miso => slave_miso_arr(I)
+ );
+ END GENERATE;
+
+END str;
diff --git a/libraries/base/common/src/vhdl/common_mem_bus.vhd b/libraries/base/mm/src/vhdl/mm_bus_comb.vhd
similarity index 53%
rename from libraries/base/common/src/vhdl/common_mem_bus.vhd
rename to libraries/base/mm/src/vhdl/mm_bus_comb.vhd
index 32078476336ad8c684d3ec53fafc0d2231994b51..4fda2cd307a9c12189e85bbfbf5522b4fe04a364 100644
--- a/libraries/base/common/src/vhdl/common_mem_bus.vhd
+++ b/libraries/base/mm/src/vhdl/mm_bus_comb.vhd
@@ -1,233 +1,216 @@
--------------------------------------------------------------------------------
---
--- Copyright 2020
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- Licensed under the Apache License, Version 2.0 (the "License");
--- you may not use this file except in compliance with the License.
--- You may obtain a copy of the License at
---
--- http://www.apache.org/licenses/LICENSE-2.0
---
--- Unless required by applicable law or agreed to in writing, software
--- distributed under the License is distributed on an "AS IS" BASIS,
--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--- See the License for the specific language governing permissions and
--- limitations under the License.
---
--------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------
---
--- Author: E. Kooistra
--- Purpose: Connect a single MM master interface to a list of MM slave
--- interfaces
--- Description:
--- * MM bus
--- The common_mem_bus creates a memory mapped (MM) bus that connects read
--- and write accesses from the master interface to the addressed slave
--- interface. There is one master that controls the bus and there are
--- g_nof_slaves on the bus. Per slave the start address and address span
--- have to be specified via g_base_arr and g_width_arr.
---
--- * Slave allocation
--- The slaves have to be located on the bus such that the MSbits of the
--- global address can be used to select the slave and the LSbits of the
--- global address can directly be used to select the address within the
--- slave. Therefore:
--- . The width of a slave is the power of 2 that fits the address range of
--- the slave.
--- . The span of a slave is 2**width.
--- . The base address of a slave has to be a power of 2 multiple of the
--- slave span.
---
--- * The mm_clk is only used when there is a slave with read latency > 0 or
--- when the MM bus uses pipelining.
---
--- * Read latency
--- For read accesses a slave will typically have a read latency > 0, which
--- means that when the rd and address are active, then it takes read
--- latency number of clock cycles until the rddata becomes available. The
--- read latency can be specified per slave via g_rd_latency_arr.
--- The index_pipeline is used to support that a new wr access or rd access
--- can already start, while a current rd access still has to finish with
--- a rdval. Without the index_pipeline the master would have to wait with
--- a new rd or wr access to another slave until the read response from the
--- current slave has finished.
--- ________
--- | pipe |
--- master_mosi.address[h:w] = index --+-->| line |--\
--- | |______| |
--- | |
--- v |
--- master_mosi --> slave_mosi_arr.wr[ ]----------------> slave_mosi_arr
--- rd |
--- v
--- master_miso <--------------------slave_miso_arr[ ]<-- slave_miso_arr
---
--- A limitation is that if one slave has a read latency of 2 and another
--- slave has a read latency of 1 then it is not possible to access them
--- without a gap of 1 mm_clk cycle, because the rdval will then be active
--- simultaneously from both slaves. Therefore the master can only use
--- random read access between slaves if all slaves have the same read
--- latency. For slaves that have larger read latency the master must
--- insert an gap, before it can read a slave that has less read latency.
---
--- * Pipelining
--- Default the common_mm_bus is combinatorial, so there is no pipelining
--- between the master interface and the slave interfaces. If possible do not
--- use pipelining of mosi and miso to avoid increasing the read latency and
--- achieve timing closure by lower clock rate for the MM bus. Pipelining the
--- MM bus can be necessary to achieve timing closure:
--- . g_pipeline_mosi
--- Pipelining mosi write accesses introduces an extra latency from master
--- to slave, which is typically not a problem. Pipelining mosi read
--- accesses increases the read latency between accessing the slave and
--- getting the rddata. Using a different pipelining for the wr and the rd
--- pulse would yield a different pipelining of the address for write and
--- for read, which is akward. Therefore assume that both mosi write and
--- mosi read have the same pipelining.
--- . g_pipeline_miso
--- Pipelining the miso read data increases the read latency.
--- The total write latency from master to slave is c_mosi_latency.
--- The total read latency from master via slave back to master is
--- c_mosi_latency + g_rd_latency_arr of the selected slave + c_miso_latency.
---
--- Remarks:
--- . The common_mem_bus resembles common_mem_mux, but the difference is that
--- with common_mem_mux all slaves have the same address range and are
--- spaced without address gaps. It is possible to use common_mem_mux in
--- series with common_mem_bus to provide hierarchy by reprensenting an array
--- of slave ports via a single slave port on the MM bus.
--- . In simulation selecting an unused element address will cause a simulation
--- failure. Therefore the element index is only accepted when it is in the
--- 0 TO g_nof_slaves-1 range.
---
--------------------------------------------------------------------------------
-
-
-LIBRARY IEEE, common_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-
-ENTITY common_mem_bus IS
- GENERIC (
- g_nof_slaves : POSITIVE; -- Number of MM slave interfaces on the bus
- g_base_arr : t_nat_natural_arr; -- Address base per slave
- g_width_arr : t_nat_natural_arr; -- Address width per slave
- g_rd_latency_arr : t_nat_natural_arr; -- Read latency per slave
- g_pipeline_mosi : BOOLEAN := FALSE;
- g_pipeline_miso : BOOLEAN := FALSE
- );
- PORT (
- mm_clk : IN STD_LOGIC := '0';
- master_mosi : IN t_mem_mosi;
- master_miso : OUT t_mem_miso;
- slave_mosi_arr : OUT t_mem_mosi_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_mosi_rst);
- slave_miso_arr : IN t_mem_miso_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_miso_rst)
- );
-END common_mem_bus;
-
-ARCHITECTURE rtl OF common_mem_bus IS
-
- -- Determine the address range of all slaves on the MM bus.
- FUNCTION func_derive_mm_bus_addr_w(g_base_arr, g_width_arr : t_nat_natural_arr) RETURN NATURAL IS
- VARIABLE v_base : NATURAL := 0;
- VARIABLE v_width : NATURAL;
- VARIABLE v_mm_bus_addr_max : NATURAL;
- BEGIN
- FOR I IN g_base_arr'RANGE LOOP
- IF g_base_arr(I) > v_base THEN
- v_base := g_base_arr(I);
- v_width := g_width_arr(I);
- END IF;
- END LOOP;
- -- Largest base address + the width of the slave at this address - 1. The
- -- -1 is because the addresses count from 0 to N-1.
- v_mm_bus_addr_max := v_base + 2**v_width - 1;
- -- Return number of bits to represent the largest address that will be used
- -- on the MM bus
- RETURN ceil_log2(v_mm_bus_addr_max);
- END;
-
- CONSTANT c_mm_bus_addr_w : NATURAL := func_derive_mm_bus_addr_w(g_base_arr, g_width_arr);
- CONSTANT c_mosi_latency : NATURAL := sel_a_b(g_pipeline_mosi, 1, 0);
- CONSTANT c_miso_latency : NATURAL := sel_a_b(g_pipeline_miso, 1, 0);
- CONSTANT c_index_latency_max : NATURAL := c_mosi_latency + largest(g_rd_latency_arr);
-
- SIGNAL index_pipeline : t_nat_natural_arr(0 TO c_index_latency_max) := (OTHERS=>0);
- SIGNAL slave_mosi_arr_comb : t_mem_mosi_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_mosi_rst);
- SIGNAL master_miso_comb : t_mem_miso := c_mem_miso_rst;
-
-BEGIN
-
- gen_single : IF g_nof_slaves=1 GENERATE
- slave_mosi_arr(0) <= master_mosi;
- master_miso <= slave_miso_arr(0);
- END GENERATE;
-
- gen_multiple : IF g_nof_slaves>1 GENERATE
-
- -- Detect which slave in the array is addressed
- p_index : PROCESS(master_mosi)
- VARIABLE v_base : NATURAL;
- BEGIN
- index_pipeline(0) <= g_nof_slaves; -- default index of none existing slave
- FOR I IN 0 TO g_nof_slaves-1 LOOP
- v_base := TO_UINT(master_mosi.address(c_mm_bus_addr_w-1 DOWNTO g_width_arr(I)));
- ASSERT g_base_arr(I) MOD 2**g_width_arr(I) = 0 REPORT "Slave base address must be a multiple of the slave width." SEVERITY FAILURE;
- IF v_base = g_base_arr(I) / 2**g_width_arr(I) THEN
- index_pipeline(0) <= I; -- return index of addressed slave
- EXIT;
- END IF;
- END LOOP;
- END PROCESS;
-
- index_pipeline(1 TO c_index_latency_max) <= index_pipeline(0 TO c_index_latency_max-1) WHEN rising_edge(mm_clk);
-
- -- Master access, can be write or read
- p_mosi : PROCESS(master_mosi, index_pipeline)
- BEGIN
- slave_mosi_arr_comb <= (OTHERS=>master_mosi); -- default assign to all, to avoid latches
- FOR I IN 0 TO g_nof_slaves-1 LOOP
- slave_mosi_arr_comb(I).rd <= '0';
- slave_mosi_arr_comb(I).wr <= '0';
- IF I = index_pipeline(0) THEN -- check index for read or write access
- slave_mosi_arr_comb(I).rd <= master_mosi.rd;
- slave_mosi_arr_comb(I).wr <= master_mosi.wr;
- END IF;
- END LOOP;
- END PROCESS;
-
- no_pipeline_mosi : IF g_pipeline_mosi = FALSE GENERATE
- slave_mosi_arr <= slave_mosi_arr_comb;
- END GENERATE;
- gen_pipeline_mosi : IF g_pipeline_mosi = TRUE GENERATE
- slave_mosi_arr <= slave_mosi_arr_comb WHEN rising_edge(mm_clk);
- END GENERATE;
-
- -- Slave response to read access after read latency mm_clk cycles
- p_miso : PROCESS(slave_miso_arr, index_pipeline)
- VARIABLE v_rd_latency : NATURAL;
- BEGIN
- master_miso_comb <= c_mem_miso_rst; -- default clear, to avoid latches
- FOR I IN 0 TO g_nof_slaves-1 LOOP
- v_rd_latency := c_mosi_latency + g_rd_latency_arr(I);
- IF I = index_pipeline(v_rd_latency) THEN -- check index for read response
- master_miso_comb <= slave_miso_arr(I);
- END IF;
- END LOOP;
- END PROCESS;
-
- no_pipeline_miso : IF g_pipeline_miso = FALSE GENERATE
- master_miso <= master_miso_comb;
- END GENERATE;
- gen_pipeline_miso : IF g_pipeline_miso = TRUE GENERATE
- master_miso <= master_miso_comb WHEN rising_edge(mm_clk);
- END GENERATE;
-
- END GENERATE;
-
-END rtl;
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Connect a single MM master interface to a list of MM slave
+-- interfaces using a combinatorial muliplexer as bus.
+-- Description:
+-- * MM bus
+-- The mm_bus_comb creates a memory mapped (MM) bus that connects read
+-- and write accesses from the master interface to the addressed slave
+-- interface. There is one master that controls the bus and there are
+-- g_nof_slaves on the bus. Per slave the start address and address span
+-- have to be specified via g_base_arr and g_width_arr.
+--
+-- * Slave allocation
+-- The slaves have to be located on the bus such that the MSbits of the
+-- global address can be used to select the slave and the LSbits of the
+-- global address can directly be used to select the address within the
+-- slave. Therefore:
+-- . The width of a slave is the power of 2 that fits the address range of
+-- the slave.
+-- . The span of a slave is 2**width.
+-- . The base address of a slave has to be a power of 2 multiple of the
+-- slave span.
+--
+-- * The mm_clk is only used when there is a slave with read latency > 0, to
+-- pipeline the slave_index_arr for the master_miso.rddata/rdval.
+-- Typically a master will wait for the last rdval, before accessing
+-- another slave port, so then it is not benecessary to pipeline the
+-- slave_index_arr. However registering the slave_index_arr eases timing
+-- closure on the miso part and will allow reading from different slave
+-- ports without waiting, provided that both slaves have the same read
+-- latency.
+--
+-- * Read latency
+-- For read accesses a slave will typically have a read latency > 0, which
+-- means that when the rd and address are active, then it takes read
+-- latency number of clock cycles until the rddata becomes available. The
+-- read latency can be specified per slave via g_rd_latency_arr.
+-- The slave_index_arr is used to support that a new wr access or rd access
+-- can already start, while a current rd access still has to finish with
+-- a rdval. Without the slave_index_arr the master would have to wait with
+-- a new rd or wr access to another slave until the read response from the
+-- current slave has finished.
+-- ________
+-- | delay|
+-- master_mosi.address[h:w] = index --+-->| line |--\
+-- | |______| |
+-- | |
+-- v |
+-- master_mosi --> slave_mosi_arr.wr[ ]----------------> slave_mosi_arr
+-- rd |
+-- v
+-- master_miso <--------------------slave_miso_arr[ ]<-- slave_miso_arr
+--
+--
+-- * No pipelining
+-- The mm_bus_comb is combinatorial, so there is no pipelining between
+-- the master interface and the slave interfaces. Use mm_bus_pipe to add
+-- pipelining.
+--
+-- Usage:
+-- See mm_bus.vhd.
+--
+-- Limitations:
+-- * A limitation is that if one slave has a read latency of 2 and another
+-- slave has a read latency of 1 then it is not possible to access them
+-- without a gap of 1 mm_clk cycle, because the rdval will then be active
+-- simultaneously from both slaves. Therefore the master can only use
+-- random read access between slaves if all slaves have the same read
+-- latency. For slaves that have larger read latency the master must
+-- insert an gap, before it can read a slave that has less read latency.
+-- An alternative workaround would be to use the same read latency for all
+-- slaves on the bus, by pipelining the miso.rd, rddata for MM slaves that
+-- have a smaller read latency.
+--
+-- Remarks:
+-- . The mm_bus_comb resembles common_mem_mux, but the difference is that
+-- with common_mem_mux all slaves have the same address range and are
+-- spaced without address gaps. It is possible to use common_mem_mux in
+-- series with mm_bus_comb to provide hierarchy by reprensenting an array
+-- of slave ports via a single slave port on the MM bus.
+--
+-------------------------------------------------------------------------------
+
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+ENTITY mm_bus_comb IS
+ GENERIC (
+ g_nof_slaves : POSITIVE; -- Number of MM slave interfaces on the bus
+ g_base_arr : t_nat_natural_arr; -- Address base per slave
+ g_width_arr : t_nat_natural_arr; -- Address width per slave
+ g_rd_latency_arr : t_nat_natural_arr -- Read latency per slave
+ );
+ PORT (
+ mm_clk : IN STD_LOGIC := '0';
+ master_mosi : IN t_mem_mosi;
+ master_miso : OUT t_mem_miso;
+ slave_mosi_arr : OUT t_mem_mosi_arr(0 TO g_nof_slaves-1);
+ slave_miso_arr : IN t_mem_miso_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_miso_rst)
+ );
+END mm_bus_comb;
+
+ARCHITECTURE rtl OF mm_bus_comb IS
+
+ -- Determine the address range of all slaves on the MM bus.
+ FUNCTION func_derive_mm_bus_addr_w(g_base_arr, g_width_arr : t_nat_natural_arr) RETURN NATURAL IS
+ VARIABLE v_base : NATURAL := 0;
+ VARIABLE v_width : NATURAL;
+ VARIABLE v_mm_bus_addr_max : NATURAL;
+ BEGIN
+ FOR I IN g_base_arr'RANGE LOOP
+ IF g_base_arr(I) > v_base THEN
+ v_base := g_base_arr(I);
+ v_width := g_width_arr(I);
+ END IF;
+ END LOOP;
+ -- Largest base address + the width of the slave at this address - 1. The
+ -- -1 is because the addresses count from 0 to N-1.
+ v_mm_bus_addr_max := v_base + 2**v_width - 1;
+ -- Return number of bits to represent the largest address that will be used
+ -- on the MM bus
+ RETURN ceil_log2(v_mm_bus_addr_max);
+ END;
+
+ CONSTANT c_mm_bus_addr_w : NATURAL := func_derive_mm_bus_addr_w(g_base_arr, g_width_arr);
+ CONSTANT c_rd_latency_max : NATURAL := largest(g_rd_latency_arr);
+
+ SIGNAL slave_index_arr : t_nat_natural_arr(0 TO c_rd_latency_max) := (OTHERS=>0);
+
+BEGIN
+
+ gen_single : IF g_nof_slaves=1 GENERATE
+ slave_mosi_arr(0) <= master_mosi;
+ master_miso <= slave_miso_arr(0);
+ END GENERATE;
+
+ gen_multiple : IF g_nof_slaves>1 GENERATE
+ -- Detect which slave in the array is addressed
+ p_index : PROCESS(master_mosi)
+ VARIABLE v_base : NATURAL;
+ BEGIN
+ slave_index_arr(0) <= g_nof_slaves; -- default index of none existing slave
+ FOR I IN 0 TO g_nof_slaves-1 LOOP
+ v_base := TO_UINT(master_mosi.address(c_mm_bus_addr_w-1 DOWNTO g_width_arr(I)));
+ ASSERT g_base_arr(I) MOD 2**g_width_arr(I) = 0 REPORT "Slave base address must be a multiple of the slave width." SEVERITY FAILURE;
+ IF v_base = g_base_arr(I) / 2**g_width_arr(I) THEN
+ slave_index_arr(0) <= I; -- return index of addressed slave
+ EXIT; -- Found addressed slave, no need to loop further. EXIT is
+ -- not realy needed, because there can only be one
+ -- addressed slave so loop further will not change the index.
+ END IF;
+ END LOOP;
+ END PROCESS;
+
+ slave_index_arr(1 TO c_rd_latency_max) <= slave_index_arr(0 TO c_rd_latency_max-1) WHEN rising_edge(mm_clk);
+
+ -- Master access, can be write or read
+ p_slave_mosi_arr : PROCESS(master_mosi, slave_index_arr)
+ BEGIN
+ slave_mosi_arr <= (OTHERS=>master_mosi); -- default assign to all, to avoid latches
+ FOR I IN 0 TO g_nof_slaves-1 LOOP
+ slave_mosi_arr(I).rd <= '0';
+ slave_mosi_arr(I).wr <= '0';
+ IF I = slave_index_arr(0) THEN -- check index for read or write access
+ slave_mosi_arr(I).rd <= master_mosi.rd;
+ slave_mosi_arr(I).wr <= master_mosi.wr;
+ END IF;
+ END LOOP;
+ END PROCESS;
+
+
+ -- Slave response to read access after read latency mm_clk cycles
+ p_master_miso : PROCESS(slave_miso_arr, slave_index_arr)
+ VARIABLE v_rd_latency : NATURAL;
+ BEGIN
+ master_miso <= c_mem_miso_rst; -- default clear, to avoid latches
+ FOR I IN 0 TO g_nof_slaves-1 LOOP
+ v_rd_latency := g_rd_latency_arr(I);
+ IF I = slave_index_arr(v_rd_latency) THEN -- check index for read response
+ master_miso <= slave_miso_arr(I);
+ END IF;
+ END LOOP;
+ FOR I IN 0 TO g_nof_slaves-1 LOOP
+ IF I = slave_index_arr(0) THEN -- check index for waitrequest
+ master_miso.waitrequest <= slave_miso_arr(I).waitrequest;
+ END IF;
+ END LOOP;
+ END PROCESS;
+
+ END GENERATE;
+
+END rtl;
diff --git a/libraries/base/mm/src/vhdl/mm_bus_pipe.vhd b/libraries/base/mm/src/vhdl/mm_bus_pipe.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2b8f8ecba4dad4d87fdc9dbb6607df467bcd6075
--- /dev/null
+++ b/libraries/base/mm/src/vhdl/mm_bus_pipe.vhd
@@ -0,0 +1,223 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Provide pipelining to the combinatorial mm_bus_comb
+-- Description:
+-- The mm_bus_comb is combinatorial, so there is no pipelining between
+-- the master interface and the slave interfaces. If possible do not
+-- use pipelining of mosi and miso to avoid extra logic and to avoid
+-- increasing the read latency. Instead first try achieve timing closure
+-- by lower clock rate for the MM bus. Pipelining the MM bus can be
+-- necessary to achieve timing closure. Thanks to mm_bus_comb the
+-- pipelining is clearly separated from the MM bus multiplexer. The
+-- pipelining is placed at the output of the bus, so at the slave side
+-- for mosi and at the master side for miso:
+--
+-- FOR g_nof_slaves:
+-- g_pipeline_miso_rdval g_pipeline_mosi
+-- g_pipeline_miso_wait | g_pipeline_miso_wait
+-- | | |
+-- v ________ ____v___ ___v___
+-- <-- p_miso_pipe <--| mm_bus |<--|mm |<--|mm |<--------
+-- ------------------>| comb |-->|pipeline|-->|latency|-------->
+-- . . |________| . |________| |adapter| . .
+-- master_miso . . . |_______| . slave_miso_arr
+-- master_mosi . . . . slave_mosi_arr
+-- m_miso bus_miso_arr pipe_miso_arr adapt_miso_arr
+-- m_mosi bus_mosi_arr pipe_mosi_arr adapt_mosi_arr
+--
+-- The MM bus pipelining is defined by:
+--
+-- * g_pipeline_mosi
+-- Pipelining mosi write accesses introduces an extra latency from master
+-- to slave, which is typically not a problem. Pipelining mosi read
+-- accesses increases the read latency between accessing the slave and
+-- getting the rddata. Using a different pipelining for the wr and the rd
+-- pulse would yield a different pipelining of the address for write and
+-- for read, which is akward. Therefore both mosi write and mosi read
+-- use the same g_pipeline_mosi pipelining.
+--
+-- * g_pipeline_miso_rdval
+-- Pipelining the miso read data increases the read latency.
+--
+-- * g_pipeline_miso_wait
+-- Pipelining the miso waitrequest increases the write and read latency
+-- for slaves that need MM flow control. Only applies to slave that
+-- have g_waitrequest_arr is TRUE.
+--
+-- The pipelining generics are defined as BOOLEAN (rather than NATURAL),
+-- because the pipelining only needs to be 0 or 1.
+--
+-- The total write latency from master to slave is 1 when either
+-- g_pipeline_mosi or g_pipeline_miso_wait.
+-- The total read latency from master via slave back to master is
+-- write latency + g_rd_latency_arr of the selected slave + 1 or 0
+-- dependend on g_pipeline_miso_rdval.
+--
+-- Usage:
+-- See mm_bus.vhd
+--
+-- Remark:
+-- * It is not allowed to simultaneously use g_pipeline_miso_wait = TRUE
+-- and g_pipeline_mosi = TRUE, because this leads to a combinatorial loop
+-- of the miso.waitrequest that is used at the output of the mm_pipeline
+-- and at the input of the mm_latency adapter:
+-- - at the mm_pipeline output the waitrequest gates the mosi.wr and rd
+-- - at the mm_latency_adapter input in common_rl_decrease the wr or
+-- rd strobe is used to set the waitrequest.
+-- This combinatorial loop seems unavoidable when the interface between
+-- mm_pipeline and mm_latency_adpater is at RL = 0. A solution could be
+-- to increase the RL at the output of the mm_pipeline to RL = 1 by
+-- registering the waitrequest from the mm_latency_adapter. The total
+-- RL for the input of the MM latency adapter then becomes RL = 2, so
+-- then the mm_latency_adapter needs to adapt from RL = 2 to 0.
+-- Currently the mm_latency_adapter only supports RL 1 to 0. Is possible
+-- to extent this to RL = N to 0, similar as in dp_latency_adapter.
+-- However fortunately it is not necessary to support g_pipeline_mosi =
+-- TRUE when g_pipeline_miso_wait = TRUE, because g_pipeline_miso_wait =
+-- TRUE by itself already also pipeplines the mosi.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+ENTITY mm_bus_pipe IS
+ GENERIC (
+ g_nof_slaves : POSITIVE; -- Number of MM slave interfaces on the bus
+ g_base_arr : t_nat_natural_arr; -- Address base per slave
+ g_width_arr : t_nat_natural_arr; -- Address width per slave
+ g_rd_latency_arr : t_nat_natural_arr; -- Read latency per slave
+ g_waitrequest_arr : t_nat_boolean_arr; -- Enable waitrequest flow control per slave, else fixed '0'
+ g_pipeline_mosi : BOOLEAN := FALSE; -- Pipeline MM access (wr, rd)
+ g_pipeline_miso_rdval : BOOLEAN := FALSE; -- Pipeline MM read (rdval)
+ g_pipeline_miso_wait : BOOLEAN := FALSE -- Pipeline MM access flow control (waitrequest)
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ master_mosi : IN t_mem_mosi;
+ master_miso : OUT t_mem_miso;
+ slave_mosi_arr : OUT t_mem_mosi_arr(0 TO g_nof_slaves-1);
+ slave_miso_arr : IN t_mem_miso_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_miso_rst)
+ );
+END mm_bus_pipe;
+
+ARCHITECTURE str OF mm_bus_pipe IS
+
+ SIGNAL m_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL m_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL m_miso_reg : t_mem_miso := c_mem_miso_rst;
+
+ SIGNAL bus_mosi_arr : t_mem_mosi_arr(0 TO g_nof_slaves-1);
+ SIGNAL bus_miso_arr : t_mem_miso_arr(0 TO g_nof_slaves-1);
+ SIGNAL pipe_mosi_arr : t_mem_mosi_arr(0 TO g_nof_slaves-1);
+ SIGNAL pipe_miso_arr : t_mem_miso_arr(0 TO g_nof_slaves-1);
+ SIGNAL adapt_mosi_arr : t_mem_mosi_arr(0 TO g_nof_slaves-1);
+ SIGNAL adapt_miso_arr : t_mem_miso_arr(0 TO g_nof_slaves-1);
+
+BEGIN
+
+ ASSERT NOT(g_pipeline_miso_wait = TRUE AND g_pipeline_mosi = TRUE)
+ REPORT "Do not use g_pipeline_mosi = TRUE if g_pipeline_miso_wait = TRUE"
+ SEVERITY FAILURE;
+
+ -- Master side
+ m_mosi <= master_mosi;
+
+ m_miso_reg <= m_miso WHEN rising_edge(mm_clk);
+
+ p_miso_pipe : PROCESS(m_miso, m_miso_reg)
+ BEGIN
+ -- Default no miso pipelining
+ master_miso <= m_miso;
+ -- Use pipelining
+ IF g_pipeline_miso_rdval THEN
+ master_miso.rddata <= m_miso_reg.rddata;
+ master_miso.rdval <= m_miso_reg.rdval;
+ END IF;
+ IF g_pipeline_miso_wait THEN
+ master_miso.waitrequest <= m_miso_reg.waitrequest;
+ END IF;
+ END PROCESS;
+
+ -- MM bus
+ u_mm_bus_comb : ENTITY work.mm_bus_comb
+ GENERIC MAP (
+ g_nof_slaves => g_nof_slaves,
+ g_base_arr => g_base_arr,
+ g_width_arr => g_width_arr,
+ g_rd_latency_arr => g_rd_latency_arr
+ )
+ PORT MAP (
+ mm_clk => mm_clk,
+ master_mosi => m_mosi,
+ master_miso => m_miso,
+ slave_mosi_arr => bus_mosi_arr,
+ slave_miso_arr => bus_miso_arr
+ );
+
+ -- Slaves side
+ gen_slave_pipes : FOR I IN 0 TO g_nof_slaves-1 GENERATE
+ u_slave_pipe_mosi : ENTITY work.mm_pipeline
+ GENERIC MAP (
+ g_pipeline => g_pipeline_mosi
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ in_mosi => bus_mosi_arr(I),
+ in_miso => bus_miso_arr(I),
+ out_mosi => pipe_mosi_arr(I),
+ out_miso => pipe_miso_arr(I)
+ );
+
+ gen_wires : IF g_waitrequest_arr(I) = FALSE GENERATE
+ adapt_mosi_arr(I) <= pipe_mosi_arr(I);
+ pipe_miso_arr(I) <= adapt_miso_arr(I);
+ END GENERATE;
+
+ gen_slave_latency_adapter : IF g_waitrequest_arr(I) = TRUE GENERATE
+ u_slave_latency_adapter : ENTITY work.mm_latency_adapter
+ GENERIC MAP (
+ g_adapt => g_pipeline_miso_wait
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ -- MM input RL = 1
+ in_mosi => pipe_mosi_arr(I),
+ in_miso => pipe_miso_arr(I),
+ -- MM output RL = 0
+ out_mosi => adapt_mosi_arr(I),
+ out_miso => adapt_miso_arr(I)
+ );
+ END GENERATE;
+ END GENERATE;
+
+ slave_mosi_arr <= adapt_mosi_arr;
+ adapt_miso_arr <= slave_miso_arr;
+
+END str;
diff --git a/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd b/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..137efa3891e545ffab1c485b056ab4fe79904e57
--- /dev/null
+++ b/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd
@@ -0,0 +1,109 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Adapt miso.waitrequest latency from 1 to 0, to support pipelining
+-- of the waitrequest flow control
+-- Description:
+-- Wraps common_rl_decrease.vhd.
+-- The common_rl_decrease.vhd latency adapter FIFO buffers the in_mosi, to
+-- create time to compensate for the pipeline of the in_mosi.waitrequest.
+-- When the in_mosi.waitrequest goes high, then this FIFO buffer can hold
+-- the in_mosi input that may still arrive, due to that the master at the
+-- input only notices the in_mosi.waitrequest from the output slave one
+-- cycle later due to the pipelining.
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+ENTITY mm_latency_adapter IS
+ GENERIC (
+ g_adapt : BOOLEAN := TRUE -- default when TRUE then decrease sink RL 1 to source RL 0, else then implement wires
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ -- MM input RL = 1
+ in_mosi : IN t_mem_mosi;
+ in_miso : OUT t_mem_miso;
+ -- MM output RL = 0
+ out_mosi : OUT t_mem_mosi;
+ out_miso : IN t_mem_miso
+ );
+END mm_latency_adapter;
+
+
+ARCHITECTURE str OF mm_latency_adapter IS
+
+ -- Sum of all t_mem_mosi fields widths (synthesis will optimize away unused address and data bits)
+ CONSTANT c_data_w : NATURAL := c_mem_address_w + c_mem_data_w + 2; -- 32 + 72 + 1 (wr) + 1 (rd) = 106
+
+ SIGNAL in_waitrequest : STD_LOGIC;
+ SIGNAL in_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
+ SIGNAL in_val : STD_LOGIC;
+ SIGNAL in_ready : STD_LOGIC;
+ SIGNAL out_ready : STD_LOGIC;
+ SIGNAL out_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
+ SIGNAL out_val : STD_LOGIC;
+
+BEGIN
+
+ in_data <= func_slv_concat(in_mosi.address, in_mosi.wrdata, slv(in_mosi.wr), slv(in_mosi.rd));
+ in_val <= in_mosi.wr OR in_mosi.rd;
+
+ p_miso : PROCESS(out_miso, in_waitrequest)
+ BEGIN
+ in_miso <= out_miso;
+ --in_miso.rdval <= out_miso.rdval AND NOT in_waitrequest;
+ in_miso.waitrequest <= in_waitrequest;
+ END PROCESS;
+
+ -- Account for opposite meaning of waitrequest and ready
+ in_waitrequest <= NOT in_ready;
+ out_ready <= NOT out_miso.waitrequest;
+
+ u_rl : ENTITY common_lib.common_rl_decrease
+ GENERIC MAP (
+ g_adapt => g_adapt,
+ g_dat_w => c_data_w
+ )
+ PORT MAP (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- ST sink: RL = 1
+ snk_out_ready => in_ready,
+ snk_in_dat => in_data,
+ snk_in_val => in_val,
+ -- ST source: RL = 0
+ src_in_ready => out_ready,
+ src_out_dat => out_data,
+ src_out_val => out_val
+ );
+
+ out_mosi.address <= func_slv_extract(c_mem_address_w, c_mem_data_w, 1, 1, out_data, 0);
+ out_mosi.wrdata <= func_slv_extract(c_mem_address_w, c_mem_data_w, 1, 1, out_data, 1);
+ out_mosi.wr <= sl(func_slv_extract(c_mem_address_w, c_mem_data_w, 1, 1, out_data, 2));
+ out_mosi.rd <= sl(func_slv_extract(c_mem_address_w, c_mem_data_w, 1, 1, out_data, 3));
+
+END str;
diff --git a/libraries/base/common/src/vhdl/common_mem_master_mux.vhd b/libraries/base/mm/src/vhdl/mm_master_mux.vhd
similarity index 72%
rename from libraries/base/common/src/vhdl/common_mem_master_mux.vhd
rename to libraries/base/mm/src/vhdl/mm_master_mux.vhd
index 82e5fff65c07f3f870fe92a2869ff3ae607e4517..abac065ce676b536b61ea87e0d741c85253c3bd0 100644
--- a/libraries/base/common/src/vhdl/common_mem_master_mux.vhd
+++ b/libraries/base/mm/src/vhdl/mm_master_mux.vhd
@@ -1,132 +1,147 @@
--------------------------------------------------------------------------------
---
--- Copyright 2020
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- Licensed under the Apache License, Version 2.0 (the "License");
--- you may not use this file except in compliance with the License.
--- You may obtain a copy of the License at
---
--- http://www.apache.org/licenses/LICENSE-2.0
---
--- Unless required by applicable law or agreed to in writing, software
--- distributed under the License is distributed on an "AS IS" BASIS,
--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--- See the License for the specific language governing permissions and
--- limitations under the License.
---
--------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------
---
--- Author: E. Kooistra
--- Purpose: Multiplex an array of MM master interfaces to a single MM master
--- interface
--- Description:
--- This common_mem_master_mux is a simple multiplexer that allows multiple
--- masters to access the same MM port. The common_mem_master_mux does not
--- provide arbitration between the masters in the array. Therefore the
--- precondition is that the external application takes care that the MM
--- accesses of the multiple masters in the array do not overlap in time.
---
--- Write accesses from multiple masters occur may without gaps. After a read
--- access from one master the read latency must first be accounted for by
--- the application introducing a gap, before a read access by another master
--- can be multiplexed.
---
--- The common_mem_master_mux operates combinatorially, so it introduces no
--- extra latency. The mm_clk is needed to hold the index of the master that
--- is currently active, to ensure that the read data.is passed on to the
--- master that did the rd access.
--- Remarks:
--- . The mux_miso.waitrequest is not supported.
---
--------------------------------------------------------------------------------
-
-
-LIBRARY IEEE, common_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-
-ENTITY common_mem_master_mux IS
- GENERIC (
- g_nof_masters : POSITIVE; -- Number of MM masters
- g_rd_latency_min : NATURAL -- Minimum read latency
- );
- PORT (
- mm_clk : IN STD_LOGIC;
- master_mosi_arr : IN t_mem_mosi_arr(0 TO g_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
- master_miso_arr : OUT t_mem_miso_arr(0 TO g_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
- mux_mosi : OUT t_mem_mosi;
- mux_miso : IN t_mem_miso
- );
-END common_mem_master_mux;
-
-ARCHITECTURE rtl OF common_mem_master_mux IS
-
- SIGNAL index : NATURAL := 0;
- SIGNAL index_hold : NATURAL := 0;
-
-BEGIN
-
- gen_single : IF g_nof_masters=1 GENERATE
- mux_mosi <= master_mosi_arr(0);
- master_miso_arr(0) <= mux_miso;
- END GENERATE;
-
- gen_multiple : IF g_nof_masters>1 GENERATE
-
- -- Detect which master in the array is active
- -- The pre condition is that the input masters will only start an access
- -- when the mux master is free. For a rd access this means that the
- -- read latency of the rdval has passed. Therefor it is not necessary
- -- that this common_mem_master_mux maintains an index pipeline
- -- from rd until expected rdval. Instead it is sufficient to hold the
- -- index of the active master, until the next master does an access. For
- -- rd access hold the last active index to ensure that rdval will be
- -- directed to the master that orginated the rd access. For wr access
- -- hold last active index instead of reset to '0' to ease observation of
- -- the index value in wave window.
- p_index : PROCESS(master_mosi_arr, index_hold)
- BEGIN
- index <= index_hold; -- default hold index of last active master
- FOR I IN 0 TO g_nof_masters-1 LOOP
- IF master_mosi_arr(I).wr='1' OR master_mosi_arr(I).rd='1' THEN
- index <= I; -- index of active master
- EXIT;
- END IF;
- END LOOP;
- END PROCESS;
-
- index_hold <= index WHEN rising_edge(mm_clk); -- hold index of last active master
-
-
- -- Multiplex master access, can be write or read
- mux_mosi <= master_mosi_arr(index);
-
- -- Multiplex slave read response
- p_miso : PROCESS(mux_miso, index)
- BEGIN
- master_miso_arr <= (OTHERS=>mux_miso); -- default assign to all, to avoid latches
- FOR I IN 0 TO g_nof_masters-1 LOOP
- master_miso_arr(I).rdval <= '0';
- -- If the minimal read latency is g_rd_latency_min = 0, then the mux
- -- has to use the combinatorial index, else it use the registered
- -- index, to ease achieving timing closure.
- IF g_rd_latency_min=0 THEN
- IF I = index THEN
- master_miso_arr(I).rdval <= mux_miso.rdval;
- END IF;
- ELSE
- IF I = index_hold THEN
- master_miso_arr(I).rdval <= mux_miso.rdval;
- END IF;
- END IF;
- END LOOP;
- END PROCESS;
-
- END GENERATE;
-
-END rtl;
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Multiplex an array of MM master interfaces to a single MM master
+-- interface
+-- Description:
+-- This mm_master_mux is a simple multiplexer that allows multiple
+-- masters to access the same MM port. The mm_master_mux does not
+-- provide arbitration between the masters in the array. Therefore the
+-- precondition is that the external application takes care that the MM
+-- accesses of the multiple masters in the array do not overlap in time.
+--
+-- Write accesses from multiple masters occur may without gaps. After a read
+-- access from one master the read latency must first be accounted for by
+-- the application introducing a gap, before a read access by another master
+-- can be multiplexed.
+--
+-- The mm_master_mux operates combinatorially, so it introduces no
+-- extra latency. The mm_clk is needed to hold the index of the master that
+-- is currently active, to ensure that the read data is passed on to the
+-- master that did the rd access.
+--
+-- Remarks:
+-- . This resembles common_mem_demux.vhd, but is not identical. The difference
+-- is that common_mem_demux is the inverse of common_mem_demux and therefore
+-- assumes that all the mux_mosi spans the entire array whereas for this
+-- mm_master_mux the mux_mosi spans one element.
+-- . There is no bus arbitrator. This is sufficient for use cases where e.g.
+-- one master only does some initialization accesses after reset and the
+-- other master is the main master that does all subsequent accesses.
+-- Therefore this mm_master_mux is typically suited per MM slave
+-- that needs dual master access, rather then to select between two main
+-- central MM masters.
+-- . There is no pipelining. The advantage is that the mux_miso.waitrequest is
+-- supported without extra effort.
+--
+-------------------------------------------------------------------------------
+
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+ENTITY mm_master_mux IS
+ GENERIC (
+ g_nof_masters : POSITIVE; -- Number of MM masters
+ g_rd_latency_min : NATURAL -- Minimum read latency
+ );
+ PORT (
+ mm_clk : IN STD_LOGIC;
+ master_mosi_arr : IN t_mem_mosi_arr(0 TO g_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
+ master_miso_arr : OUT t_mem_miso_arr(0 TO g_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
+ mux_mosi : OUT t_mem_mosi;
+ mux_miso : IN t_mem_miso
+ );
+END mm_master_mux;
+
+ARCHITECTURE rtl OF mm_master_mux IS
+
+ SIGNAL index : NATURAL := 0;
+ SIGNAL index_hold : NATURAL := 0;
+
+BEGIN
+
+ gen_single : IF g_nof_masters=1 GENERATE
+ mux_mosi <= master_mosi_arr(0);
+ master_miso_arr(0) <= mux_miso;
+ END GENERATE;
+
+ gen_multiple : IF g_nof_masters>1 GENERATE
+
+ -- Detect which master in the array is active
+ -- The pre condition is that the input masters will only start an access
+ -- when the mux master is free. For a rd access this means that the
+ -- read latency of the rdval has passed. Therefor it is not necessary
+ -- that this mm_master_mux maintains an index pipeline
+ -- from rd until expected rdval. Instead it is sufficient to hold the
+ -- index of the active master, until the next master does an access. For
+ -- rd access hold the last active index to ensure that rdval will be
+ -- directed to the master that orginated the rd access. For wr access
+ -- hold last active index instead of reset to '0' to ease observation of
+ -- the index value in wave window.
+ p_index : PROCESS(master_mosi_arr, index_hold)
+ BEGIN
+ index <= index_hold; -- default hold index of last active master
+ FOR I IN 0 TO g_nof_masters-1 LOOP
+ IF master_mosi_arr(I).wr='1' OR master_mosi_arr(I).rd='1' THEN
+ index <= I; -- index of active master
+ EXIT; -- Found active master, no need to loop further. EXIT is not
+ -- realy needed, because there should be only one active
+ -- master, and if there are more active masters, then it
+ -- does not matter whether the first or the last is selected.
+ END IF;
+ END LOOP;
+ END PROCESS;
+
+ index_hold <= index WHEN rising_edge(mm_clk); -- hold index of last active master
+
+
+ -- Multiplex master access, can be write or read
+ mux_mosi <= master_mosi_arr(index);
+
+ -- Multiplex slave read response
+ p_miso : PROCESS(mux_miso, index)
+ BEGIN
+ master_miso_arr <= (OTHERS=>mux_miso); -- default assign to all, to avoid latches
+ FOR I IN 0 TO g_nof_masters-1 LOOP
+ master_miso_arr(I).rdval <= '0';
+ -- If the minimal read latency is g_rd_latency_min = 0, then the mux
+ -- has to use the combinatorial index, else it use the registered
+ -- index, to ease achieving timing closure.
+ IF g_rd_latency_min=0 THEN
+ IF I = index THEN
+ master_miso_arr(I).rdval <= mux_miso.rdval;
+ END IF;
+ ELSE
+ IF I = index_hold THEN
+ master_miso_arr(I).rdval <= mux_miso.rdval;
+ END IF;
+ END IF;
+ END LOOP;
+ END PROCESS;
+
+ END GENERATE;
+
+END rtl;
diff --git a/libraries/base/mm/src/vhdl/mm_pipeline.vhd b/libraries/base/mm/src/vhdl/mm_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..179a3d51adfa85d3b5ed77c5bb1a449a2c50ff24
--- /dev/null
+++ b/libraries/base/mm/src/vhdl/mm_pipeline.vhd
@@ -0,0 +1,153 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Pipeline MM mosi
+-- Description:
+-- The mm_pipeline mosi registers the in_mosi if g_pipeline = TRUE, else it
+-- defaults to wires.
+--
+-- Background information
+-- The MM waitrequest resembles the behaviour of the streaming backpressure
+-- ready for ready latency RL = 0. For RL = 0 the ready acts as an
+-- acknowledge to pending data. For RL > 0 the ready acts as a request for
+-- new data. The miso.waitrequest is defined for RL = 0 but for analysis
+-- the timing diagrams below show an example of both RL = 0 and RL = 1. The
+-- miso.waitrequest is equivalent to NOT sosi.ready.
+--
+-- * RL=1
+-- _ _ _ _ _ _ _ _ _ _ _ _
+-- clk _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
+--
+-- in_dat |a |b |c |d
+-- _________ ___ ___
+-- in_val |_______| |_______| |_______________
+-- _____ ___ _______ ___________
+-- ready |_______| |___|... |_______|...........
+-- _________ ___ _______ _______
+-- reg_ready |_______| |___|... |_______|.......
+--
+-- reg_dat |a |b |c |d
+-- _____________________________ ___________
+-- reg_val |___| |___
+-- _________ ___ ___ ___
+-- out_val |a |_______|b |___|c |___________|d |___
+--
+--
+-- * RL=0
+-- _ _ _ _ _ _ _ _ _ _ _ _ _
+-- clk _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
+--
+-- in_dat |a |b |c |d |e
+-- _________ _______________ ___
+-- in_val |_______| |_______| |_______
+-- _____________ ___ _______ ___________
+-- ack |_______| |___| |___|
+--
+-- reg_dat |a |b |c |d |e
+-- _____________ ___________ ___
+-- reg_val |___________| |_______| |___
+-- _____________ _______ ___
+-- out_val |a |b |_______________|c |d |_______|e |___
+--
+-- In these timing diagrams the out_ready is wired to the in_ready, so
+-- therefore they are identical and called ready.
+-- The ready for RL = 0 or the reg_ready for RL = 1 is used to gate the
+-- out_val. The ready/reg_ready is used and not the in_val, because by
+-- using the ready/reg_ready the pipeline register is emptied as soon
+-- as the ready is active, rather than to wait for a next in_val to push
+-- it out. The ready/reg_ready have the same latency as the in_val,
+-- because they are both derived using the same RL.
+--
+-- Remark:
+-- * The mm_pipeline could be optimized regarding the miso.waitrequest flow
+-- control if it would be implemented similar as dp_pipeline.vhd. This
+-- involves using the pipeline register to accept an access when it is
+-- empty. In this way the waitrequest to the in_mosi only needs to apply
+-- when the out_miso is not ready and the pipeline is full. This would
+-- achieve the maximum throughput. The advantage of simply registering
+-- in_mosi and wiring in_miso is that it is simpler and does not put extra
+-- logic into the combinatorial miso.waitrequest path. It is better to
+-- keep it simpler and with less logic, then to try to win the last few
+-- percent of throughput.
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+ENTITY mm_pipeline IS
+ GENERIC (
+ g_pipeline : BOOLEAN := TRUE
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ in_mosi : IN t_mem_mosi;
+ in_miso : OUT t_mem_miso;
+ out_mosi : OUT t_mem_mosi;
+ out_miso : IN t_mem_miso
+ );
+END mm_pipeline;
+
+
+ARCHITECTURE rtl OF mm_pipeline IS
+
+ SIGNAL mosi_reg : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL nxt_mosi_reg : t_mem_mosi;
+ SIGNAL ready : STD_LOGIC;
+
+BEGIN
+
+ -- Pass on miso
+ in_miso <= out_miso;
+
+ -- Pipeline the mosi when g_pipeline = TRUE, else default to wires
+ gen_wires : IF g_pipeline = FALSE GENERATE
+ out_mosi <= in_mosi;
+ END GENERATE;
+
+ gen_pipeline : IF g_pipeline = TRUE GENERATE
+ p_reg : PROCESS(mm_rst, mm_clk)
+ BEGIN
+ IF mm_rst = '1' THEN
+ mosi_reg <= c_mem_mosi_rst;
+ ELSIF rising_edge(mm_clk) THEN
+ mosi_reg <= nxt_mosi_reg;
+ END IF;
+ END PROCESS;
+
+ ready <= NOT out_miso.waitrequest;
+
+ nxt_mosi_reg <= in_mosi WHEN ready = '1' ELSE mosi_reg;
+
+ p_out_mosi : PROCESS(mosi_reg, ready)
+ BEGIN
+ out_mosi <= mosi_reg;
+ IF ready /= '1' THEN
+ out_mosi.wr <= '0'; -- out_mosi.wr = mosi_reg.wr AND ready
+ out_mosi.rd <= '0'; -- out_mosi.rd = mosi_reg.rd AND ready
+ END IF;
+ END PROCESS;
+ END GENERATE;
+
+END rtl;
diff --git a/libraries/base/mm/src/vhdl/mm_slave_enable.vhd b/libraries/base/mm/src/vhdl/mm_slave_enable.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7803a14da266adc98274703022c01b4c8945d3b3
--- /dev/null
+++ b/libraries/base/mm/src/vhdl/mm_slave_enable.vhd
@@ -0,0 +1,122 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Connect an MM slave to the MM bus or represent an not connected
+-- slave. Force waitrequest = '0' if slave does not need mosi flow
+-- control
+-- Description:
+-- * g_enable
+-- When FALSE then the in_miso output tot the master is forced to
+-- c_mem_miso_rst to represent a not connected MM slave. When TRUE then
+-- the out_miso signal from the slave is passed on to the master.
+-- * g_waitrequest
+-- When FALSE then the in_miso.waitrequest is forced to '0' to indicate
+-- that the MM slave does not need mosi flow control. When FALSE then
+-- the miso.waitrequest from the connected slave is passed on to the
+-- master.
+-- * g_rd_latency
+-- Used to derive in_miso.rdval from in_mosi.rd and out_miso.waitrequest,
+-- to provide rdval for MM slaves that do not drive rdval. Typically any
+-- MM slave that needs miso.waitrequest flow control, also should support
+-- rdval themselves.
+--
+-- Todo:
+-- * Add miso.response field as defined in Avalon bus, to inform master about
+-- rd status (00 = okay, 01 = rsvd, 10 = slaveerror, 11 = decodeerror).
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+ENTITY mm_slave_enable IS
+ GENERIC (
+ g_enable : BOOLEAN;
+ g_waitrequest : BOOLEAN;
+ g_rd_latency : NATURAL
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ -- MM input RL = 1
+ in_mosi : IN t_mem_mosi;
+ in_miso : OUT t_mem_miso;
+ -- MM output RL = 0
+ out_mosi : OUT t_mem_mosi;
+ out_miso : IN t_mem_miso
+ );
+END mm_slave_enable;
+
+
+ARCHITECTURE rtl OF mm_slave_enable IS
+
+ SIGNAL rd : STD_LOGIC;
+ SIGNAL rdval : STD_LOGIC;
+ SIGNAL waitrequest : STD_LOGIC;
+
+BEGIN
+
+ -- Use mosi.rd to create miso.rdval for unconnected slave or for slaves that do not support rdval
+ u_rdval : ENTITY common_lib.common_pipeline_sl
+ GENERIC MAP (
+ g_pipeline => g_rd_latency
+ )
+ PORT MAP (
+ rst => mm_rst,
+ clk => mm_clk,
+ in_dat => rd,
+ out_dat => rdval
+ );
+
+
+ no_slave : IF g_enable = FALSE GENERATE
+ out_mosi <= c_mem_mosi_rst;
+
+ rd <= in_mosi.rd;
+
+ p_in_miso : PROCESS(rdval)
+ BEGIN
+ in_miso <= c_mem_miso_rst; -- force all miso to 0, so rddata = 0 and no waitrequest
+ in_miso.rdval <= rdval; -- support rdval to avoid hanging master that waits for rdval
+ END PROCESS;
+ END GENERATE;
+
+ gen_slave : IF g_enable = TRUE GENERATE
+ out_mosi <= in_mosi;
+
+ -- Use waitrequest from slave, or force waitrequest = '0' if slave does not need mosi flow control
+ waitrequest <= out_miso.waitrequest WHEN g_waitrequest = TRUE ELSE '0';
+
+ rd <= in_mosi.rd AND NOT waitrequest;
+
+ p_in_miso : PROCESS(out_miso, rdval, waitrequest)
+ BEGIN
+ in_miso <= out_miso;
+ in_miso.rdval <= rdval;
+ in_miso.waitrequest <= waitrequest;
+ END PROCESS;
+ END GENERATE;
+
+END rtl;
diff --git a/libraries/base/mm/src/vhdl/mm_slave_mux.vhd b/libraries/base/mm/src/vhdl/mm_slave_mux.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c2a61ace47ece1df90a026338eceb366c79e7341
--- /dev/null
+++ b/libraries/base/mm/src/vhdl/mm_slave_mux.vhd
@@ -0,0 +1,70 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Combines an array of MM interfaces into a single MM interface.
+-- Description:
+-- Wraps common_mem_mux.vhd.
+-- Remark:
+-- No need for g_rd_latency pipelining, so pure combinatorial and no need
+-- for clk. If necessary apply pipelining via mm_bus.vhd.
+-------------------------------------------------------------------------------
+
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+ENTITY mm_slave_mux IS
+ GENERIC (
+ g_broadcast : BOOLEAN := FALSE; -- TRUE use port[0] to access all, else use separate ports
+ g_nof_mosi : POSITIVE := 256; -- Number of slave memory interfaces in the array.
+ g_mosi_addr_w : POSITIVE := 8 -- Address width per slave
+ );
+ PORT (
+ mosi : IN t_mem_mosi;
+ miso : OUT t_mem_miso;
+ mosi_arr : OUT t_mem_mosi_arr(g_nof_mosi - 1 DOWNTO 0);
+ miso_arr : IN t_mem_miso_arr(g_nof_mosi - 1 DOWNTO 0) := (OTHERS=>c_mem_miso_rst)
+ );
+END mm_slave_mux;
+
+ARCHITECTURE str OF mm_slave_mux IS
+BEGIN
+
+ u_common_mem_mux : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_broadcast => g_broadcast,
+ g_nof_mosi => g_nof_mosi,
+ g_mult_addr_w => g_mosi_addr_w,
+ g_rd_latency => 0
+ )
+ PORT MAP (
+ clk => '0', -- only used when g_rd_latency > 0
+ mosi => mosi,
+ miso => miso,
+ mosi_arr => mosi_arr,
+ miso_arr => miso_arr
+ );
+
+END str;
diff --git a/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd b/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
index f253848f810b786efb2ead64f221e735c510d625..1b0148e99c85b83e36a8ed7e61c82d1ea343c83e 100644
--- a/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
@@ -1,757 +1,757 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2017
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Author :
--- D. van der Schuur May 2012 Original for Python - file IO - VHDL
--- E. Kooistra feb 2017 Added purpose and description
--- Added procedures for external control in a
--- pure VHDL test bench.
---
--- Purpose: Provide DUT access via MM bus through file IO per MM slave
--- Description:
--- This package provides file IO access to MM slaves and to the status of
--- the simulation:
---
--- 1) MM slave access
--- Access to MM slaves is provided by component mm_file.vhd that first calls
--- mmf_file_create() and loop forever calling mmf_mm_from_file(). Each MM
--- slave has a dedicated pair of request (.ctrl) and response (.stat) IO
--- files.
--- The mmf_file_create() creates the .ctrl file and mmf_mm_from_file() reads
--- it to check whether there is a WR or RD access request. For a WR request
--- the wr_data and wr_addr are read from the .ctrl and output on the MM bus
--- via mm_mosi. For a RD access request the rd_addr is read from the .ctrl
--- and output on the MM bus via mm_mosi. The after the read latency the
--- rd_data is written to the .stat file that is then created and closed.
---
--- wr rd _________ __________
--- mmf_mm_bus_wr() ---> ctrl file --->| |---mm_mosi-->| |
--- | mm_file | | MM slave |
--- mmf_mm_bus_rd() <--- stat file <---|___\_____|<--mm_miso---|__________|
--- rd wr \
--- \--> loop: mmf_mm_from_file()
---
--- The ctrl file is created by mm_file at initialization and recreated by
--- every call of mmf_mm_from_file().
--- The stat file is recreated by every call of mmf_mm_bus_rd().
---
--- 2) Simulator access
--- External access to the simulation is provided via a .ctrl file that
--- supports GET_SIM_TIME and then report the NOW time via the .stat file.
--- The simulation access is provided via a procedure mmf_poll_sim_ctrl_file()
--- that works similar component mm_file.vhd.
---
--- wr rd
--- |---> ctrl file --->|
--- mmf_sim_get_now()| |mmf_poll_sim_ctrl_file()
--- |<--- stat file <---| \
--- rd wr \
--- \--> loop: mmf_sim_ctrl_from_file()
---
--- The ctrl file is created by mmf_poll_sim_ctrl_file at initialization and
--- recreated by every call of mmf_sim_ctrl_from_file().
--- The stat file is recreated by every call of mmf_sim_get_now().
---
--- A) External control by a Python script
--- A Python script can issue requests via the .ctrl files to control the
--- simulation and read the .stat files. This models the MM access via a
--- Monitoring and Control protocol via 1GbE.
---
--- Internal procedures:
--- . mmf_file_create(filename: IN STRING);
--- . mmf_mm_from_file(SIGNAL mm_clk : IN STD_LOGIC;
--- . mmf_sim_ctrl_from_file(rd_filename: IN STRING;
---
--- External procedures (used in a VHDL design to provide access to the MM
--- slaves and simulation via file IO):
--- . mm_file.vhd --> instead of a procedure MM slave file IO uses a component
--- . mmf_poll_sim_ctrl_file()
---
--- B) External control by a VHDL process --> see tb_mm_file.vhd
--- Instead of a Python script the file IO access to the MM slaves can also
--- be used in a pure VHDL testbench. This is useful when the MM slave bus
--- signals (mm_mosi, mm_miso) are not available on the entity of the DUT
--- (device under test), which is typically the case when a complete FPGA
--- design needs to be simulated.
---
--- Internal procedures:
--- . mmf_wait_for_file_status()
--- . mmf_wait_for_file_empty()
--- . mmf_wait_for_file_not_empty()
---
--- External procedures (used in a VHDL test bench to provide access to the
--- MM slaves in a DUT VHDL design and simulation via file IO):
--- . mmf_mm_bus_wr()
--- . mmf_mm_bus_rd()
--- . mmf_sim_get_now()
---
--- External function to create unique sim.ctrl/sim.stat filename per test bench in a multi tb
--- . mmf_slave_prefix()
---
--- Remarks:
--- . The timing of the MM access in mmf_mm_bus_wr() and mmf_mm_bus_rd() and the
--- simulation access in mmf_sim_get_now() is not critical. The timing of the first
--- access depends on the tb. Due to falling_edge(mm_clk) in mmf_wait_for_file_*()
--- all subsequent accesses will start at falling_edge(mm_clk)
-
-LIBRARY IEEE, common_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.tb_common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE common_lib.tb_common_mem_pkg.ALL;
-USE std.textio.ALL;
-USE IEEE.std_logic_textio.ALL;
-USE common_lib.common_str_pkg.ALL;
-
-PACKAGE mm_file_pkg IS
-
- -- Constants used by mm_file.vhd
- CONSTANT c_mmf_mm_clk_period : TIME := 100 ps; -- Default mm_clk period in simulation. Set much faster than DP clock to speed up
- -- simulation of MM access. Without file IO throttling 100 ps is a good balance
- -- between simulation speed and file IO rate.
- CONSTANT c_mmf_mm_timeout : TIME := 1000 ns; -- Default MM file IO timeout period. Set large enough to account for MM-DP clock
- -- domain crossing delays. Use 0 ns to disable file IO throttling, to have file IO
- -- at the mm_clk rate.
- CONSTANT c_mmf_mm_pause : TIME := 100 ns; -- Default MM file IO pause period after timeout. Balance between file IO rate
- -- reduction and responsiveness to new MM access.
-
- -- Procedure to (re)create empty file
- PROCEDURE mmf_file_create(filename: IN STRING);
-
- -- Procedure to perform an MM access from file
- PROCEDURE mmf_mm_from_file(SIGNAL mm_clk : IN STD_LOGIC;
- SIGNAL mm_rst : IN STD_LOGIC;
- SIGNAL mm_mosi : OUT t_mem_mosi;
- SIGNAL mm_miso : IN t_mem_miso;
- rd_filename: IN STRING;
- wr_filename: IN STRING;
- rd_latency: IN NATURAL);
-
- -- Procedure to process a simulation status request from the .ctrl file and provide response via the .stat file
- PROCEDURE mmf_sim_ctrl_from_file(rd_filename: IN STRING;
- wr_filename: IN STRING);
-
- -- Procedure to poll the simulation status
- PROCEDURE mmf_poll_sim_ctrl_file(rd_file_name: IN STRING;
- wr_file_name: IN STRING);
-
- -- Procedure to poll the simulation status
- PROCEDURE mmf_poll_sim_ctrl_file(SIGNAL mm_clk : IN STD_LOGIC;
- rd_file_name: IN STRING;
- wr_file_name: IN STRING);
-
- -- Procedures that keep reading the file until it has been made empty or not empty by some other program,
- -- to ensure the file is ready for a new write access
- PROCEDURE mmf_wait_for_file_status(rd_filename : IN STRING; -- file name with extension
- exit_on_empty : IN BOOLEAN;
- SIGNAL mm_clk : IN STD_LOGIC);
-
- PROCEDURE mmf_wait_for_file_empty(rd_filename : IN STRING; -- file name with extension
- SIGNAL mm_clk : IN STD_LOGIC);
- PROCEDURE mmf_wait_for_file_not_empty(rd_filename : IN STRING; -- file name with extension
- SIGNAL mm_clk : IN STD_LOGIC);
-
- -- Procedure to issue a write access via the MM request .ctrl file
- PROCEDURE mmf_mm_bus_wr(filename : IN STRING; -- file name without extension
- wr_addr : IN INTEGER; -- use integer to support full 32 bit range
- wr_data : IN INTEGER;
- SIGNAL mm_clk : IN STD_LOGIC);
-
- -- Procedure to issue a read access via the MM request .ctrl file and get the read data from the MM response file
- PROCEDURE mmf_mm_bus_rd(filename : IN STRING; -- file name without extension
- rd_latency : IN NATURAL;
- rd_addr : IN INTEGER; -- use integer to support full 32 bit range
- SIGNAL rd_data : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- SIGNAL mm_clk : IN STD_LOGIC);
- -- . rd_latency = 1
- PROCEDURE mmf_mm_bus_rd(filename : IN STRING;
- rd_addr : IN INTEGER;
- SIGNAL rd_data : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- SIGNAL mm_clk : IN STD_LOGIC);
-
- -- Procedure that reads the rd_data every rd_interval until has the specified rd_value, the proc arguments can be understood as a sentence
- PROCEDURE mmf_mm_wait_until_value(filename : IN STRING; -- file name without extension
- rd_addr : IN INTEGER;
- c_representation : IN STRING; -- treat rd_data as "SIGNED" or "UNSIGNED" 32 bit word
- SIGNAL rd_data : INOUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- c_condition : IN STRING; -- ">", ">=", "=", "<=", "<", "/="
- c_rd_value : IN INTEGER;
- c_rd_interval : IN TIME;
- SIGNAL mm_clk : IN STD_LOGIC);
-
- -- Procedure to get NOW via simulator status
- PROCEDURE mmf_sim_get_now(filename : IN STRING; -- file name without extension
- SIGNAL rd_now : OUT STRING;
- SIGNAL mm_clk : IN STD_LOGIC);
-
- -- Functions to create prefixes for the mmf file filename
- FUNCTION mmf_prefix(name : STRING; index : NATURAL) RETURN STRING; -- generic prefix name with index to be used for a file IO filename
- FUNCTION mmf_tb_prefix(tb : INTEGER) RETURN STRING; -- fixed test bench prefix with index tb to allow file IO with multi tb
- FUNCTION mmf_subrack_prefix(subrack : INTEGER) RETURN STRING; -- fixed subrack prefix with index subrack to allow file IO with multi subracks that use same unb numbers
-
- -- Functions to create mmf file prefix that is unique per slave, for increasing number of hierarchy levels:
- -- . return "filepath/s0_i0_"
- -- . return "filepath/s0_i0_s1_i1_"
- -- . return "filepath/s0_i0_s1_i1_s2_i2_"
- -- . return "filepath/s0_i0_s1_i1_s2_i2_s3_i3_"
- -- . return "filepath/s0_i0_s1_i1_s2_i2_s3_i3_s4_i4_"
- FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL) RETURN STRING;
- FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL) RETURN STRING;
- FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL) RETURN STRING;
- FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL) RETURN STRING;
- FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL; s4 : STRING; i4 : NATURAL) RETURN STRING;
-
- CONSTANT c_mmf_local_dir_path : STRING := "mmfiles/"; -- local directory in project file build directory
- FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL) RETURN STRING;
- FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL) RETURN STRING;
- FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL) RETURN STRING;
- FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL) RETURN STRING;
- FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL; s4 : STRING; i4 : NATURAL) RETURN STRING;
-
- ----------------------------------------------------------------------------
- -- Declare mm_file component to support positional generic and port mapping of many instances in a TB
- ----------------------------------------------------------------------------
- COMPONENT mm_file
- GENERIC(
- g_file_prefix : STRING;
- g_file_enable : STD_LOGIC := '1';
- g_mm_rd_latency : NATURAL := 2;
- g_mm_timeout : TIME := c_mmf_mm_timeout;
- g_mm_pause : TIME := c_mmf_mm_pause
- );
- PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi;
- mm_master_in : IN t_mem_miso
- );
- END COMPONENT;
-
-END mm_file_pkg;
-
-PACKAGE BODY mm_file_pkg IS
-
- PROCEDURE mmf_file_create(filename: IN STRING) IS
- FILE created_file : TEXT OPEN write_mode IS filename;
- BEGIN
- -- Write the file with nothing in it
- write(created_file, "");
- END;
-
- PROCEDURE mmf_mm_from_file(SIGNAL mm_clk : IN STD_LOGIC;
- SIGNAL mm_rst : IN STD_LOGIC;
- SIGNAL mm_mosi : OUT t_mem_mosi;
- SIGNAL mm_miso : IN t_mem_miso;
- rd_filename: IN STRING;
- wr_filename: IN STRING;
- rd_latency: IN NATURAL) IS
- FILE rd_file : TEXT;
- FILE wr_file : TEXT;
-
- VARIABLE open_status_rd: file_open_status;
- VARIABLE open_status_wr: file_open_status;
-
- VARIABLE rd_line : LINE;
- VARIABLE wr_line : LINE;
-
- -- Note: Both the address and the data are interpreted as 32-bit data!
- -- This means one has to use leading zeros in the file when either is
- -- less than 8 hex characters, e.g.:
- -- (address) 0000000A
- -- (data) DEADBEEF
- -- ...as a hex address 'A' would fit in only 4 bits, causing an error in hread().
- VARIABLE v_addr_slv : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- VARIABLE v_data_slv : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
-
- VARIABLE v_rd_wr_str : STRING(1 TO 2); -- Contains 'RD' or 'WR'
-
- BEGIN
-
- proc_common_wait_until_low(mm_clk, mm_rst);
-
- -- We have to open the file explicitely so we can check the status
- file_open(open_status_rd, rd_file, rd_filename, read_mode);
-
- -- open_status may throw an error if the file is being written to by some other program
- IF open_status_rd=open_ok THEN
-
- IF NOT endfile(rd_file) THEN
- -- The file is not empty: process its contents
-
- -- Read a line from it, first line indicates RD or WR
- readline(rd_file, rd_line);
- read(rd_line, v_rd_wr_str);
-
- -- The second line represents the address offset:
- readline(rd_file, rd_line);
- hread(rd_line, v_addr_slv); -- read the string as HEX and assign to SLV.
-
- -- Write only: The third line contains the data to write:
- IF v_rd_wr_str="WR" THEN
- readline(rd_file, rd_line);
- hread(rd_line, v_data_slv); -- read the string as HEX and assign to SLV.
- END IF;
-
- -- We're done reading MM request from the .ctrl file.
- -- Clear the .ctrl file by closing and recreating it, because we don't want to do the same
- -- MM request again the next time this procedure is called.
- file_close(rd_file);
- mmf_file_create(rd_filename);
-
- -- Execute the MM request to the MM slave
- IF v_rd_wr_str="WR" THEN
- print_str("[" & time_to_str(now) & "] " & rd_filename & ": Writing 0x" & slv_to_hex(v_data_slv) & " to address 0x" & slv_to_hex(v_addr_slv));
- -- Treat 32 bit hex data from file as 32 bit VHDL INTEGER, so need to use signed TO_SINT() to avoid out of NATURAL range
- -- warning in simulation due to '1' sign bit, because unsigned VHDL NATURAL only fits 31 bits
- proc_mem_mm_bus_wr(TO_UINT(v_addr_slv), TO_SINT(v_data_slv), mm_clk, mm_miso, mm_mosi);
-
- ELSIF v_rd_wr_str="RD" THEN
- proc_mem_mm_bus_rd(TO_UINT(v_addr_slv), mm_clk, mm_miso, mm_mosi);
- IF rd_latency>0 THEN
- proc_mem_mm_bus_rd_latency(rd_latency, mm_clk);
- END IF;
- v_data_slv := mm_miso.rddata(31 DOWNTO 0);
- print_str("[" & time_to_str(now) & "] " & rd_filename & ": Reading from address 0x" & slv_to_hex(v_addr_slv) & ": 0x" & slv_to_hex(v_data_slv));
-
- -- Write the RD response read data to the .stat file
- file_open(open_status_wr, wr_file, wr_filename, write_mode);
- hwrite(wr_line, v_data_slv);
- writeline(wr_file, wr_line);
- file_close(wr_file);
- END IF;
-
- ELSE
- -- Nothing to process; wait one MM clock cycle.
- proc_common_wait_some_cycles(mm_clk, 1);
- END IF;
-
- ELSE
- REPORT "mmf_mm_from_file() could not open " & rd_filename & " at " & time_to_str(now) SEVERITY NOTE;
- -- Try again next time; wait one MM clock cycle.
- proc_common_wait_some_cycles(mm_clk, 1);
- END IF;
-
- -- The END implicitely close the rd_file, if still necessary.
- END;
-
-
- PROCEDURE mmf_sim_ctrl_from_file(rd_filename: IN STRING;
- wr_filename: IN STRING) IS
-
- FILE rd_file : TEXT;
- FILE wr_file : TEXT;
-
- VARIABLE open_status_rd: file_open_status;
- VARIABLE open_status_wr: file_open_status;
-
- VARIABLE rd_line : LINE;
- VARIABLE wr_line : LINE;
-
- VARIABLE v_rd_wr_str : STRING(1 TO 12); -- "GET_SIM_TIME"
-
- BEGIN
-
- -- We have to open the file explicitely so we can check the status
- file_open(open_status_rd, rd_file, rd_filename, read_mode);
-
- -- open_status may throw an error if the file is being written to by some other program
- IF open_status_rd=open_ok THEN
-
- IF NOT endfile(rd_file) THEN
- -- The file is not empty: process its contents
-
- -- Read a line from it, interpret the simulation request
- readline(rd_file, rd_line);
- read(rd_line, v_rd_wr_str);
-
- -- We're done reading this simulation request .ctrl file. Clear the file by closing and recreating it.
- file_close(rd_file);
- mmf_file_create(rd_filename);
-
- -- Execute the simulation request
- IF v_rd_wr_str="GET_SIM_TIME" THEN
- -- Write the GET_SIM_TIME response time NOW to the .stat file
- file_open(open_status_wr, wr_file, wr_filename, write_mode);
- write(wr_line, time_to_str(now));
- writeline(wr_file, wr_line);
- file_close(wr_file);
- END IF;
-
- ELSE
- -- Nothing to process; wait in procedure mmf_poll_sim_ctrl_file
- NULL;
- END IF;
-
- ELSE
- REPORT "mmf_mm_from_file() could not open " & rd_filename & " at " & time_to_str(now) SEVERITY NOTE;
- -- Try again next time; wait in procedure mmf_poll_sim_ctrl_file
- END IF;
-
- -- The END implicitely close the rd_file, if still necessary.
- END;
-
-
- PROCEDURE mmf_poll_sim_ctrl_file(rd_file_name: IN STRING; wr_file_name : IN STRING) IS
- BEGIN
- -- Create the ctrl file that we're going to read from
- print_str("[" & time_to_str(now) & "] " & rd_file_name & ": Created" );
- mmf_file_create(rd_file_name);
-
- WHILE TRUE LOOP
- mmf_sim_ctrl_from_file(rd_file_name, wr_file_name);
- WAIT FOR 1 ns;
- END LOOP;
-
- END;
-
-
- PROCEDURE mmf_poll_sim_ctrl_file(SIGNAL mm_clk : IN STD_LOGIC;
- rd_file_name: IN STRING; wr_file_name : IN STRING) IS
- BEGIN
- -- Create the ctrl file that we're going to read from
- print_str("[" & time_to_str(now) & "] " & rd_file_name & ": Created" );
- mmf_file_create(rd_file_name);
-
- WHILE TRUE LOOP
- mmf_sim_ctrl_from_file(rd_file_name, wr_file_name);
- proc_common_wait_some_cycles(mm_clk, 1);
- END LOOP;
-
- END;
-
-
- PROCEDURE mmf_wait_for_file_status(rd_filename : IN STRING; -- file name with extension
- exit_on_empty : IN BOOLEAN;
- SIGNAL mm_clk : IN STD_LOGIC) IS
- FILE rd_file : TEXT;
- VARIABLE open_status_rd : file_open_status;
- VARIABLE v_endfile : BOOLEAN;
- BEGIN
- -- Check on falling_edge(mm_clk) because mmf_mm_from_file() operates on rising_edge(mm_clk)
- -- Note: In fact the file IO also works fine when rising_edge() is used, but then
- -- tb_tb_mm_file.vhd takes about 1% more mm_clk cycles
- WAIT UNTIL falling_edge(mm_clk);
-
- -- Keep reading the file until it has become empty by some other program
- WHILE TRUE LOOP
- -- Open the file in read mode to check whether it is empty
- file_open(open_status_rd, rd_file, rd_filename, read_mode);
- -- open_status may throw an error if the file is being written to by some other program
- IF open_status_rd=open_ok THEN
- v_endfile := endfile(rd_file);
- file_close(rd_file);
- IF exit_on_empty THEN
- IF v_endfile THEN
- -- The file is empty; continue
- EXIT;
- ELSE
- -- The file is not empty; wait one MM clock cycle.
- WAIT UNTIL falling_edge(mm_clk);
- END IF;
- ELSE
- IF v_endfile THEN
- -- The file is empty; wait one MM clock cycle.
- WAIT UNTIL falling_edge(mm_clk);
- ELSE
- -- The file is not empty; continue
- EXIT;
- END IF;
- END IF;
- ELSE
- REPORT "mmf_wait_for_file_status() could not open " & rd_filename & " at " & time_to_str(now) SEVERITY NOTE;
- WAIT UNTIL falling_edge(mm_clk);
- END IF;
- END LOOP;
- -- The END implicitely close the file, if still necessary.
- END;
-
- PROCEDURE mmf_wait_for_file_empty(rd_filename : IN STRING; -- file name with extension
- SIGNAL mm_clk : IN STD_LOGIC) IS
- BEGIN
- mmf_wait_for_file_status(rd_filename, TRUE, mm_clk);
- END;
-
- PROCEDURE mmf_wait_for_file_not_empty(rd_filename : IN STRING; -- file name with extension
- SIGNAL mm_clk : IN STD_LOGIC) IS
- BEGIN
- mmf_wait_for_file_status(rd_filename, FALSE, mm_clk);
- END;
-
- PROCEDURE mmf_mm_bus_wr(filename : IN STRING; -- file name without extension
- wr_addr : IN INTEGER; -- use integer to support full 32 bit range
- wr_data : IN INTEGER;
- SIGNAL mm_clk : IN STD_LOGIC) IS
- CONSTANT ctrl_filename : STRING := filename & ".ctrl";
- FILE ctrl_file : TEXT;
- VARIABLE open_status_wr : file_open_status;
- VARIABLE wr_line : LINE;
-
- BEGIN
- -- Write MM WR access to the .ctrl file.
- -- The MM device is ready for a new MM request, because any previous MM request has finished at
- -- mmf_mm_bus_wr() or mmf_mm_bus_rd() procedure exit, therefore just overwrite the .ctrl file.
- file_open(open_status_wr, ctrl_file, ctrl_filename, write_mode);
- -- open_status may throw an error if the file is being written to by some other program
- IF open_status_wr=open_ok THEN
- write(wr_line, STRING'("WR"));
- writeline(ctrl_file, wr_line);
- hwrite(wr_line, TO_SVEC(wr_addr, c_word_w));
- writeline(ctrl_file, wr_line);
- hwrite(wr_line, TO_SVEC(wr_data, c_word_w));
- writeline(ctrl_file, wr_line);
- file_close(ctrl_file);
- ELSE
- REPORT "mmf_mm_bus_wr() could not open " & ctrl_filename & " at " & time_to_str(now) SEVERITY NOTE;
- END IF;
-
- -- Prepare for next MM request
- -- Keep reading the .ctrl file until it is empty, to ensure that the MM device is ready for a new MM request
- mmf_wait_for_file_empty(ctrl_filename, mm_clk);
-
- -- The END implicitely close the ctrl_file, if still necessary.
- END;
-
- PROCEDURE mmf_mm_bus_rd(filename : IN STRING; -- file name without extension
- rd_latency : IN NATURAL;
- rd_addr : IN INTEGER; -- use integer to support full 32 bit range
- SIGNAL rd_data : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- SIGNAL mm_clk : IN STD_LOGIC) IS
- CONSTANT ctrl_filename : STRING := filename & ".ctrl";
- CONSTANT stat_filename : STRING := filename & ".stat";
- FILE ctrl_file : TEXT;
- FILE stat_file : TEXT;
- VARIABLE open_status_wr : file_open_status;
- VARIABLE open_status_rd : file_open_status;
- VARIABLE wr_line : LINE;
- VARIABLE rd_line : LINE;
- VARIABLE v_rd_data : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
-
- BEGIN
- -- Clear the .stat file by recreating it, because we don't want to do read old file data again
- mmf_file_create(stat_filename);
-
- -- Write MM RD access to the .ctrl file.
- -- The MM device is ready for a new MM request, because any previous MM request has finished at
- -- mmf_mm_bus_wr() or mmf_mm_bus_rd() procedure exit, therefore just overwrite the .ctrl file.
- file_open(open_status_wr, ctrl_file, ctrl_filename, write_mode);
- -- open_status may throw an error if the file is being written to by some other program
- IF open_status_wr=open_ok THEN
- write(wr_line, STRING'("RD"));
- writeline(ctrl_file, wr_line);
- hwrite(wr_line, TO_SVEC(rd_addr, c_word_w));
- writeline(ctrl_file, wr_line);
- file_close(ctrl_file);
- ELSE
- REPORT "mmf_mm_bus_rd() could not open " & ctrl_filename & " at " & time_to_str(now) SEVERITY FAILURE;
- END IF;
-
- -- Wait until the MM RD access has written the read data to the .stat file
- mmf_wait_for_file_not_empty(stat_filename, mm_clk);
-
- -- Read the MM RD access read data from the .stat file
- file_open(open_status_rd, stat_file, stat_filename, read_mode);
- -- open_status may throw an error if the file is being written to by some other program
- IF open_status_rd=open_ok THEN
- readline(stat_file, rd_line);
- hread(rd_line, v_rd_data);
- file_close(stat_file);
- rd_data <= v_rd_data;
- -- wait to ensure rd_data has got v_rd_data, otherwise rd_data still holds the old data on procedure exit
- -- the wait should be < mm_clk period/2 to not affect the read rate
- WAIT FOR 1 fs;
- ELSE
- REPORT "mmf_mm_bus_rd() could not open " & stat_filename & " at " & time_to_str(now) SEVERITY FAILURE;
- END IF;
-
- -- No need to prepare for next MM request, because:
- -- . the .ctrl file must already be empty because the .stat file was there
- -- . the .stat file will be cleared on this procedure entry
-
- -- The END implicitely closes the files, if still necessary
- END;
-
- -- rd_latency = 1
- PROCEDURE mmf_mm_bus_rd(filename : IN STRING;
- rd_addr : IN INTEGER;
- SIGNAL rd_data : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- SIGNAL mm_clk : IN STD_LOGIC) IS
- BEGIN
- mmf_mm_bus_rd(filename, 1, rd_addr, rd_data, mm_clk);
- END;
-
- PROCEDURE mmf_mm_wait_until_value(filename : IN STRING; -- file name without extension
- rd_addr : IN INTEGER;
- c_representation : IN STRING; -- treat rd_data as "SIGNED" or "UNSIGNED" 32 bit word
- SIGNAL rd_data : INOUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- c_condition : IN STRING; -- ">", ">=", "=", "<=", "<", "/="
- c_rd_value : IN INTEGER;
- c_rd_interval : IN TIME;
- SIGNAL mm_clk : IN STD_LOGIC) IS
- BEGIN
- WHILE TRUE LOOP
- -- Read current
- mmf_mm_bus_rd(filename, rd_addr, rd_data, mm_clk); -- only read low part
- IF c_representation="SIGNED" THEN
- IF c_condition=">" THEN IF TO_SINT(rd_data)> c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
- ELSIF c_condition=">=" THEN IF TO_SINT(rd_data)>=c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
- ELSIF c_condition="/=" THEN IF TO_SINT(rd_data)/=c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
- ELSIF c_condition="<=" THEN IF TO_SINT(rd_data)<=c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
- ELSIF c_condition="<" THEN IF TO_SINT(rd_data)< c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
- ELSE IF TO_SINT(rd_data) =c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF; -- default: "="
- END IF;
- ELSE -- default: UNSIGED
- IF c_condition=">" THEN IF TO_UINT(rd_data)> c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
- ELSIF c_condition=">=" THEN IF TO_UINT(rd_data)>=c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
- ELSIF c_condition="/=" THEN IF TO_UINT(rd_data)/=c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
- ELSIF c_condition="<=" THEN IF TO_UINT(rd_data)<=c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
- ELSIF c_condition="<" THEN IF TO_UINT(rd_data)< c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
- ELSE IF TO_UINT(rd_data) =c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF; -- default: "="
- END IF;
- END IF;
- END LOOP;
- END mmf_mm_wait_until_value;
-
-
- PROCEDURE mmf_sim_get_now(filename : IN STRING; -- file name without extension
- SIGNAL rd_now : OUT STRING;
- SIGNAL mm_clk : IN STD_LOGIC) IS
- CONSTANT ctrl_filename : STRING := filename & ".ctrl";
- CONSTANT stat_filename : STRING := filename & ".stat";
- FILE ctrl_file : TEXT;
- FILE stat_file : TEXT;
- VARIABLE open_status_wr : file_open_status;
- VARIABLE open_status_rd : file_open_status;
- VARIABLE wr_line : LINE;
- VARIABLE rd_line : LINE;
- VARIABLE v_rd_now : STRING(rd_now'RANGE);
-
- BEGIN
- -- Clear the sim.stat file by recreating it, because we don't want to do read old simulator status again
- mmf_file_create(stat_filename);
-
- -- Write GET_SIM_TIME to the sim.ctrl file
- -- The simulation is ready for a new simulation status request, because any previous simulation status request has finished at
- -- mmf_sim_get_now() procedure exit, therefore just overwrite the .ctrl file.
- file_open(open_status_wr, ctrl_file, ctrl_filename, write_mode);
- -- open_status may throw an error if the file is being written to by some other program
- IF open_status_wr=open_ok THEN
- write(wr_line, STRING'("GET_SIM_TIME"));
- writeline(ctrl_file, wr_line);
- file_close(ctrl_file);
- ELSE
- REPORT "mmf_sim_get_now() could not open " & ctrl_filename & " at " & time_to_str(now) SEVERITY FAILURE;
- END IF;
-
- -- Wait until the simulation has written the simulation status to the sim.stat file
- mmf_wait_for_file_not_empty(stat_filename, mm_clk);
-
- -- Read the GET_SIM_TIME simulation status from the .stat file
- file_open(open_status_rd, stat_file, stat_filename, read_mode);
- -- open_status may throw an error if the file is being written to by some other program
- IF open_status_rd=open_ok THEN
- readline(stat_file, rd_line);
- read(rd_line, v_rd_now);
- file_close(stat_file);
- rd_now <= v_rd_now;
- print_str("GET_SIM_TIME = " & v_rd_now & " at " & time_to_str(now));
- ELSE
- REPORT "mmf_sim_get_now() could not open " & stat_filename & " at " & time_to_str(now) SEVERITY FAILURE;
- END IF;
-
- -- No need to prepare for next simulation status request, because:
- -- . the .ctrl file must already be empty because the .stat file was there
- -- . the .stat file will be cleared on this procedure entry
-
- -- The END implicitely closes the files, if still necessary
- END;
-
- -- Functions to create prefixes for the mmf file filename
- FUNCTION mmf_prefix(name : STRING; index : NATURAL) RETURN STRING IS
- BEGIN
- RETURN name & "_" & int_to_str(index) & "_";
- END;
-
- FUNCTION mmf_tb_prefix(tb : INTEGER) RETURN STRING IS
- BEGIN
- RETURN mmf_prefix("TB", tb);
- END;
-
- FUNCTION mmf_subrack_prefix(subrack : INTEGER) RETURN STRING IS
- BEGIN
- RETURN mmf_prefix("SUBRACK", subrack);
- END;
-
- -- Functions to create mmf file prefix that is unique per slave, for increasing number of hierarchy levels:
- FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL) RETURN STRING IS
- BEGIN
- RETURN dir_path & mmf_prefix(s0, i0);
- END;
-
- FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL) RETURN STRING IS
- BEGIN
- RETURN dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1);
- END;
-
- FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL) RETURN STRING IS
- BEGIN
- RETURN dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1) & mmf_prefix(s2, i2);
- END;
-
- FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL) RETURN STRING IS
- BEGIN
- RETURN dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1) & mmf_prefix(s2, i2) & mmf_prefix(s3, i3);
- END;
-
- FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL; s4 : STRING; i4 : NATURAL) RETURN STRING IS
- BEGIN
- RETURN dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1) & mmf_prefix(s2, i2) & mmf_prefix(s3, i3) & mmf_prefix(s4, i4);
- END;
-
- -- Use local dir_path
- FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL) RETURN STRING IS
- BEGIN
- RETURN c_mmf_local_dir_path & mmf_prefix(s0, i0);
- END;
-
- FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL) RETURN STRING IS
- BEGIN
- RETURN c_mmf_local_dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1);
- END;
-
- FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL) RETURN STRING IS
- BEGIN
- RETURN c_mmf_local_dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1) & mmf_prefix(s2, i2);
- END;
-
- FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL) RETURN STRING IS
- BEGIN
- RETURN c_mmf_local_dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1) & mmf_prefix(s2, i2) & mmf_prefix(s3, i3);
- END;
-
- FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL; s4 : STRING; i4 : NATURAL) RETURN STRING IS
- BEGIN
- RETURN c_mmf_local_dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1) & mmf_prefix(s2, i2) & mmf_prefix(s3, i3) & mmf_prefix(s4, i4);
- END;
-
-END mm_file_pkg;
-
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2017
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Author :
+-- D. van der Schuur May 2012 Original for Python - file IO - VHDL
+-- E. Kooistra feb 2017 Added purpose and description
+-- Added procedures for external control in a
+-- pure VHDL test bench.
+--
+-- Purpose: Provide DUT access via MM bus through file IO per MM slave
+-- Description:
+-- This package provides file IO access to MM slaves and to the status of
+-- the simulation:
+--
+-- 1) MM slave access
+-- Access to MM slaves is provided by component mm_file.vhd that first calls
+-- mmf_file_create() and loop forever calling mmf_mm_from_file(). Each MM
+-- slave has a dedicated pair of request (.ctrl) and response (.stat) IO
+-- files.
+-- The mmf_file_create() creates the .ctrl file and mmf_mm_from_file() reads
+-- it to check whether there is a WR or RD access request. For a WR request
+-- the wr_data and wr_addr are read from the .ctrl and output on the MM bus
+-- via mm_mosi. For a RD access request the rd_addr is read from the .ctrl
+-- and output on the MM bus via mm_mosi. The after the read latency the
+-- rd_data is written to the .stat file that is then created and closed.
+--
+-- wr rd _________ __________
+-- mmf_mm_bus_wr() ---> ctrl file --->| |---mm_mosi-->| |
+-- | mm_file | | MM slave |
+-- mmf_mm_bus_rd() <--- stat file <---|___\_____|<--mm_miso---|__________|
+-- rd wr \
+-- \--> loop: mmf_mm_from_file()
+--
+-- The ctrl file is created by mm_file at initialization and recreated by
+-- every call of mmf_mm_from_file().
+-- The stat file is recreated by every call of mmf_mm_bus_rd().
+--
+-- 2) Simulator access
+-- External access to the simulation is provided via a .ctrl file that
+-- supports GET_SIM_TIME and then report the NOW time via the .stat file.
+-- The simulation access is provided via a procedure mmf_poll_sim_ctrl_file()
+-- that works similar component mm_file.vhd.
+--
+-- wr rd
+-- |---> ctrl file --->|
+-- mmf_sim_get_now()| |mmf_poll_sim_ctrl_file()
+-- |<--- stat file <---| \
+-- rd wr \
+-- \--> loop: mmf_sim_ctrl_from_file()
+--
+-- The ctrl file is created by mmf_poll_sim_ctrl_file at initialization and
+-- recreated by every call of mmf_sim_ctrl_from_file().
+-- The stat file is recreated by every call of mmf_sim_get_now().
+--
+-- A) External control by a Python script
+-- A Python script can issue requests via the .ctrl files to control the
+-- simulation and read the .stat files. This models the MM access via a
+-- Monitoring and Control protocol via 1GbE.
+--
+-- Internal procedures:
+-- . mmf_file_create(filename: IN STRING);
+-- . mmf_mm_from_file(SIGNAL mm_clk : IN STD_LOGIC;
+-- . mmf_sim_ctrl_from_file(rd_filename: IN STRING;
+--
+-- External procedures (used in a VHDL design to provide access to the MM
+-- slaves and simulation via file IO):
+-- . mm_file.vhd --> instead of a procedure MM slave file IO uses a component
+-- . mmf_poll_sim_ctrl_file()
+--
+-- B) External control by a VHDL process --> see tb_mm_file.vhd
+-- Instead of a Python script the file IO access to the MM slaves can also
+-- be used in a pure VHDL testbench. This is useful when the MM slave bus
+-- signals (mm_mosi, mm_miso) are not available on the entity of the DUT
+-- (device under test), which is typically the case when a complete FPGA
+-- design needs to be simulated.
+--
+-- Internal procedures:
+-- . mmf_wait_for_file_status()
+-- . mmf_wait_for_file_empty()
+-- . mmf_wait_for_file_not_empty()
+--
+-- External procedures (used in a VHDL test bench to provide access to the
+-- MM slaves in a DUT VHDL design and simulation via file IO):
+-- . mmf_mm_bus_wr()
+-- . mmf_mm_bus_rd()
+-- . mmf_sim_get_now()
+--
+-- External function to create unique sim.ctrl/sim.stat filename per test bench in a multi tb
+-- . mmf_slave_prefix()
+--
+-- Remarks:
+-- . The timing of the MM access in mmf_mm_bus_wr() and mmf_mm_bus_rd() and the
+-- simulation access in mmf_sim_get_now() is not critical. The timing of the first
+-- access depends on the tb. Due to falling_edge(mm_clk) in mmf_wait_for_file_*()
+-- all subsequent accesses will start at falling_edge(mm_clk)
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE std.textio.ALL;
+USE IEEE.std_logic_textio.ALL;
+USE common_lib.common_str_pkg.ALL;
+
+PACKAGE mm_file_pkg IS
+
+ -- Constants used by mm_file.vhd
+ CONSTANT c_mmf_mm_clk_period : TIME := 100 ps; -- Default mm_clk period in simulation. Set much faster than DP clock to speed up
+ -- simulation of MM access. Without file IO throttling 100 ps is a good balance
+ -- between simulation speed and file IO rate.
+ CONSTANT c_mmf_mm_timeout : TIME := 1000 ns; -- Default MM file IO timeout period. Set large enough to account for MM-DP clock
+ -- domain crossing delays. Use 0 ns to disable file IO throttling, to have file IO
+ -- at the mm_clk rate.
+ CONSTANT c_mmf_mm_pause : TIME := 100 ns; -- Default MM file IO pause period after timeout. Balance between file IO rate
+ -- reduction and responsiveness to new MM access.
+
+ -- Procedure to (re)create empty file
+ PROCEDURE mmf_file_create(filename: IN STRING);
+
+ -- Procedure to perform an MM access from file
+ PROCEDURE mmf_mm_from_file(SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_rst : IN STD_LOGIC;
+ SIGNAL mm_mosi : OUT t_mem_mosi;
+ SIGNAL mm_miso : IN t_mem_miso;
+ rd_filename: IN STRING;
+ wr_filename: IN STRING;
+ rd_latency: IN NATURAL);
+
+ -- Procedure to process a simulation status request from the .ctrl file and provide response via the .stat file
+ PROCEDURE mmf_sim_ctrl_from_file(rd_filename: IN STRING;
+ wr_filename: IN STRING);
+
+ -- Procedure to poll the simulation status
+ PROCEDURE mmf_poll_sim_ctrl_file(rd_file_name: IN STRING;
+ wr_file_name: IN STRING);
+
+ -- Procedure to poll the simulation status
+ PROCEDURE mmf_poll_sim_ctrl_file(SIGNAL mm_clk : IN STD_LOGIC;
+ rd_file_name: IN STRING;
+ wr_file_name: IN STRING);
+
+ -- Procedures that keep reading the file until it has been made empty or not empty by some other program,
+ -- to ensure the file is ready for a new write access
+ PROCEDURE mmf_wait_for_file_status(rd_filename : IN STRING; -- file name with extension
+ exit_on_empty : IN BOOLEAN;
+ SIGNAL mm_clk : IN STD_LOGIC);
+
+ PROCEDURE mmf_wait_for_file_empty(rd_filename : IN STRING; -- file name with extension
+ SIGNAL mm_clk : IN STD_LOGIC);
+ PROCEDURE mmf_wait_for_file_not_empty(rd_filename : IN STRING; -- file name with extension
+ SIGNAL mm_clk : IN STD_LOGIC);
+
+ -- Procedure to issue a write access via the MM request .ctrl file
+ PROCEDURE mmf_mm_bus_wr(filename : IN STRING; -- file name without extension
+ wr_addr : IN INTEGER; -- use integer to support full 32 bit range
+ wr_data : IN INTEGER;
+ SIGNAL mm_clk : IN STD_LOGIC);
+
+ -- Procedure to issue a read access via the MM request .ctrl file and get the read data from the MM response file
+ PROCEDURE mmf_mm_bus_rd(filename : IN STRING; -- file name without extension
+ rd_latency : IN NATURAL;
+ rd_addr : IN INTEGER; -- use integer to support full 32 bit range
+ SIGNAL rd_data : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL mm_clk : IN STD_LOGIC);
+ -- . rd_latency = 1
+ PROCEDURE mmf_mm_bus_rd(filename : IN STRING;
+ rd_addr : IN INTEGER;
+ SIGNAL rd_data : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL mm_clk : IN STD_LOGIC);
+
+ -- Procedure that reads the rd_data every rd_interval until has the specified rd_value, the proc arguments can be understood as a sentence
+ PROCEDURE mmf_mm_wait_until_value(filename : IN STRING; -- file name without extension
+ rd_addr : IN INTEGER;
+ c_representation : IN STRING; -- treat rd_data as "SIGNED" or "UNSIGNED" 32 bit word
+ SIGNAL rd_data : INOUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ c_condition : IN STRING; -- ">", ">=", "=", "<=", "<", "/="
+ c_rd_value : IN INTEGER;
+ c_rd_interval : IN TIME;
+ SIGNAL mm_clk : IN STD_LOGIC);
+
+ -- Procedure to get NOW via simulator status
+ PROCEDURE mmf_sim_get_now(filename : IN STRING; -- file name without extension
+ SIGNAL rd_now : OUT STRING;
+ SIGNAL mm_clk : IN STD_LOGIC);
+
+ -- Functions to create prefixes for the mmf file filename
+ FUNCTION mmf_prefix(name : STRING; index : NATURAL) RETURN STRING; -- generic prefix name with index to be used for a file IO filename
+ FUNCTION mmf_tb_prefix(tb : INTEGER) RETURN STRING; -- fixed test bench prefix with index tb to allow file IO with multi tb
+ FUNCTION mmf_subrack_prefix(subrack : INTEGER) RETURN STRING; -- fixed subrack prefix with index subrack to allow file IO with multi subracks that use same unb numbers
+
+ -- Functions to create mmf file prefix that is unique per slave, for increasing number of hierarchy levels:
+ -- . return "filepath/s0_i0_"
+ -- . return "filepath/s0_i0_s1_i1_"
+ -- . return "filepath/s0_i0_s1_i1_s2_i2_"
+ -- . return "filepath/s0_i0_s1_i1_s2_i2_s3_i3_"
+ -- . return "filepath/s0_i0_s1_i1_s2_i2_s3_i3_s4_i4_"
+ FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL) RETURN STRING;
+ FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL) RETURN STRING;
+ FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL) RETURN STRING;
+ FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL) RETURN STRING;
+ FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL; s4 : STRING; i4 : NATURAL) RETURN STRING;
+
+ CONSTANT c_mmf_local_dir_path : STRING := "mmfiles/"; -- local directory in project file build directory
+ FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL) RETURN STRING;
+ FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL) RETURN STRING;
+ FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL) RETURN STRING;
+ FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL) RETURN STRING;
+ FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL; s4 : STRING; i4 : NATURAL) RETURN STRING;
+
+ ----------------------------------------------------------------------------
+ -- Declare mm_file component to support positional generic and port mapping of many instances in a TB
+ ----------------------------------------------------------------------------
+ COMPONENT mm_file
+ GENERIC(
+ g_file_prefix : STRING;
+ g_file_enable : STD_LOGIC := '1';
+ g_mm_rd_latency : NATURAL := 2;
+ g_mm_timeout : TIME := c_mmf_mm_timeout;
+ g_mm_pause : TIME := c_mmf_mm_pause
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ mm_master_out : OUT t_mem_mosi;
+ mm_master_in : IN t_mem_miso
+ );
+ END COMPONENT;
+
+END mm_file_pkg;
+
+PACKAGE BODY mm_file_pkg IS
+
+ PROCEDURE mmf_file_create(filename: IN STRING) IS
+ FILE created_file : TEXT OPEN write_mode IS filename;
+ BEGIN
+ -- Write the file with nothing in it
+ write(created_file, "");
+ END;
+
+ PROCEDURE mmf_mm_from_file(SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_rst : IN STD_LOGIC;
+ SIGNAL mm_mosi : OUT t_mem_mosi;
+ SIGNAL mm_miso : IN t_mem_miso;
+ rd_filename: IN STRING;
+ wr_filename: IN STRING;
+ rd_latency: IN NATURAL) IS
+ FILE rd_file : TEXT;
+ FILE wr_file : TEXT;
+
+ VARIABLE open_status_rd: file_open_status;
+ VARIABLE open_status_wr: file_open_status;
+
+ VARIABLE rd_line : LINE;
+ VARIABLE wr_line : LINE;
+
+ -- Note: Both the address and the data are interpreted as 32-bit data!
+ -- This means one has to use leading zeros in the file when either is
+ -- less than 8 hex characters, e.g.:
+ -- (address) 0000000A
+ -- (data) DEADBEEF
+ -- ...as a hex address 'A' would fit in only 4 bits, causing an error in hread().
+ VARIABLE v_addr_slv : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ VARIABLE v_data_slv : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ VARIABLE v_rd_wr_str : STRING(1 TO 2); -- Contains 'RD' or 'WR'
+
+ BEGIN
+
+ proc_common_wait_until_low(mm_clk, mm_rst);
+
+ -- We have to open the file explicitely so we can check the status
+ file_open(open_status_rd, rd_file, rd_filename, read_mode);
+
+ -- open_status may throw an error if the file is being written to by some other program
+ IF open_status_rd=open_ok THEN
+
+ IF NOT endfile(rd_file) THEN
+ -- The file is not empty: process its contents
+
+ -- Read a line from it, first line indicates RD or WR
+ readline(rd_file, rd_line);
+ read(rd_line, v_rd_wr_str);
+
+ -- The second line represents the address offset:
+ readline(rd_file, rd_line);
+ hread(rd_line, v_addr_slv); -- read the string as HEX and assign to SLV.
+
+ -- Write only: The third line contains the data to write:
+ IF v_rd_wr_str="WR" THEN
+ readline(rd_file, rd_line);
+ hread(rd_line, v_data_slv); -- read the string as HEX and assign to SLV.
+ END IF;
+
+ -- We're done reading MM request from the .ctrl file.
+ -- Clear the .ctrl file by closing and recreating it, because we don't want to do the same
+ -- MM request again the next time this procedure is called.
+ file_close(rd_file);
+ mmf_file_create(rd_filename);
+
+ -- Execute the MM request to the MM slave
+ IF v_rd_wr_str="WR" THEN
+ print_str("[" & time_to_str(now) & "] " & rd_filename & ": Writing 0x" & slv_to_hex(v_data_slv) & " to address 0x" & slv_to_hex(v_addr_slv));
+ -- Treat 32 bit hex data from file as 32 bit VHDL INTEGER, so need to use signed TO_SINT() to avoid out of NATURAL range
+ -- warning in simulation due to '1' sign bit, because unsigned VHDL NATURAL only fits 31 bits
+ proc_mem_mm_bus_wr(TO_UINT(v_addr_slv), TO_SINT(v_data_slv), mm_clk, mm_miso, mm_mosi);
+
+ ELSIF v_rd_wr_str="RD" THEN
+ proc_mem_mm_bus_rd(TO_UINT(v_addr_slv), mm_clk, mm_miso, mm_mosi);
+ IF rd_latency>0 THEN
+ proc_mem_mm_bus_rd_latency(rd_latency, mm_clk);
+ END IF;
+ v_data_slv := mm_miso.rddata(31 DOWNTO 0);
+ print_str("[" & time_to_str(now) & "] " & rd_filename & ": Reading from address 0x" & slv_to_hex(v_addr_slv) & ": 0x" & slv_to_hex(v_data_slv));
+
+ -- Write the RD response read data to the .stat file
+ file_open(open_status_wr, wr_file, wr_filename, write_mode);
+ hwrite(wr_line, v_data_slv);
+ writeline(wr_file, wr_line);
+ file_close(wr_file);
+ END IF;
+
+ ELSE
+ -- Nothing to process; wait one MM clock cycle.
+ proc_common_wait_some_cycles(mm_clk, 1);
+ END IF;
+
+ ELSE
+ REPORT "mmf_mm_from_file() could not open " & rd_filename & " at " & time_to_str(now) SEVERITY NOTE;
+ -- Try again next time; wait one MM clock cycle.
+ proc_common_wait_some_cycles(mm_clk, 1);
+ END IF;
+
+ -- The END implicitely close the rd_file, if still necessary.
+ END;
+
+
+ PROCEDURE mmf_sim_ctrl_from_file(rd_filename: IN STRING;
+ wr_filename: IN STRING) IS
+
+ FILE rd_file : TEXT;
+ FILE wr_file : TEXT;
+
+ VARIABLE open_status_rd: file_open_status;
+ VARIABLE open_status_wr: file_open_status;
+
+ VARIABLE rd_line : LINE;
+ VARIABLE wr_line : LINE;
+
+ VARIABLE v_rd_wr_str : STRING(1 TO 12); -- "GET_SIM_TIME"
+
+ BEGIN
+
+ -- We have to open the file explicitely so we can check the status
+ file_open(open_status_rd, rd_file, rd_filename, read_mode);
+
+ -- open_status may throw an error if the file is being written to by some other program
+ IF open_status_rd=open_ok THEN
+
+ IF NOT endfile(rd_file) THEN
+ -- The file is not empty: process its contents
+
+ -- Read a line from it, interpret the simulation request
+ readline(rd_file, rd_line);
+ read(rd_line, v_rd_wr_str);
+
+ -- We're done reading this simulation request .ctrl file. Clear the file by closing and recreating it.
+ file_close(rd_file);
+ mmf_file_create(rd_filename);
+
+ -- Execute the simulation request
+ IF v_rd_wr_str="GET_SIM_TIME" THEN
+ -- Write the GET_SIM_TIME response time NOW to the .stat file
+ file_open(open_status_wr, wr_file, wr_filename, write_mode);
+ write(wr_line, time_to_str(now));
+ writeline(wr_file, wr_line);
+ file_close(wr_file);
+ END IF;
+
+ ELSE
+ -- Nothing to process; wait in procedure mmf_poll_sim_ctrl_file
+ NULL;
+ END IF;
+
+ ELSE
+ REPORT "mmf_mm_from_file() could not open " & rd_filename & " at " & time_to_str(now) SEVERITY NOTE;
+ -- Try again next time; wait in procedure mmf_poll_sim_ctrl_file
+ END IF;
+
+ -- The END implicitely close the rd_file, if still necessary.
+ END;
+
+
+ PROCEDURE mmf_poll_sim_ctrl_file(rd_file_name: IN STRING; wr_file_name : IN STRING) IS
+ BEGIN
+ -- Create the ctrl file that we're going to read from
+ print_str("[" & time_to_str(now) & "] " & rd_file_name & ": Created" );
+ mmf_file_create(rd_file_name);
+
+ WHILE TRUE LOOP
+ mmf_sim_ctrl_from_file(rd_file_name, wr_file_name);
+ WAIT FOR 1 ns;
+ END LOOP;
+
+ END;
+
+
+ PROCEDURE mmf_poll_sim_ctrl_file(SIGNAL mm_clk : IN STD_LOGIC;
+ rd_file_name: IN STRING; wr_file_name : IN STRING) IS
+ BEGIN
+ -- Create the ctrl file that we're going to read from
+ print_str("[" & time_to_str(now) & "] " & rd_file_name & ": Created" );
+ mmf_file_create(rd_file_name);
+
+ WHILE TRUE LOOP
+ mmf_sim_ctrl_from_file(rd_file_name, wr_file_name);
+ proc_common_wait_some_cycles(mm_clk, 1);
+ END LOOP;
+
+ END;
+
+
+ PROCEDURE mmf_wait_for_file_status(rd_filename : IN STRING; -- file name with extension
+ exit_on_empty : IN BOOLEAN;
+ SIGNAL mm_clk : IN STD_LOGIC) IS
+ FILE rd_file : TEXT;
+ VARIABLE open_status_rd : file_open_status;
+ VARIABLE v_endfile : BOOLEAN;
+ BEGIN
+ -- Check on falling_edge(mm_clk) because mmf_mm_from_file() operates on rising_edge(mm_clk)
+ -- Note: In fact the file IO also works fine when rising_edge() is used, but then
+ -- tb_tb_mm_file.vhd takes about 1% more mm_clk cycles
+ WAIT UNTIL falling_edge(mm_clk);
+
+ -- Keep reading the file until it has become empty by some other program
+ WHILE TRUE LOOP
+ -- Open the file in read mode to check whether it is empty
+ file_open(open_status_rd, rd_file, rd_filename, read_mode);
+ -- open_status may throw an error if the file is being written to by some other program
+ IF open_status_rd=open_ok THEN
+ v_endfile := endfile(rd_file);
+ file_close(rd_file);
+ IF exit_on_empty THEN
+ IF v_endfile THEN
+ -- The file is empty; continue
+ EXIT;
+ ELSE
+ -- The file is not empty; wait one MM clock cycle.
+ WAIT UNTIL falling_edge(mm_clk);
+ END IF;
+ ELSE
+ IF v_endfile THEN
+ -- The file is empty; wait one MM clock cycle.
+ WAIT UNTIL falling_edge(mm_clk);
+ ELSE
+ -- The file is not empty; continue
+ EXIT;
+ END IF;
+ END IF;
+ ELSE
+ REPORT "mmf_wait_for_file_status() could not open " & rd_filename & " at " & time_to_str(now) SEVERITY NOTE;
+ WAIT UNTIL falling_edge(mm_clk);
+ END IF;
+ END LOOP;
+ -- The END implicitely close the file, if still necessary.
+ END;
+
+ PROCEDURE mmf_wait_for_file_empty(rd_filename : IN STRING; -- file name with extension
+ SIGNAL mm_clk : IN STD_LOGIC) IS
+ BEGIN
+ mmf_wait_for_file_status(rd_filename, TRUE, mm_clk);
+ END;
+
+ PROCEDURE mmf_wait_for_file_not_empty(rd_filename : IN STRING; -- file name with extension
+ SIGNAL mm_clk : IN STD_LOGIC) IS
+ BEGIN
+ mmf_wait_for_file_status(rd_filename, FALSE, mm_clk);
+ END;
+
+ PROCEDURE mmf_mm_bus_wr(filename : IN STRING; -- file name without extension
+ wr_addr : IN INTEGER; -- use integer to support full 32 bit range
+ wr_data : IN INTEGER;
+ SIGNAL mm_clk : IN STD_LOGIC) IS
+ CONSTANT ctrl_filename : STRING := filename & ".ctrl";
+ FILE ctrl_file : TEXT;
+ VARIABLE open_status_wr : file_open_status;
+ VARIABLE wr_line : LINE;
+
+ BEGIN
+ -- Write MM WR access to the .ctrl file.
+ -- The MM device is ready for a new MM request, because any previous MM request has finished at
+ -- mmf_mm_bus_wr() or mmf_mm_bus_rd() procedure exit, therefore just overwrite the .ctrl file.
+ file_open(open_status_wr, ctrl_file, ctrl_filename, write_mode);
+ -- open_status may throw an error if the file is being written to by some other program
+ IF open_status_wr=open_ok THEN
+ write(wr_line, STRING'("WR"));
+ writeline(ctrl_file, wr_line);
+ hwrite(wr_line, TO_SVEC(wr_addr, c_word_w));
+ writeline(ctrl_file, wr_line);
+ hwrite(wr_line, TO_SVEC(wr_data, c_word_w));
+ writeline(ctrl_file, wr_line);
+ file_close(ctrl_file);
+ ELSE
+ REPORT "mmf_mm_bus_wr() could not open " & ctrl_filename & " at " & time_to_str(now) SEVERITY NOTE;
+ END IF;
+
+ -- Prepare for next MM request
+ -- Keep reading the .ctrl file until it is empty, to ensure that the MM device is ready for a new MM request
+ mmf_wait_for_file_empty(ctrl_filename, mm_clk);
+
+ -- The END implicitely close the ctrl_file, if still necessary.
+ END;
+
+ PROCEDURE mmf_mm_bus_rd(filename : IN STRING; -- file name without extension
+ rd_latency : IN NATURAL;
+ rd_addr : IN INTEGER; -- use integer to support full 32 bit range
+ SIGNAL rd_data : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL mm_clk : IN STD_LOGIC) IS
+ CONSTANT ctrl_filename : STRING := filename & ".ctrl";
+ CONSTANT stat_filename : STRING := filename & ".stat";
+ FILE ctrl_file : TEXT;
+ FILE stat_file : TEXT;
+ VARIABLE open_status_wr : file_open_status;
+ VARIABLE open_status_rd : file_open_status;
+ VARIABLE wr_line : LINE;
+ VARIABLE rd_line : LINE;
+ VARIABLE v_rd_data : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ BEGIN
+ -- Clear the .stat file by recreating it, because we don't want to do read old file data again
+ mmf_file_create(stat_filename);
+
+ -- Write MM RD access to the .ctrl file.
+ -- The MM device is ready for a new MM request, because any previous MM request has finished at
+ -- mmf_mm_bus_wr() or mmf_mm_bus_rd() procedure exit, therefore just overwrite the .ctrl file.
+ file_open(open_status_wr, ctrl_file, ctrl_filename, write_mode);
+ -- open_status may throw an error if the file is being written to by some other program
+ IF open_status_wr=open_ok THEN
+ write(wr_line, STRING'("RD"));
+ writeline(ctrl_file, wr_line);
+ hwrite(wr_line, TO_SVEC(rd_addr, c_word_w));
+ writeline(ctrl_file, wr_line);
+ file_close(ctrl_file);
+ ELSE
+ REPORT "mmf_mm_bus_rd() could not open " & ctrl_filename & " at " & time_to_str(now) SEVERITY FAILURE;
+ END IF;
+
+ -- Wait until the MM RD access has written the read data to the .stat file
+ mmf_wait_for_file_not_empty(stat_filename, mm_clk);
+
+ -- Read the MM RD access read data from the .stat file
+ file_open(open_status_rd, stat_file, stat_filename, read_mode);
+ -- open_status may throw an error if the file is being written to by some other program
+ IF open_status_rd=open_ok THEN
+ readline(stat_file, rd_line);
+ hread(rd_line, v_rd_data);
+ file_close(stat_file);
+ rd_data <= v_rd_data;
+ -- wait to ensure rd_data has got v_rd_data, otherwise rd_data still holds the old data on procedure exit
+ -- the wait should be < mm_clk period/2 to not affect the read rate
+ WAIT FOR 1 fs;
+ ELSE
+ REPORT "mmf_mm_bus_rd() could not open " & stat_filename & " at " & time_to_str(now) SEVERITY FAILURE;
+ END IF;
+
+ -- No need to prepare for next MM request, because:
+ -- . the .ctrl file must already be empty because the .stat file was there
+ -- . the .stat file will be cleared on this procedure entry
+
+ -- The END implicitely closes the files, if still necessary
+ END;
+
+ -- rd_latency = 1
+ PROCEDURE mmf_mm_bus_rd(filename : IN STRING;
+ rd_addr : IN INTEGER;
+ SIGNAL rd_data : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL mm_clk : IN STD_LOGIC) IS
+ BEGIN
+ mmf_mm_bus_rd(filename, 1, rd_addr, rd_data, mm_clk);
+ END;
+
+ PROCEDURE mmf_mm_wait_until_value(filename : IN STRING; -- file name without extension
+ rd_addr : IN INTEGER;
+ c_representation : IN STRING; -- treat rd_data as "SIGNED" or "UNSIGNED" 32 bit word
+ SIGNAL rd_data : INOUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ c_condition : IN STRING; -- ">", ">=", "=", "<=", "<", "/="
+ c_rd_value : IN INTEGER;
+ c_rd_interval : IN TIME;
+ SIGNAL mm_clk : IN STD_LOGIC) IS
+ BEGIN
+ WHILE TRUE LOOP
+ -- Read current
+ mmf_mm_bus_rd(filename, rd_addr, rd_data, mm_clk); -- only read low part
+ IF c_representation="SIGNED" THEN
+ IF c_condition=">" THEN IF TO_SINT(rd_data)> c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
+ ELSIF c_condition=">=" THEN IF TO_SINT(rd_data)>=c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
+ ELSIF c_condition="/=" THEN IF TO_SINT(rd_data)/=c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
+ ELSIF c_condition="<=" THEN IF TO_SINT(rd_data)<=c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
+ ELSIF c_condition="<" THEN IF TO_SINT(rd_data)< c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
+ ELSE IF TO_SINT(rd_data) =c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF; -- default: "="
+ END IF;
+ ELSE -- default: UNSIGED
+ IF c_condition=">" THEN IF TO_UINT(rd_data)> c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
+ ELSIF c_condition=">=" THEN IF TO_UINT(rd_data)>=c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
+ ELSIF c_condition="/=" THEN IF TO_UINT(rd_data)/=c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
+ ELSIF c_condition="<=" THEN IF TO_UINT(rd_data)<=c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
+ ELSIF c_condition="<" THEN IF TO_UINT(rd_data)< c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF;
+ ELSE IF TO_UINT(rd_data) =c_rd_value THEN EXIT; ELSE WAIT FOR c_rd_interval; END IF; -- default: "="
+ END IF;
+ END IF;
+ END LOOP;
+ END mmf_mm_wait_until_value;
+
+
+ PROCEDURE mmf_sim_get_now(filename : IN STRING; -- file name without extension
+ SIGNAL rd_now : OUT STRING;
+ SIGNAL mm_clk : IN STD_LOGIC) IS
+ CONSTANT ctrl_filename : STRING := filename & ".ctrl";
+ CONSTANT stat_filename : STRING := filename & ".stat";
+ FILE ctrl_file : TEXT;
+ FILE stat_file : TEXT;
+ VARIABLE open_status_wr : file_open_status;
+ VARIABLE open_status_rd : file_open_status;
+ VARIABLE wr_line : LINE;
+ VARIABLE rd_line : LINE;
+ VARIABLE v_rd_now : STRING(rd_now'RANGE);
+
+ BEGIN
+ -- Clear the sim.stat file by recreating it, because we don't want to do read old simulator status again
+ mmf_file_create(stat_filename);
+
+ -- Write GET_SIM_TIME to the sim.ctrl file
+ -- The simulation is ready for a new simulation status request, because any previous simulation status request has finished at
+ -- mmf_sim_get_now() procedure exit, therefore just overwrite the .ctrl file.
+ file_open(open_status_wr, ctrl_file, ctrl_filename, write_mode);
+ -- open_status may throw an error if the file is being written to by some other program
+ IF open_status_wr=open_ok THEN
+ write(wr_line, STRING'("GET_SIM_TIME"));
+ writeline(ctrl_file, wr_line);
+ file_close(ctrl_file);
+ ELSE
+ REPORT "mmf_sim_get_now() could not open " & ctrl_filename & " at " & time_to_str(now) SEVERITY FAILURE;
+ END IF;
+
+ -- Wait until the simulation has written the simulation status to the sim.stat file
+ mmf_wait_for_file_not_empty(stat_filename, mm_clk);
+
+ -- Read the GET_SIM_TIME simulation status from the .stat file
+ file_open(open_status_rd, stat_file, stat_filename, read_mode);
+ -- open_status may throw an error if the file is being written to by some other program
+ IF open_status_rd=open_ok THEN
+ readline(stat_file, rd_line);
+ read(rd_line, v_rd_now);
+ file_close(stat_file);
+ rd_now <= v_rd_now;
+ print_str("GET_SIM_TIME = " & v_rd_now & " at " & time_to_str(now));
+ ELSE
+ REPORT "mmf_sim_get_now() could not open " & stat_filename & " at " & time_to_str(now) SEVERITY FAILURE;
+ END IF;
+
+ -- No need to prepare for next simulation status request, because:
+ -- . the .ctrl file must already be empty because the .stat file was there
+ -- . the .stat file will be cleared on this procedure entry
+
+ -- The END implicitely closes the files, if still necessary
+ END;
+
+ -- Functions to create prefixes for the mmf file filename
+ FUNCTION mmf_prefix(name : STRING; index : NATURAL) RETURN STRING IS
+ BEGIN
+ RETURN name & "_" & int_to_str(index) & "_";
+ END;
+
+ FUNCTION mmf_tb_prefix(tb : INTEGER) RETURN STRING IS
+ BEGIN
+ RETURN mmf_prefix("TB", tb);
+ END;
+
+ FUNCTION mmf_subrack_prefix(subrack : INTEGER) RETURN STRING IS
+ BEGIN
+ RETURN mmf_prefix("SUBRACK", subrack);
+ END;
+
+ -- Functions to create mmf file prefix that is unique per slave, for increasing number of hierarchy levels:
+ FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL) RETURN STRING IS
+ BEGIN
+ RETURN dir_path & mmf_prefix(s0, i0);
+ END;
+
+ FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL) RETURN STRING IS
+ BEGIN
+ RETURN dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1);
+ END;
+
+ FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL) RETURN STRING IS
+ BEGIN
+ RETURN dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1) & mmf_prefix(s2, i2);
+ END;
+
+ FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL) RETURN STRING IS
+ BEGIN
+ RETURN dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1) & mmf_prefix(s2, i2) & mmf_prefix(s3, i3);
+ END;
+
+ FUNCTION mmf_slave_prefix(dir_path, s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL; s4 : STRING; i4 : NATURAL) RETURN STRING IS
+ BEGIN
+ RETURN dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1) & mmf_prefix(s2, i2) & mmf_prefix(s3, i3) & mmf_prefix(s4, i4);
+ END;
+
+ -- Use local dir_path
+ FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL) RETURN STRING IS
+ BEGIN
+ RETURN c_mmf_local_dir_path & mmf_prefix(s0, i0);
+ END;
+
+ FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL) RETURN STRING IS
+ BEGIN
+ RETURN c_mmf_local_dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1);
+ END;
+
+ FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL) RETURN STRING IS
+ BEGIN
+ RETURN c_mmf_local_dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1) & mmf_prefix(s2, i2);
+ END;
+
+ FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL) RETURN STRING IS
+ BEGIN
+ RETURN c_mmf_local_dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1) & mmf_prefix(s2, i2) & mmf_prefix(s3, i3);
+ END;
+
+ FUNCTION mmf_slave_prefix(s0 : STRING; i0 : NATURAL; s1 : STRING; i1 : NATURAL; s2 : STRING; i2 : NATURAL; s3 : STRING; i3 : NATURAL; s4 : STRING; i4 : NATURAL) RETURN STRING IS
+ BEGIN
+ RETURN c_mmf_local_dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1) & mmf_prefix(s2, i2) & mmf_prefix(s3, i3) & mmf_prefix(s4, i4);
+ END;
+
+END mm_file_pkg;
+
diff --git a/libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd b/libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fc530c0b9df5c8c0868441ba17b9344e333c7c29
--- /dev/null
+++ b/libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd
@@ -0,0 +1,138 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Provide waitrequest stimuli to model a slave with MM flow control
+-- Description:
+-- The model applies random waitrequest stimuli for a MM slave that does not
+-- need MM flow control. In this way the MM slave acts like a MM slave that
+-- does need MM flow control.
+-- * The model only controls the bus_miso.waitrequest. The other slave_miso
+-- fields are wired to the bus_miso. The bus master will act upon the
+-- waitrequest, so model can rely on that regarding the bus_mosi. However
+-- towards the MM slave that has no flow control the model has to gate the
+-- bus_mosi wr and rd with the waitrequest, so that the MM slave only gets
+-- a ram_mosi rd or wr when it was acknowledged.
+-- * When g_waitrequest = TRUE then the waitrequest model is applied to the
+-- bus_miso. Use g_waitrequest = FALSE to bypass the waitrequest model,
+-- so then bus_miso.waitrequest is fixed '0'.
+-- * The g_seed is used to initalize the random PRSG, e.g use slave instance
+-- index as g_seed to have different stimuli per instance.
+-- * The maximum number of cycles that waitrequest depends on the period of
+-- the LFSR random sequence generator and can be:
+-- . '1' for g_prsg_w mm_clk cycles
+-- . '0' for g_prsg_w-1 mm_clk cycles
+-- Remarks:
+-- . To some extend the ASSERTs check the flow control. The testbench has to
+-- verify the rddata to ensure more test coverage.
+--
+-------------------------------------------------------------------------------
+
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_lfsr_sequences_pkg.ALL;
+
+ENTITY mm_waitrequest_model IS
+ GENERIC (
+ g_waitrequest : BOOLEAN;
+ g_seed : NATURAL := 0;
+ g_prsg_w : NATURAL := 16
+ );
+ PORT (
+ mm_clk : IN STD_LOGIC;
+ bus_mosi : IN t_mem_mosi;
+ bus_miso : OUT t_mem_miso;
+ slave_mosi : OUT t_mem_mosi;
+ slave_miso : IN t_mem_miso
+ );
+END mm_waitrequest_model;
+
+ARCHITECTURE rtl OF mm_waitrequest_model IS
+
+ CONSTANT c_prsg_init : NATURAL := g_seed + 1; -- PRSG init must be > 0
+
+ SIGNAL prsg : STD_LOGIC_VECTOR(g_prsg_w-1 DOWNTO 0) := TO_UVEC(c_prsg_init, g_prsg_w);
+
+ SIGNAL waitrequest : STD_LOGIC;
+
+ SIGNAL prev_bus_mosi : t_mem_mosi;
+ SIGNAL prev_waitrequest : STD_LOGIC;
+
+BEGIN
+
+ no_waitrequest : IF g_waitrequest=FALSE GENERATE
+ slave_mosi <= bus_mosi;
+
+ p_waitrequest : PROCESS(slave_miso)
+ BEGIN
+ bus_miso <= slave_miso;
+ bus_miso.waitrequest <= '0';
+ END PROCESS;
+ END GENERATE;
+
+ gen_waitrequest : IF g_waitrequest=TRUE GENERATE
+ -- Model MM flow control using random waitrequest
+ p_reg : PROCESS(mm_clk)
+ BEGIN
+ IF rising_edge(mm_clk) THEN
+ -- random waitrequest flow control
+ prsg <= func_common_random(prsg);
+ -- check MM access
+ prev_bus_mosi <= bus_mosi;
+ prev_waitrequest <= waitrequest;
+ END IF;
+ END PROCESS;
+
+ waitrequest <= prsg(0);
+
+ -- Apply MM flow control to bus master using waitrequest
+ p_bus_miso : PROCESS(waitrequest, slave_miso)
+ BEGIN
+ bus_miso <= slave_miso;
+ bus_miso.waitrequest <= waitrequest;
+ END PROCESS;
+
+ -- Gate MM rd and wr access to RAM slave that has no flow control
+ p_slave_mosi : PROCESS(waitrequest, bus_mosi)
+ BEGIN
+ slave_mosi <= bus_mosi;
+ slave_mosi.wr <= bus_mosi.wr AND NOT waitrequest;
+ slave_mosi.rd <= bus_mosi.rd AND NOT waitrequest;
+ END PROCESS;
+
+ -- Verify that MM access is not removed before it is acknowledged by waitrequest
+ p_verify : PROCESS(bus_mosi, prev_bus_mosi, prev_waitrequest)
+ BEGIN
+ IF prev_waitrequest = '1' THEN
+ IF prev_bus_mosi.wr = '1' AND bus_mosi.wr = '0' THEN REPORT "Aborted slave write." SEVERITY ERROR; END IF;
+ IF prev_bus_mosi.rd = '1' AND bus_mosi.rd = '0' THEN REPORT "Aborted slave read." SEVERITY ERROR; END IF;
+ IF prev_bus_mosi.wr = '1' AND bus_mosi.address /= prev_bus_mosi.address THEN REPORT "Address change during pending slave write." SEVERITY ERROR; END IF;
+ IF prev_bus_mosi.rd = '1' AND bus_mosi.address /= prev_bus_mosi.address THEN REPORT "Address change during pending slave read." SEVERITY ERROR; END IF;
+ END IF;
+ END PROCESS;
+
+ END GENERATE;
+
+END rtl;
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd b/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..44cb20799724a60185b5ad273e029245b8f3ee52
--- /dev/null
+++ b/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
@@ -0,0 +1,249 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Test bench for mm_bus.vhd
+-- Remark:
+-- . This test bench covers:
+-- . g_nof_slaves >= 1
+-- . g_waitrequest for g_pipeline_miso_wait = FALSE
+-- . g_pipeline_mosi
+-- . g_pipeline_miso_rdval
+-- . g_pipeline_miso_wait = FALSE
+-- . g_rd_latency >= 1 (using 0 is supported by mm_bus, but not by
+-- the common_ram_r_w in u_slaves)
+-- . same g_rd_latency for all slaves
+-- . same g_width for all slaves
+-- . regular base address spacing of slaves in c_base_arr
+-- . The mm_bus.vhd can support a list of arbitrary width slaves, but
+-- this tb_mm_bus test bench uses an array of fixed width slaves.
+-- It is considered sufficient coverage for this tb and the corresponding
+-- multi tb_tb to also only support regular c_base_arr, same g_rd_latency,
+-- and same g_width for all slaves. The tb_mm_master_mux also uses a
+-- mm_bus.vhd and the tb_mm_master_mux does uses an array of
+-- arbitrary width slaves.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+
+ENTITY tb_mm_bus IS
+ GENERIC (
+ g_nof_slaves : POSITIVE := 1; -- Number of slave memory interfaces on the MM bus array.
+ g_base_offset : NATURAL := 0; -- Address of first slave on the MM bus
+ g_width_w : POSITIVE := 4; -- Address width of each slave memory in the MM bus array.
+ g_rd_latency : NATURAL := 1; -- Read latency of the slaves
+ g_waitrequest : BOOLEAN := FALSE; -- When TRUE model waitrequest by MM slaves, else fixed '0'
+ g_pipeline_mosi : BOOLEAN := FALSE;
+ g_pipeline_miso_rdval : BOOLEAN := FALSE;
+ g_pipeline_miso_wait : BOOLEAN := FALSE
+ );
+END tb_mm_bus;
+
+-- Usage:
+-- > as 10
+-- > run -all
+
+
+ARCHITECTURE tb OF tb_mm_bus IS
+
+ CONSTANT mm_clk_period : TIME := 10 ns;
+
+ CONSTANT c_repeat : NATURAL := 10;--sel_a_b(g_waitrequest, 10, 2); -- repeat 2 for deterministic, more often for random
+ CONSTANT c_slave_span : NATURAL := 2**g_width_w;
+ CONSTANT c_base_arr : t_nat_natural_arr := array_init(g_base_offset, g_nof_slaves, c_slave_span); -- Address base per slave
+ CONSTANT c_width_arr : t_nat_natural_arr := array_init( g_width_w, g_nof_slaves); -- Address width per slave
+ CONSTANT c_rd_latency_arr : t_nat_natural_arr := array_init( g_rd_latency, g_nof_slaves); -- Read latency per slave
+ CONSTANT c_slave_enable_arr: t_nat_boolean_arr := array_init( TRUE, g_nof_slaves); -- TRUE for connected slaves
+ CONSTANT c_waitrequest_arr : t_nat_boolean_arr := array_init(g_waitrequest, g_nof_slaves); -- Flow control per slave
+
+ CONSTANT c_bus_pipelining : BOOLEAN := g_pipeline_mosi OR g_pipeline_miso_rdval OR g_pipeline_miso_wait;
+ CONSTANT c_pipeline_mosi : NATURAL := sel_a_b(g_pipeline_mosi, 1, 0);
+ CONSTANT c_pipeline_miso_rdval : NATURAL := sel_a_b(g_pipeline_miso_rdval, 1, 0);
+ CONSTANT c_pipeline_miso_wait : NATURAL := sel_a_b(g_pipeline_miso_wait, 1, 0);
+ CONSTANT c_read_latency : NATURAL := c_pipeline_mosi + g_rd_latency + c_pipeline_miso_rdval;
+
+ CONSTANT c_data_w : NATURAL := 32;
+ CONSTANT c_test_ram : t_c_mem := (latency => g_rd_latency,
+ adr_w => g_width_w,
+ dat_w => c_data_w,
+ nof_dat => c_slave_span,
+ init_sl => '0');
+ SIGNAL mm_rst : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC := '1';
+ SIGNAL tb_end : STD_LOGIC;
+
+ SIGNAL cnt_rd : NATURAL := 0;
+ SIGNAL cnt_rdval : NATURAL := 0;
+
+ -- MM bus
+ SIGNAL master_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL master_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL slave_mosi_arr : t_mem_mosi_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_mosi_rst);
+ SIGNAL slave_miso_arr : t_mem_miso_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_miso_rst);
+ SIGNAL ram_mosi_arr : t_mem_mosi_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_mosi_rst);
+ SIGNAL ram_miso_arr : t_mem_miso_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_miso_rst);
+
+ -- Debug signals for monitoring in simulation Wave window
+ SIGNAL dbg_c_base_arr : t_nat_natural_arr(0 TO g_nof_slaves-1) := c_base_arr;
+ SIGNAL dbg_c_width_arr : t_nat_natural_arr(0 TO g_nof_slaves-1) := c_width_arr;
+ SIGNAL dbg_c_rd_latency_arr : t_nat_natural_arr(0 TO g_nof_slaves-1) := c_rd_latency_arr;
+
+BEGIN
+
+ mm_clk <= NOT mm_clk OR tb_end AFTER mm_clk_period/2;
+ mm_rst <= '1', '0' AFTER mm_clk_period*5;
+
+ -----------------------------------------------------------------------------
+ -- Write stimuli and readback to verify
+ -----------------------------------------------------------------------------
+ p_stimuli : PROCESS
+ VARIABLE v_wrdata : INTEGER; -- write data
+ BEGIN
+ tb_end <= '0';
+ master_mosi <= c_mem_mosi_rst;
+
+ -- Wait until reset is released
+ proc_common_wait_until_low(mm_clk, mm_rst);
+ proc_common_wait_some_cycles(mm_clk, 10);
+
+ -- Repeat twice to have wr all, rd all, wr all, rd all
+ v_wrdata := 0;
+ FOR vR IN 0 TO c_repeat-1 LOOP
+ -- Write the whole memory range
+ FOR vI IN 0 TO g_nof_slaves-1 LOOP
+ FOR vJ IN 0 TO c_slave_span-1 LOOP
+ proc_mem_mm_bus_wr(g_base_offset + vI*c_slave_span + vJ, v_wrdata, mm_clk, master_miso, master_mosi);
+ v_wrdata := v_wrdata + 1;
+ END LOOP;
+ proc_common_wait_some_cycles(mm_clk, 10);
+ END LOOP;
+
+ -- Read back the whole range and check if data is as expected
+ FOR vI IN 0 TO g_nof_slaves-1 LOOP
+ FOR vJ IN 0 TO c_slave_span-1 LOOP
+ proc_mem_mm_bus_rd(g_base_offset + vI*c_slave_span + vJ, mm_clk, master_miso, master_mosi);
+ --proc_common_wait_some_cycles(mm_clk, c_read_latency); -- not needed, see p_verify
+ cnt_rd <= cnt_rd + 1;
+ END LOOP;
+ proc_common_wait_some_cycles(mm_clk, 10);
+ END LOOP;
+ END LOOP;
+
+ proc_common_wait_some_cycles(mm_clk, 10);
+
+ -- Verify that test has indeed ran
+ WAIT FOR 1 ns; -- wait 1 ns to ensure that assert report appears at end of transcript log
+ ASSERT cnt_rdval = cnt_rd AND cnt_rdval > 0 REPORT "Wrong number of rdval" SEVERITY ERROR;
+
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ -- Use miso.rdval to know when to verify the rddata, rather than to wait for a fixed c_read_latency after
+ -- the mosi.rd. The advantage is that then rd accesses can be done on every mm_clk, without having to
+ -- wait for the c_read_latency. In case of g_pipeline_mosi = TRUE or g_pipeline_miso_wait = TRUE it is
+ -- even essential to use rdval, because then the latency between rd and rdval can become larger than
+ -- c_read_latency and even variable (in case of g_waitrequest = TRUE). The disadvantage is that the MM
+ -- slave must support rdval, but that is ensured by mm_slave_enable.
+ p_verify : PROCESS
+ VARIABLE v_expdata : INTEGER := 0; -- expected data
+ VARIABLE v_rddata : INTEGER; -- read data
+ BEGIN
+ WAIT UNTIL rising_edge(mm_clk);
+ IF master_miso.rdval = '1' THEN
+ cnt_rdval <= cnt_rdval + 1;
+ v_rddata := TO_UINT(master_miso.rddata(c_data_w-1 DOWNTO 0));
+ IF v_rddata /= v_expdata THEN
+ REPORT "Error! Readvalue is not as expected" SEVERITY ERROR;
+ END IF;
+ v_expdata := v_expdata + 1;
+ END IF;
+ END PROCESS;
+
+ -----------------------------------------------------------------------------
+ -- The MM bus
+ -----------------------------------------------------------------------------
+ u_mm_bus: ENTITY work.mm_bus
+ GENERIC MAP (
+ g_nof_slaves => g_nof_slaves,
+ g_base_arr => c_base_arr,
+ g_width_arr => c_width_arr,
+ g_rd_latency_arr => c_rd_latency_arr,
+ g_slave_enable_arr => c_slave_enable_arr,
+ g_waitrequest_arr => c_waitrequest_arr,
+ g_pipeline_mosi => g_pipeline_mosi,
+ g_pipeline_miso_rdval => g_pipeline_miso_rdval,
+ g_pipeline_miso_wait => g_pipeline_miso_wait
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ master_mosi => master_mosi,
+ master_miso => master_miso,
+ slave_mosi_arr => slave_mosi_arr,
+ slave_miso_arr => slave_miso_arr
+ );
+
+ -----------------------------------------------------------------------------
+ -- Model the MM slaves
+ -----------------------------------------------------------------------------
+ gen_slaves : FOR I IN 0 TO g_nof_slaves-1 GENERATE
+ u_waitrequest_model : ENTITY work.mm_waitrequest_model
+ GENERIC MAP (
+ g_waitrequest => g_waitrequest,
+ g_seed => I
+ )
+ PORT MAP (
+ mm_clk => mm_clk,
+ bus_mosi => slave_mosi_arr(I),
+ bus_miso => slave_miso_arr(I),
+ slave_mosi => ram_mosi_arr(I),
+ slave_miso => ram_miso_arr(I)
+ );
+
+ u_ram : ENTITY common_lib.common_ram_r_w
+ GENERIC MAP (
+ g_ram => c_test_ram,
+ g_init_file => "UNUSED"
+ )
+ PORT MAP (
+ rst => mm_rst,
+ clk => mm_clk,
+ clken => '1',
+ wr_en => ram_mosi_arr(I).wr,
+ wr_adr => ram_mosi_arr(I).address(g_width_w-1 DOWNTO 0),
+ wr_dat => ram_mosi_arr(I).wrdata(c_data_w-1 DOWNTO 0),
+ rd_en => ram_mosi_arr(I).rd,
+ rd_adr => ram_mosi_arr(I).address(g_width_w-1 DOWNTO 0),
+ rd_dat => ram_miso_arr(I).rddata(c_data_w-1 DOWNTO 0),
+ rd_val => ram_miso_arr(I).rdval
+ );
+ END GENERATE;
+
+END tb;
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd b/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d3550ff0001464c698daef02c55ab19cedc57373
--- /dev/null
+++ b/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
@@ -0,0 +1,225 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Test bench for mm_master_mux.vhd and also mm_bus
+-- Description:
+-- The test bench uses mm_master_mux to access a RAM via an array of
+-- masters. The array of masters is modelled using a stimuli from a single
+-- master that get demultiplexed to the array of masters using
+-- mm_bus. The address space of the RAM is defined by the g_base_arr
+-- and g_width_arr that define the mm_bus. Therefore this test bench
+-- implicitely also verifies mm_bus.vhd.
+--
+-- stimuli master mux
+-- mosi mosi_arr mosi
+-- common -------/----> common
+-- p_stimuli ----------> mem ------/-----> mem --------> RAM
+-- bus -----/------> master
+-- / mux
+-- g_nof_masters
+-- Remark:
+-- In an application it is typical to use mm_master_mux to connect
+-- mulitple masters to multiple slabes via a mm_bus MM bus.
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+
+ENTITY tb_mm_master_mux IS
+ GENERIC (
+ g_nof_masters : POSITIVE := 2; -- Number of master memory interfaces on the MM bus array.
+ g_base_arr : t_nat_natural_arr := (0, 256); -- Address base per slave port of mm_bus
+ g_width_arr : t_nat_natural_arr := (4, 8); -- Address width per slave port of mm_bus
+ g_waitrequest : BOOLEAN := TRUE; -- When TRUE model waitrequest by the MM RAM slave, else fixed '0'
+ g_pipeline_bus_mosi : BOOLEAN := FALSE;
+ g_pipeline_bus_miso_rdval : BOOLEAN := FALSE;
+ g_pipeline_bus_miso_wait : BOOLEAN := FALSE
+ );
+END tb_mm_master_mux;
+
+-- Usage:
+-- > as 10
+-- > run -all
+
+
+ARCHITECTURE tb OF tb_mm_master_mux IS
+
+ CONSTANT mm_clk_period : TIME := 10 ns;
+
+ CONSTANT c_repeat : NATURAL := sel_a_b(g_waitrequest, 10, 2); -- repeat 2 for deterministic, more often for random
+ CONSTANT c_bus_pipeline_mosi : NATURAL := sel_a_b(g_pipeline_bus_mosi, 1, 0);
+ CONSTANT c_bus_pipeline_miso_rdval : NATURAL := sel_a_b(g_pipeline_bus_miso_rdval, 1, 0);
+ CONSTANT c_bus_pipeline_miso_wait : NATURAL := sel_a_b(g_pipeline_bus_miso_wait, 1, 0);
+ CONSTANT c_ram_rd_latency : NATURAL := 1;
+ CONSTANT c_ram_rd_latency_arr : t_nat_natural_arr := array_init(c_ram_rd_latency, g_nof_masters);
+ CONSTANT c_slave_enable_arr : t_nat_boolean_arr := array_init(TRUE, g_nof_masters);
+ CONSTANT c_waitrequest_arr : t_nat_boolean_arr := array_init(g_waitrequest, g_nof_masters);
+
+ CONSTANT c_read_latency : NATURAL := c_bus_pipeline_mosi + c_ram_rd_latency + c_bus_pipeline_miso_rdval;
+
+ CONSTANT c_addr_w : NATURAL := largest(ceil_log2(largest(g_base_arr)), largest(g_width_arr)) + 1;
+ CONSTANT c_data_w : NATURAL := 32;
+ CONSTANT c_test_ram : t_c_mem := (latency => c_ram_rd_latency,
+ adr_w => c_addr_w,
+ dat_w => c_data_w,
+ nof_dat => 2**c_addr_w,
+ init_sl => '0');
+ SIGNAL mm_rst : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC := '1';
+ SIGNAL tb_end : STD_LOGIC;
+
+ SIGNAL stimuli_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL stimuli_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL master_mosi_arr : t_mem_mosi_arr(0 TO g_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
+ SIGNAL master_miso_arr : t_mem_miso_arr(0 TO g_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
+ SIGNAL mux_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL mux_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_miso : t_mem_miso := c_mem_miso_rst;
+
+BEGIN
+
+ mm_clk <= NOT mm_clk OR tb_end AFTER mm_clk_period/2;
+ mm_rst <= '1', '0' AFTER mm_clk_period*5;
+
+ p_stimuli : PROCESS
+ VARIABLE v_base : NATURAL;
+ VARIABLE v_span : NATURAL;
+ VARIABLE v_wrdata : INTEGER; -- write data
+ VARIABLE v_rddata : INTEGER; -- read data
+ VARIABLE v_expdata : INTEGER; -- expected data
+ BEGIN
+ tb_end <= '0';
+ stimuli_mosi <= c_mem_mosi_rst;
+
+ -- Wait until reset is released
+ proc_common_wait_until_low(mm_clk, mm_rst);
+ proc_common_wait_some_cycles(mm_clk, 10);
+
+ -- Repeat twice to have wr all, rd all, wr all, rd all
+ v_wrdata := 0;
+ v_expdata := 0;
+ FOR vR IN 0 TO c_repeat-1 LOOP
+ -- Write the whole memory range
+ FOR vI IN 0 TO g_nof_masters-1 LOOP
+ v_base := g_base_arr(vI);
+ v_span := 2**g_width_arr(vI);
+ FOR vJ IN 0 TO v_span-1 LOOP
+ proc_mem_mm_bus_wr(v_base + vJ, v_wrdata, mm_clk, stimuli_miso, stimuli_mosi);
+ v_wrdata := v_wrdata + 1;
+ END LOOP;
+ END LOOP;
+
+ -- Read back the whole range and check if data is as expected
+ FOR vI IN 0 TO g_nof_masters-1 LOOP
+ v_base := g_base_arr(vI);
+ v_span := 2**g_width_arr(vI);
+ FOR vJ IN 0 TO v_span-1 LOOP
+ proc_mem_mm_bus_rd(v_base + vJ, mm_clk, stimuli_miso, stimuli_mosi);
+ proc_common_wait_some_cycles(mm_clk, c_read_latency);
+ v_rddata := TO_UINT(stimuli_miso.rddata(c_data_w-1 DOWNTO 0));
+ IF v_rddata /= v_expdata THEN
+ REPORT "Error! Readvalue is not as expected" SEVERITY ERROR;
+ END IF;
+ v_expdata := v_expdata + 1;
+ END LOOP;
+ END LOOP;
+ END LOOP;
+
+ proc_common_wait_some_cycles(mm_clk, 10);
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ -- Model multiple masters using stimuli from a single master
+ u_masters : ENTITY work.mm_bus
+ GENERIC MAP (
+ g_nof_slaves => g_nof_masters,
+ g_base_arr => g_base_arr,
+ g_width_arr => g_width_arr,
+ g_rd_latency_arr => c_ram_rd_latency_arr,
+ g_slave_enable_arr => c_slave_enable_arr,
+ g_waitrequest_arr => c_waitrequest_arr,
+ g_pipeline_mosi => g_pipeline_bus_mosi,
+ g_pipeline_miso_rdval => g_pipeline_bus_miso_rdval,
+ g_pipeline_miso_wait => g_pipeline_bus_miso_wait
+ )
+ PORT MAP (
+ mm_clk => mm_clk,
+ master_mosi => stimuli_mosi,
+ master_miso => stimuli_miso,
+ slave_mosi_arr => master_mosi_arr,
+ slave_miso_arr => master_miso_arr
+ );
+
+ -- DUT = device under test
+ u_dut: ENTITY work.mm_master_mux
+ GENERIC MAP (
+ g_nof_masters => g_nof_masters,
+ g_rd_latency_min => c_read_latency
+ )
+ PORT MAP (
+ mm_clk => mm_clk,
+ master_mosi_arr => master_mosi_arr,
+ master_miso_arr => master_miso_arr,
+ mux_mosi => mux_mosi,
+ mux_miso => mux_miso
+ );
+
+ -- Model master access to MM bus with multiple slaves using a single RAM
+ u_waitrequest_model : ENTITY work.mm_waitrequest_model
+ GENERIC MAP (
+ g_waitrequest => g_waitrequest
+ )
+ PORT MAP (
+ mm_clk => mm_clk,
+ bus_mosi => mux_mosi,
+ bus_miso => mux_miso,
+ slave_mosi => ram_mosi,
+ slave_miso => ram_miso
+ );
+
+ u_ram : ENTITY common_lib.common_ram_r_w
+ GENERIC MAP (
+ g_ram => c_test_ram,
+ g_init_file => "UNUSED"
+ )
+ PORT MAP (
+ rst => mm_rst,
+ clk => mm_clk,
+ wr_en => ram_mosi.wr,
+ wr_adr => ram_mosi.address(c_addr_w-1 DOWNTO 0),
+ wr_dat => ram_mosi.wrdata(c_data_w-1 DOWNTO 0),
+ rd_en => ram_mosi.rd,
+ rd_adr => ram_mosi.address(c_addr_w-1 DOWNTO 0),
+ rd_dat => ram_miso.rddata(c_data_w-1 DOWNTO 0),
+ rd_val => ram_miso.rdval
+ );
+
+
+END tb;
diff --git a/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd b/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e399076bb1f973284b4ed38e5a7722a0dbca39e8
--- /dev/null
+++ b/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd
@@ -0,0 +1,67 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Multi test bench for mm_bus.vhd
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+ENTITY tb_tb_mm_bus IS
+END tb_tb_mm_bus;
+
+ARCHITECTURE tb OF tb_tb_mm_bus IS
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+BEGIN
+ -- Usage:
+ -- > as 4
+ -- > run -all
+
+ -- g_nof_slaves : POSITIVE := 2; -- Number of slave memory interfaces on the MM bus array.
+ -- g_base_offset : NATURAL := 0; -- Address of first slave on the MM bus
+ -- g_width_w : POSITIVE := 4; -- Address width of each slave memory in the MM bus array.
+ -- g_rd_latency : NATURAL := 1; -- Read latency of the slaves slave
+ -- g_waitrequest : BOOLEAN := FALSE; -- When TRUE model waitrequest by MM slaves, else fixed '0'
+ -- g_pipeline_mosi : BOOLEAN := FALSE;
+ -- g_pipeline_miso_rdval : BOOLEAN := TRUE;
+ -- g_pipeline_miso_wait : BOOLEAN := FALSE
+
+ u_no_pipe : ENTITY work.tb_mm_bus GENERIC MAP (16, 0, 3, 1, FALSE, FALSE, FALSE, FALSE);
+ u_no_pipe_base_offset : ENTITY work.tb_mm_bus GENERIC MAP (16, 3*2**4, 4, 1, FALSE, FALSE, FALSE, FALSE);
+ u_pipe_mosi : ENTITY work.tb_mm_bus GENERIC MAP ( 3, 0, 4, 1, FALSE, TRUE, FALSE, FALSE);
+ u_pipe_mosi_miso_rdval : ENTITY work.tb_mm_bus GENERIC MAP ( 3, 0, 4, 1, FALSE, TRUE, TRUE, FALSE);
+ u_waitrequest_no_pipe : ENTITY work.tb_mm_bus GENERIC MAP ( 3, 0, 4, 1, TRUE, FALSE, FALSE, FALSE);
+ u_waitrequest_pipe_miso_rdval : ENTITY work.tb_mm_bus GENERIC MAP ( 3, 0, 4, 1, TRUE, FALSE, TRUE, FALSE);
+ u_waitrequest_pipe_miso_rdval2 : ENTITY work.tb_mm_bus GENERIC MAP ( 3, 0, 4, 2, TRUE, FALSE, TRUE, FALSE);
+ u_waitrequest_pipe_miso_wait : ENTITY work.tb_mm_bus GENERIC MAP ( 2, 0, 4, 1, TRUE, FALSE, FALSE, TRUE);
+ u_waitrequest_pipe_mosi_one : ENTITY work.tb_mm_bus GENERIC MAP ( 1, 0, 4, 1, TRUE, TRUE, FALSE, FALSE);
+ u_waitrequest_pipe_mosi : ENTITY work.tb_mm_bus GENERIC MAP ( 2, 0, 4, 1, TRUE, TRUE, FALSE, FALSE);
+ u_waitrequest_pipe_mosi_miso_rdval : ENTITY work.tb_mm_bus GENERIC MAP ( 2, 0, 4, 1, TRUE, TRUE, TRUE, FALSE);
+
+ -- Do not support simultaneous g_pipeline_mosi = TRUE and g_pipeline_miso_wait = TRUE, see mm_bus_pipe.vhd.
+ --u_waitrequest_pipe_mosi_miso_wait : ENTITY work.tb_mm_bus GENERIC MAP ( 2, 0, 4, 1, TRUE, TRUE, FALSE, TRUE);
+ --u_waitrequest_pipe_all : ENTITY work.tb_mm_bus GENERIC MAP ( 2, 0, 4, 1, TRUE, TRUE, TRUE, TRUE);
+
+END tb;
diff --git a/libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd b/libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..978b06ac803a73275570f583d334638ed0878a88
--- /dev/null
+++ b/libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd
@@ -0,0 +1,61 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Multi test bench for mm_master_mux.vhd
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+ENTITY tb_tb_mm_master_mux IS
+END tb_tb_mm_master_mux;
+
+ARCHITECTURE tb OF tb_tb_mm_master_mux IS
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+BEGIN
+ -- Usage:
+ -- > as 4
+ -- > run -all
+
+ -- g_nof_masters : POSITIVE := 2; -- Number of master memory interfaces on the MM bus array.
+ -- g_base_arr : t_nat_natural_arr := (0, 256); -- Address base per slave port of mm_bus
+ -- g_width_arr : t_nat_natural_arr := (4, 8); -- Address width per slave port of mm_bus
+ -- g_waitrequest : BOOLEAN := FALSE; -- When TRUE model waitrequest by the MM RAM slave, else fixed '0'
+ -- g_pipeline_bus_mosi : BOOLEAN := FALSE;
+ -- g_pipeline_bus_miso_rdval : BOOLEAN := FALSE;
+ -- g_pipeline_bus_miso_wait : BOOLEAN := FALSE
+
+ u_no_pipe : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4, 8), FALSE, FALSE, FALSE, FALSE);
+ u_pipe_mosi : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4, 8), FALSE, TRUE, FALSE, FALSE);
+ u_pipe_miso_rdval : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4, 8), FALSE, FALSE, TRUE, FALSE);
+ u_waitrequest_no_pipe : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4, 8), TRUE, FALSE, FALSE, FALSE);
+ u_waitrequest_pipe_miso_rdval : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4, 8), TRUE, FALSE, TRUE, FALSE);
+ u_waitrequest_pipe_mosi : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4, 8), TRUE, TRUE, FALSE, FALSE);
+ u_waitrequest_pipe_mosi_miso_rdval : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4, 8), TRUE, TRUE, TRUE, FALSE);
+
+ -- Do not support simultaneous g_pipeline_mosi = TRUE and g_pipeline_miso_wait = TRUE, see mm_bus_pipe.vhd.
+ --u_waitrequest_pipe_all : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4, 8), TRUE, TRUE, TRUE, TRUE);
+
+END tb;
diff --git a/libraries/io/eth/src/vhdl/eth.vhd b/libraries/io/eth/src/vhdl/eth.vhd
index 3bc629d3d421d5a28b5259d37520ea1d7f455346..04dcd650ac50b462b64b433c7cf78dc61c5e1b5b 100644
--- a/libraries/io/eth/src/vhdl/eth.vhd
+++ b/libraries/io/eth/src/vhdl/eth.vhd
@@ -638,7 +638,7 @@ BEGIN
g_sim => g_sim,
g_sim_level => g_sim_level,
g_sim_tx => TRUE,
- g_sim_rx => sel_a_b(g_sim_level=1, FALSE, TRUE) -- TX only when using fast behavioural model
+ g_sim_rx => TRUE
)
PORT MAP (
-- Clocks and reset
diff --git a/libraries/io/eth/tb/vhdl/tb_eth.vhd b/libraries/io/eth/tb/vhdl/tb_eth.vhd
index 9a8005019d277a3372d5766bd14dc1faeba66dce..22387c22d9d90beb359e0e2513ef85bd8ef065a2 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth.vhd
@@ -61,6 +61,8 @@ ENTITY tb_eth IS
GENERIC (
g_technology_dut : NATURAL := c_tech_select_default;
g_technology_lcu : NATURAL := c_tech_select_default;
+ g_sim : BOOLEAN := TRUE;
+ g_sim_level : NATURAL := 1; -- when g_sim = TRUE, then 0 = use IP; 1 = use fast serdes model
g_frm_discard_en : BOOLEAN := FALSE; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
g_flush_test_en : BOOLEAN := FALSE; -- when TRUE send many large frames to enforce flush in eth_buffer
g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
@@ -81,7 +83,7 @@ ARCHITECTURE tb OF tb_eth IS
CONSTANT sys_clk_period : TIME := 10 ns; -- 100 MHz
CONSTANT eth_clk_period : TIME := 8 ns; -- 125 MHz
- CONSTANT cable_delay : TIME := 12 ns;
+ CONSTANT cable_delay : TIME := sel_a_b(g_sim_level=0, 12 ns, 0 ns);
CONSTANT c_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
@@ -256,9 +258,11 @@ ARCHITECTURE tb OF tb_eth IS
SIGNAL lcu_tx_en : STD_LOGIC := '1';
SIGNAL lcu_tx_siso : t_dp_siso;
SIGNAL lcu_tx_sosi : t_dp_sosi;
+ SIGNAL lcu_tx_sosi_data : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL lcu_tx_mac_in : t_tech_tse_tx_mac;
SIGNAL lcu_tx_mac_out : t_tech_tse_tx_mac;
SIGNAL lcu_rx_sosi : t_dp_sosi;
+ SIGNAL lcu_rx_sosi_data : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL lcu_rx_siso : t_dp_siso;
SIGNAL lcu_rx_mac_out : t_tech_tse_rx_mac;
SIGNAL lcu_txp : STD_LOGIC;
@@ -421,6 +425,11 @@ BEGIN
------------------------------------------------------------------------------
-- LCU
------------------------------------------------------------------------------
+
+ -- Debug signal to more easily view sosi.data in Wave Window
+ lcu_tx_sosi_data <= lcu_tx_sosi.data(c_word_w-1 DOWNTO 0);
+ lcu_rx_sosi_data <= lcu_rx_sosi.data(c_word_w-1 DOWNTO 0);
+
p_lcu_setup : PROCESS
BEGIN
lcu_init <= '1';
@@ -535,7 +544,9 @@ BEGIN
GENERIC MAP (
g_technology => g_technology_dut,
g_cross_clock_domain => c_cross_clock_domain,
- g_frm_discard_en => g_frm_discard_en
+ g_frm_discard_en => g_frm_discard_en,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level
)
PORT MAP (
-- Clocks and reset
@@ -570,6 +581,12 @@ BEGIN
);
lcu : ENTITY tech_tse_lib.tech_tse
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_sim_tx => TRUE,
+ g_sim_rx => TRUE
+ )
PORT MAP (
-- Clocks and reset
mm_rst => mm_rst,
@@ -619,6 +636,10 @@ BEGIN
rx_timeout <= rx_timeout + 1;
IF lcu_rx_sosi.valid='1' THEN
rx_timeout <= 0;
+ ELSIF rx_pkt_cnt>0 THEN
+ IF tx_pkt_cnt=rx_pkt_cnt + rx_pkt_discarded_cnt + TO_UINT(rx_pkt_flushed_cnt) THEN
+ rx_end <= '1'; -- do not wait for rx_timeout if all expected packets have been received
+ END IF;
ELSIF rx_timeout>5000 THEN -- sufficiently large value determined by trial
rx_end <= '1';
END IF;
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
index 86527014f8420484d39d6edf38b0fb6007c0b2d8..e3339f2fabef00d36a8b3ae8ee3aa645335f6154 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
@@ -53,6 +53,8 @@ BEGIN
-- g_technology_dut : NATURAL := c_tech_select_default;
-- g_technology_lcu : NATURAL := c_tech_select_default;
+-- g_sim : BOOLEAN := FALSE;
+-- g_sim_level : NATURAL := 0; -- when g_sim = TRUE, then 0 = use IP; 1 = use fast serdes model
-- g_frm_discard_en : BOOLEAN := TRUE; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
-- g_flush_test_en : BOOLEAN := FALSE; -- when TRUE send many large frames to enforce flush in eth_buffer
-- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
@@ -63,12 +65,13 @@ BEGIN
-- -- g_data_type = c_tb_tech_tse_data_type_udp = 4
-- g_data_type : NATURAL := c_tb_tech_tse_data_type_udp
- u_use_symbols : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_symbols) PORT MAP (tb_end_vec(0));
- u_use_counter : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_counter) PORT MAP (tb_end_vec(1));
- u_use_arp : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_arp ) PORT MAP (tb_end_vec(2));
- u_use_ping : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_ping ) PORT MAP (tb_end_vec(3));
- u_use_udp : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(4));
- u_use_udp_flush : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, TRUE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(5));
+ u_use_symbols : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, 0, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_symbols) PORT MAP (tb_end_vec(0));
+ u_use_counter : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, 0, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_counter) PORT MAP (tb_end_vec(1));
+ u_use_arp : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, 0, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_arp ) PORT MAP (tb_end_vec(2));
+ u_use_ping : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, 0, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_ping ) PORT MAP (tb_end_vec(3));
+ u_use_udp_0 : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, 0, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(4));
+ u_use_udp_1 : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, 1, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(5));
+ u_use_udp_flush : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, 1, TRUE, TRUE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(6));
tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
diff --git a/libraries/technology/tse/hdllib.cfg b/libraries/technology/tse/hdllib.cfg
index 72a5ce131ed6b2709cd31234ac31e6f8831a3181..16e4ca1d98ab05f818c7883830d9f5e52afa986a 100644
--- a/libraries/technology/tse/hdllib.cfg
+++ b/libraries/technology/tse/hdllib.cfg
@@ -35,9 +35,10 @@ test_bench_files =
sim_tse.vhd
tb_tech_tse_pkg.vhd
tb_tech_tse.vhd
+ tb_tb_tech_tse.vhd
regression_test_vhdl =
- tb_tech_tse.vhd
+ tb_tb_tech_tse.vhd
[modelsim_project_file]
diff --git a/libraries/technology/tse/sim_tse.vhd b/libraries/technology/tse/sim_tse.vhd
index 9ae20025277303acf57013b3d96e0796e6c639c6..425729e11a0e5d0ece6791b3efc30c4a111096bc 100644
--- a/libraries/technology/tse/sim_tse.vhd
+++ b/libraries/technology/tse/sim_tse.vhd
@@ -23,9 +23,15 @@
-- Author:
-- . Daniel van der Schuur
-- Purpose:
--- . Drop-in simulation model for tech_tse.vhd.
+-- . Drop-in behavioral simulation model for tech_tse.vhd.
-- Description:
--- . Basically just a wrapper around sim_tse.
+-- . The simulation model is based on tech_transceiver_lib.sim_transceiver_gx
+-- and is about a factor 4 faster than the IP simulation model.
+-- Remark:
+-- . Default use g_tx_crc=TRUE, to model TSE IP in ETH on UniBoard1, UniBoard2
+-- . Connect eth_txp/eth_rxp directly to host rxp/txp without a TRANSPORT delay,
+-- because the sim_transceiver_gx model requries that both sides of a link
+-- are in phase.
LIBRARY IEEE, common_lib, dp_lib, tech_transceiver_lib;
USE IEEE.std_logic_1164.ALL;
@@ -37,6 +43,7 @@ USE work.tech_tse_pkg.ALL;
ENTITY sim_tse IS
GENERIC(
g_tx : BOOLEAN;
+ g_tx_crc : BOOLEAN := TRUE; -- model append CRC by TSE MAC, CRC value = 0
g_rx : BOOLEAN
);
PORT(
@@ -77,17 +84,34 @@ END sim_tse;
ARCHITECTURE str OF sim_tse IS
+ CONSTANT c_crc_sz : NATURAL := 4; -- CRC word has 4 octets
+
SIGNAL tr_clk : STD_LOGIC;
SIGNAL tr_rst : STD_LOGIC;
SIGNAL tx_snk_rst : STD_LOGIC;
SIGNAL rx_src_rst : STD_LOGIC;
- SIGNAL sim_transceiver_gx_tx_snk_in_arr : t_dp_sosi_arr(0 DOWNTO 0);
- SIGNAL sim_transceiver_gx_tx_snk_out_arr : t_dp_siso_arr(0 DOWNTO 0);
+ SIGNAL tx_fifo_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL tx_fifo_siso : t_dp_siso := c_dp_siso_hold;
+
+ TYPE t_reg IS RECORD
+ crc_sosi : t_dp_sosi;
+ crc_cnt : NATURAL RANGE 0 TO c_crc_sz;
+ END RECORD;
+
+ SIGNAL crc_siso : t_dp_siso := c_dp_siso_hold;
+ SIGNAL r : t_reg;
+ SIGNAL nxt_r : t_reg;
+
+ SIGNAL tx_pkt_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL tx_pkt_siso : t_dp_siso := c_dp_siso_hold;
+
+ SIGNAL gx_tx_snk_in_arr : t_dp_sosi_arr(0 DOWNTO 0);
+ SIGNAL gx_tx_snk_out_arr : t_dp_siso_arr(0 DOWNTO 0);
- SIGNAL sim_transceiver_gx_rx_src_out_arr : t_dp_sosi_arr(0 DOWNTO 0);
- SIGNAL sim_transceiver_gx_rx_src_in_arr : t_dp_siso_arr(0 DOWNTO 0);
+ SIGNAL gx_rx_src_out_arr : t_dp_sosi_arr(0 DOWNTO 0);
+ SIGNAL gx_rx_src_in_arr : t_dp_siso_arr(0 DOWNTO 0);
BEGIN
@@ -123,10 +147,95 @@ BEGIN
snk_in => tx_snk_in,
snk_out => tx_snk_out,
- src_out => sim_transceiver_gx_tx_snk_in_arr(0),
- src_in => sim_transceiver_gx_tx_snk_out_arr(0)
+ src_out => tx_fifo_sosi,
+ src_in => tx_fifo_siso
);
+ no_tx_crc : IF NOT g_tx_crc GENERATE
+ gx_tx_snk_in_arr(0) <= tx_fifo_sosi;
+ tx_fifo_siso <= gx_tx_snk_out_arr(0);
+ END GENERATE;
+
+ gen_tx_crc : IF g_tx_crc GENERATE
+ -----------------------------------------------------------------------------
+ -- Model Tx CRC by appending four zero octets at end of Tx packet
+ -----------------------------------------------------------------------------
+ --
+ -- The p_crc_comb implementation is based on the following timing diagram:
+ -- _ _ _ _ _ _ _ _ _
+ -- tr_clk _| |_| |_| |_| |_| |_| |_| |_| |_|
+ -- ___________________________________
+ -- tx_fifo_siso.ready
+ -- _________
+ -- tx_fifo_sosi.valid |_________________________
+ -- ___
+ -- tx_fifo_sosi.eop _____| |_________________________
+ -- _____ _____________
+ -- crc_siso.ready |_______________|
+ -- _______________
+ -- crc_sosi.valid _________| |_________
+ -- ___
+ -- crc_sosi.eop _____________________| |_________
+ --
+ -- crc_cnt | 0 | 0 | 1 | 2 | 3 | 0 | 0 | 0 |
+ -- _________________________
+ -- tx_pkt_sosi.valid |_________
+ -- ___
+ -- tx_pkt_sosi.eop _____________________| |_________
+ --
+
+ tx_fifo_siso.ready <= tx_pkt_siso.ready AND crc_siso.ready;
+
+ p_tx_pkt_sosi : PROCESS(tx_fifo_sosi, r)
+ BEGIN
+ -- start with tx_fifo_sosi packet
+ tx_pkt_sosi <= tx_fifo_sosi;
+ -- append CRC = 0 at end of tx_fifo_sosi packet
+ IF r.crc_sosi.valid = '1' THEN
+ tx_pkt_sosi.data <= TO_DP_DATA(0);
+ END IF;
+ tx_pkt_sosi.valid <= tx_fifo_sosi.valid OR r.crc_sosi.valid;
+ tx_pkt_sosi.eop <= r.crc_sosi.eop;
+ END PROCESS;
+
+ p_crc_comb : PROCESS(tx_fifo_sosi, r)
+ VARIABLE v : t_reg;
+ BEGIN
+ crc_siso.ready <= '1';
+ v := r;
+ v.crc_sosi.valid := '0';
+ v.crc_sosi.eop := '0';
+ IF tx_fifo_sosi.eop = '1' THEN
+ crc_siso.ready <= '0';
+ v.crc_sosi.valid := '1';
+ v.crc_cnt := 1;
+ END IF;
+ IF r.crc_cnt > 0 THEN
+ crc_siso.ready <= '0';
+ v.crc_sosi.valid := '1';
+ v.crc_cnt := r.crc_cnt + 1;
+ END IF;
+ IF r.crc_cnt = c_crc_sz-1 THEN
+ v.crc_sosi.eop := '1';
+ v.crc_cnt := 0;
+ END IF;
+ nxt_r <= v;
+ END PROCESS;
+
+ p_crc_reg : PROCESS(tr_rst, tr_clk)
+ BEGIN
+ IF tr_rst = '1' THEN
+ r <= (c_dp_sosi_rst, 0);
+ ELSIF rising_edge(tr_clk) THEN
+ r <= nxt_r;
+ END IF;
+ END PROCESS;
+
+ gx_tx_snk_in_arr(0) <= tx_pkt_sosi;
+ tx_pkt_siso <= gx_tx_snk_out_arr(0);
+
+ END GENERATE;
+
-------------------------------------------------------------------------------
-- Transceiver sim model
-- . Inside this model, tr_clk = tx_clk = rx_clk. We're using its output
@@ -148,13 +257,13 @@ BEGIN
tx_clk(0) => tr_clk,
tx_rst(0) => tr_rst,
- tx_sosi_arr => sim_transceiver_gx_tx_snk_in_arr,
- tx_siso_arr => sim_transceiver_gx_tx_snk_out_arr,
+ tx_sosi_arr => gx_tx_snk_in_arr,
+ tx_siso_arr => gx_tx_snk_out_arr,
tx_dataout(0) => eth_txp,
rx_datain(0) => eth_rxp,
- rx_sosi_arr => sim_transceiver_gx_rx_src_out_arr,
- rx_siso_arr => sim_transceiver_gx_rx_src_in_arr
+ rx_sosi_arr => gx_rx_src_out_arr,
+ rx_siso_arr => gx_rx_src_in_arr
);
-------------------------------------------------------------------------------
@@ -186,8 +295,8 @@ BEGIN
rd_rst => rx_src_rst,
rd_clk => rx_src_clk,
- snk_in => sim_transceiver_gx_rx_src_out_arr(0),
- snk_out => sim_transceiver_gx_rx_src_in_arr(0),
+ snk_in => gx_rx_src_out_arr(0),
+ snk_out => gx_rx_src_in_arr(0),
src_out => rx_src_out,
src_in => rx_src_in
diff --git a/libraries/technology/tse/tb_tb_tech_tse.vhd b/libraries/technology/tse/tb_tb_tech_tse.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1ad6cdc0e6456d141e36ab00fa3a90029ba03c6b
--- /dev/null
+++ b/libraries/technology/tse/tb_tb_tech_tse.vhd
@@ -0,0 +1,73 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Multi-testbench for tech_tse
+-- Description:
+-- Verify tech_tse for different data types
+-- Usage:
+-- > as 3
+-- > run -all
+
+LIBRARY IEEE, technology_lib, tech_tse_lib;
+USE IEEE.std_logic_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+
+
+ENTITY tb_tb_tech_tse IS
+END tb_tb_tech_tse;
+
+
+ARCHITECTURE tb OF tb_tb_tech_tse IS
+
+ CONSTANT c_tech : NATURAL := c_tech_select_default;
+
+ CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS=>'1');
+ SIGNAL tb_end_vec : STD_LOGIC_VECTOR(15 DOWNTO 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ SIGNAL tb_end : STD_LOGIC := '0';
+
+BEGIN
+
+-- g_technology : NATURAL := c_tech_select_default;
+-- -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
+-- -- g_data_type = c_tb_tech_tse_data_type_counter = 1
+-- g_data_type : NATURAL := c_tb_tech_tse_data_type_symbols;
+-- g_sim : BOOLEAN := TRUE;
+-- g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model;
+-- g_tb_end : BOOLEAN := TRUE -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+
+ u_ip : ENTITY work.tb_tech_tse GENERIC MAP (c_tech, c_tb_tech_tse_data_type_symbols, FALSE, 0, FALSE) PORT MAP (tb_end_vec(0));
+ u_sim_level_0 : ENTITY work.tb_tech_tse GENERIC MAP (c_tech, c_tb_tech_tse_data_type_symbols, TRUE, 0, FALSE) PORT MAP (tb_end_vec(1));
+ u_sim_level_1 : ENTITY work.tb_tech_tse GENERIC MAP (c_tech, c_tb_tech_tse_data_type_symbols, TRUE, 1, FALSE) PORT MAP (tb_end_vec(2));
+
+ tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
+
+ p_tb_end : PROCESS
+ BEGIN
+ WAIT UNTIL tb_end='1';
+ WAIT FOR 1 ns;
+ REPORT "Multi tb simulation finished." SEVERITY FAILURE;
+ WAIT;
+ END PROCESS;
+END tb;
diff --git a/libraries/technology/tse/tb_tech_tse.vhd b/libraries/technology/tse/tb_tech_tse.vhd
index 70e680667963218ca7ba41abaed4edbf96dae500..ce074ce5673c8b798bdc26a7f934adb1e5cebddd 100644
--- a/libraries/technology/tse/tb_tech_tse.vhd
+++ b/libraries/technology/tse/tb_tech_tse.vhd
@@ -48,7 +48,13 @@ ENTITY tb_tech_tse IS
g_technology : NATURAL := c_tech_select_default;
-- g_data_type = c_tb_tech_tse_data_type_symbols = 0
-- g_data_type = c_tb_tech_tse_data_type_counter = 1
- g_data_type : NATURAL := c_tb_tech_tse_data_type_symbols
+ g_data_type : NATURAL := c_tb_tech_tse_data_type_symbols;
+ g_sim : BOOLEAN := TRUE;
+ g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model;
+ g_tb_end : BOOLEAN := TRUE -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ );
+ PORT (
+ tb_end : OUT STD_LOGIC
);
END tb_tech_tse;
@@ -60,7 +66,7 @@ ARCHITECTURE tb OF tb_tech_tse IS
CONSTANT sys_clk_period : TIME := 10 ns; -- 100 MHz
CONSTANT eth_clk_period : TIME := 8 ns; -- 125 MHz
- CONSTANT cable_delay : TIME := 12 ns;
+ CONSTANT cable_delay : TIME := sel_a_b(g_sim_level=0, 12 ns, 0 ns);
CONSTANT c_promis_en : BOOLEAN := FALSE;
CONSTANT c_tx_ready_latency : NATURAL := c_tech_tse_tx_ready_latency; -- 0, 1 are supported, must match TSE MAC c_tech_tse_tx_ready_latency
@@ -84,7 +90,6 @@ ARCHITECTURE tb OF tb_tech_tse IS
-- Clocks and reset
SIGNAL rx_end : STD_LOGIC := '0';
- SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL eth_clk : STD_LOGIC := '0'; -- tse reference clock
SIGNAL sys_clk : STD_LOGIC := '0'; -- system clock
SIGNAL st_clk : STD_LOGIC; -- stream clock
@@ -214,7 +219,9 @@ BEGIN
dut : ENTITY work.tech_tse
GENERIC MAP (
g_technology => g_technology,
- g_ETH_PHY => "LVDS" -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+ g_ETH_PHY => "LVDS", -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+ g_sim => g_sim,
+ g_sim_level => g_sim_level -- 0 = use IP; 1 = use fast serdes model;
)
PORT MAP (
-- Clocks and reset
@@ -259,6 +266,7 @@ BEGIN
p_verify : PROCESS
BEGIN
+ tb_end <= '0';
WAIT UNTIL rx_end='1';
-- Verify that all transmitted packets have been received
IF tx_pkt_cnt=0 THEN
@@ -269,14 +277,13 @@ BEGIN
REPORT "Not all transmitted packets were received." SEVERITY ERROR;
END IF;
tb_end <= '1';
- WAIT;
- END PROCESS;
-
- p_tb_end : PROCESS
- BEGIN
- WAIT UNTIL tb_end='1';
+
WAIT FOR 1 ns;
- REPORT "Simulation finished." SEVERITY FAILURE;
+ IF g_tb_end=FALSE THEN
+ REPORT "Tb simulation finished." SEVERITY NOTE;
+ ELSE
+ REPORT "Tb simulation finished." SEVERITY FAILURE;
+ END IF;
WAIT;
END PROCESS;
diff --git a/libraries/technology/tse/tech_tse.vhd b/libraries/technology/tse/tech_tse.vhd
index 2afb13310bedc7f45b639377ae86dce758164165..8f9ef2a1969d0ad8969015e3149699b40944e757 100644
--- a/libraries/technology/tse/tech_tse.vhd
+++ b/libraries/technology/tse/tech_tse.vhd
@@ -34,7 +34,7 @@ ENTITY tech_tse IS
g_technology : NATURAL := c_tech_select_default;
g_ETH_PHY : STRING := "LVDS"; -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
g_sim : BOOLEAN := FALSE;
- g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model;
+ g_sim_level : NATURAL := 0; -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
g_sim_tx : BOOLEAN := TRUE;
g_sim_rx : BOOLEAN := TRUE
);